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0HITACHI® IC MEMORY DATA BOOK 




IC MEMORY 
DATA BOOK 



#M11.1 



^HITACHI 9 



CS-E410T 



When using this document, keep the following in mind: 

1. This document may, wholly or partially, be subject to change without 
notice. 

2. All rights are reserved: No one is permitted to reproduce or duplicate, in 
any form, the whole or part of this document without Hitachi's permission. 

3. Hitachi will not be held responsible for any damage to the user that may 
result from accidents or any other reasons during operation of the user's 
unit according to this document. 

4. Circuitry and other examples described herein are meant merely to indi- 
cate the characteristics and performance of Hitachi's semiconductor prod- 
ucts. Hitachi assumes no responsibility for any intellectual property claims 
or other problems that may result from applications based on the examples 
described herein. 

5. No license is granted by implication or otherwise under any patents or 
other rights of any third party or Hitachi, Ltd. 

6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for 
use in MEDICAL APPLICATIONS without the written consent of the 
appropriate officer of Hitachi's sales company. Such use includes, but is 
not limited to, use in life support systems. Buyers of Hitachi's products are 
requested to notify the relevant Hitachi sales offices when planning to use 
the products in MEDICAL APPLICATIONS. 



January 1990 



® Copyright 1990, Hitachi America. Ltd. 



Printed in U.S.A. 



INTRODUCTION 

MOS Static RAM 

Cache Static RAM and 
Fast SRAM Modules 

MOS Pseudo Static RAM 

Video Memory 

MOS Dynamic RAM 

MOS Dynamic RAM Module 

MOS Mask ROM 

MOS PROM 
ECL RAM 

HITACHI SALES OFFICES SECTION 9, PAGE 1302 
HITACHI 

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<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



TABLE OF CONTENTS 



TABLE OF CONTENTS 

Introduction Page 

QUICK REFERENCE GUIDE xiii 

PACKAGE INFORMATION 1 

RELIABILITY OF HITACHI I.C. MEMORIES 13 

QUALITY ASSURANCE OF I.C. MEMORY 28 

OUTLINE OF TESTING METHOD 34 

APPLICATION 35 

Section 1 

MOS Static Ram 

• HM6116 SERIES 2,048-word x 8-bit High Speed CMOS Static RAM 64 

HM6116P-2/3/4 
HM6116LP-2/3/4 
HM6116FP-2/3/4 
HM6116LFP-2/3/4 

• HM6116A SERIES 2,048-word x 8-bit High Speed Static CMOS RAM 69 

HM6116AP-12/15/20 
HM6116ALP-12/15/20 
HM6116ASP-12/15/20 
HM6116ALSP-12/15/20 

• HM6716 SERIES 2,048-word x 8-bit High Speed Hi-BiCMOS Static RAM (with OE). . . 74 

HM6716P-25/30 

• HM6719 SERIES 2,048-word x 9-bit High Speed Hi-BiCMOS Static RAM (with OE). . . 74 

HM6719P-25/30 

• HM6268 SERIES 4,096-word x 4-bit High Speed CMOS Static RAM 80 

HM6268P-25/35/45 
HM6268LP-25/35/45 

• HM6267 SERIES 16,384-word x 1-bit High Speed CMOS Static RAM 87 

HM6267P-35/45/55 
HM6267LP-35/45/55 

• HM6264A SERIES 8,192-word x 8-bit High Speed CMOS Static RAM : . 94 

HM6264AP-10/12/15 

HM6264ALP-10/12/15 

HM6264ALP-10L/12L/15L 

HM6264ASP-10/12/15 

HM6264ALSP-10/12/15 

HM6264ALSP-10L/12L/15L 

HM6264AFP-10/12/15 

HM6264ALFP-10/12/15 

HM6264ALFP-10L/12L/15L 

• HM6288 SERIES 16,384-word x 4-bit High Speed CMOS Static RAM 103 

HM6288P-25/35 
HM6288LP-25/35 
HM6288JP-25/35 
HM6288LJP-25/35 

• HM6788 SERIES 16,384-word x 4-bit High Speed Hi-BiCMOS Static RAM 111 

HM6788P-25/30 

• HM6788H SERIES 16,384-word x 4-bit High Speed Hi-BiCMOS Static RAM 115 

HM6788HP-15/20 

• HM6788HA SERIES 16,384-word x 4-bit High Speed Static RAM 119 

HM6788HAP-12/15/20 

• HM6289 SERIES 16,384-word x 4-bit High Speed CMOS Static RAM (with OE) 124 

HM6289JP-25/35 
HM6289LJP-25/35 



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TABLE OF CONTENTS 



Section 1— MOS Static Ram (continued) Page 

• HM6789 SERIES 16,384-word x 4-bit High Speed Hi-BiCMOS Static RAM (with OE). . 135 

HM6789P-25/30 
HM6789JP-25/30 

• HM6789H SERIES 16,384-word x 4-bit High Speed Hi-BiCMOS Static RAM (with OE). . 142 

HM6789HP-15/20 
HM6789HJP-15/20 

• HM6789HA SERIES 16,384-word x 4-bit High Speed Static RAM (with OE) 149 

HM6789HAP-12/15/20 
HM6789HAJP-12/15/20 

• HM6287 SERIES 65,536-word x 1-bit High Speed CMOS Static RAM 157 

HM6287P-45/55/70 
HM6287LP-45/55/70 

• HM6287H SERIES 65,536-word x 1 -bit High Speed CMOS Static RAM 164 

HM6287HP-25/35 
HM6287HLP-25/35 
HM6287HJP-25/35 
HM6287HLJP-25/35 

• HM6787 SERIES 65,536-word x 1-bit High Speed Hi-BiCMOS Static RAM 173 

HM6787P-25/30 

• HM6787H SERIES 65,536-word x 1-bit High Speed Hi-BiCMOS Static RAM 178 

HM6787HP-15/20 
HM6787HJP-15/20 

• HM6787HA SERIES 65,536-word x 1 -bit High Speed Static RAM 183 

HM6787HAP-12/15/20 
HM6787HAJP-12/15/20 

• HM62256 SERIES 32,768-word x 8-bit High Speed CMOS Static RAM 189 

HM62256P-8/10/12/15 

HM62256LP-8/10/12/15 

HM62256LP-10SL/12SL/15SL 

HM62256FP-8T/10T/12T/15T 

HM62256LFP-8T/10T/12T/15T 

HM62256LFP-8SLT/10SL.T/12SLT/15SLT 

• HM62832/HM62832H 32,768-word x 8-bit High Speed CMOS Static RAM 197 

HM62832P-35/45 

HM62832LP-35/45 

HM62832JP-35/45 

HM62832LJP-35/45 

HM62832HP-35/45 

HM62832HJP-35/45 

• HM6208/HM6208H SERIES 65,536-word x 4-bit High Speed CMOS Static RAM 203 

HM6208P-35/45 

HM6208HP-25/35 

HM6208HLP-25/35 

HM6208HJP-25/35 

HM6208HLJP-25/35 

• HM6708 SERIES 65,536-word x 4-bit High Speed Hi-BiCMOS Static RAM 211 

HM6708P-20/25 
HM6708JP-20/25 

• HM6708A SERIES 65,536-word x 4-bit High Speed Static RAM 217 

HM6708AP-15/20/25 
HM6708AJP-15/20/25 

• HM6709 SERIES 65,536-word x 4-bit High Speed Static RAM (with OE) 222 

HM6709JP-20/25 

• HM6709A SERIES 65,536-word x 4-bit High Speed Static RAM (with OE) 229 

HM6709AP-15/20/25 
HM6709AJP-15/20/25 



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TABLE OF CONTENTS 



Section 1— MOS Static Ram (continued) Page 

• HM6207 SERIES 262,144-word x 1-bit High Speed CMOS Static RAM 236 

HM6207P-35/45 
HM6207LP-35/45 

• HM6207H SERIES 262,144-word x 1-bit High Speed CMOS Static RAM 243 

HM6207P-35/45 

HM6207HP-25/35 

HM6207HLP-25/35 

HM6207HJP-25/35 

HM6207HUP-25/35 

• HM6707 SERIES 262,144-word x 1-bit High Speed Hi-BiCMOS Static RAM 250 

HM6707P-20/25 
HM6707JP-20/25 

• HM6707A SERIES 262,144-word x 1-bit High Speed Static RAM 255 

HM6707AP-15/20/25 
HM6707AJP-15/20/25 

• HM628128 SERIES 131,072-word x 8-bit High Speed CMOS Static RAM 261 

HM628128P-7/8/10/12 
HM628128LP-7/8/10/12 
HM628128FP-7/8/10/12 
HM628128LFP-7/8/10/12 

• HM624256 SERIES 262,144-word x 4-bit High Speed CMOS Static RAM 269 

HM624256P-35/45 
HM624256LP-35/45 
HM624256JP-35/45 
HM624256LJP-35/45 

• HM624257 SERIES 262,144-word x 4-bit High Speed CMOS Static RAM 275 

HM624257JP-35/45 
HM624257LJP-35/45 

• HM66204 SERIES 131,072-word x 8-bit High Density CMOS Static RAM Module 283 

HM66204-12/15 
HM66204L-12/15 

• HM63921 -20/25/35 2K x 9-bit CMOS Parallel In-Out FIFO Memory 289 

HM63921P-20/25/35 

• HM63941 -25/35/45 4K x 9-bit CMOS Parallel In-Out FIFO Memory 301 

HM63941 P-25/35/45 

Section 2 

Cache Static RAM and Fast SRAM Modules 

• HM62A168/HM62A188 SERIES Direct Mapped 8,192-word x 16/18-bit 2-way 311 

HM62168CP-25/35/45 4,096-word x 16/18-bit Static Cache RAM 

HM62188CP-25/35/45 

• HM67C932 SERIES 8,192-word x 9-bit x 4-row Static Cache RAM 319 

HM67C932CP-20/25 

• HB66B1616A-25/35 16,384-word x 16-bit High Speed Static RAM Module 333 

HB66B1616A-25/35 

• HB66A2568A-25/35 262,144-word x 8-bit High Speed Static RAM Module 343 

HB66A2568A-25/35 

• HM644332 2,048 Entry Tag Memory 351 

HM644332G-25/30 

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TABLE OF CONTENTS 
Section 3 

MOS Pseudo Static RAM Page 

• HM65256B SERIES 32,768-word x 8-bit High Speed Pseudo Static RAM 369 

HM65256BP-10/12/15/20 

HM65256BLP-10/12/15/20 

HM65256BSP-10/12/15/20 

HM65256BLSP-10/12/15/20 

HM65256BFP-10T/12T/15T/20T 

HM65256BLFP-10T/12T/15T/20T 

• HM658128 SERIES 131,072-word x 8-bit High Speed CMOS Pseudo Static RAM 376 

HM658128DP-10/12/15 
HM658128LP-10/12/15 
HM658128DFP-10/12/15 
HM658128LFP-10/12/15 

Section 4 
Video Memory 

• HM63021 SERIES 2,048-word x 8-bit Line Memory 388 

HM63021P-28/34/45 

• HM53051P 262,144-word x 4-bit Frame Memory 402 

HM53051P-45/60 

• HM53461 SERIES 65,536-word x 4-bit Multiport CMOS Video RAM 412 

HM53461P-10/12/15 
HM53461ZP-10/12/15 

• HM53462 SERIES 65,536-word x 4-bit Multiport CMOS Video RAM 425 

HM53462P-10/12/15 (with Logic operation mode) 

HM53462ZP-10/12/15 

• HM538122 SERIES 131,072-word x 8-bit Multiport CMOS Video RAM 444 

HM538122JP-10/12/15 

• HM538123 SERIES 131,072-word x 8-bit Multiport CMOS Video RAM 470 

HM538123JP-10/12/15 

• HM534251 SERIES 262,144-word x 4-bit Multiport CMOS Video RAM 469 

HM534251JP-10/11/12/15 
HM534251ZP-10/11/12/15 

• HM534252 SERIES 262,144-word x 4-bit Multiport CMOS Video RAM 516 

HM534252JP-10/11/12/15 
HM534252ZP-10/11/12/15 

• HM534253 SERIES 262,144-word x 4-bit Multiport CMOS Video RAM 542 

HM534253JP-10/12/15 
HM534253ZP-10/12/15 

• HM538121JP/ZP-10/12/15 131,072 x 8-bit Multiport CMOS Video Random Access Memory ... 569 

HM538121JP-10/12/15 

Sections 

MOS Dynamic RAM 

• HM50464 SERIES 65,536-word x 4-bit Dynamic Random Access Memory 590 

HM50464P-12/15/20 
HM50464CP-12/15/20 

• HM50256 SERIES 262,144-word x 1 -bit Dynamic Random Access Memory 598 

HM50256P-12/15/20 

HM50256ZP-12/15/20 

HM50256CP-12/15/20 

• HM51256 SERIES 262,144-word x 1-bit Dynamic Random Access Memory I. . . 606 

HM51256P-8/10/12/15 

HM51256CP-8/10/12/15 

HM51256LP-8/10/12/15 

HM51256LCP-8/10/12/15 

HM51256ZP-8/10/12/15 

HM51256LZP-8/10/12/15 



<§> HITACHI 

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TABLE OF CONTENTS 



Section 5— MOS Dynamic RAM (continued) Page 

• HM51258 SERIES 262,144-word x 1 -bit Static Column CMOS Dynamic RAM 614 

HM51258P-8/10/12/15 

• HM514256 SERIES 262,144-word x 4-bit CMOS Dynamic RAM 623 



HM514256P-8/10/12 
HM514256JP-8/10/12 
HM514256ZP-8/10/12 

• HM514256S/HM514256A SERIES 

HM514256P-8S/10S/12S 
HM514256JP-8S/10S/12S 
HM514256ZP-8S/10S/12S 
HM514256AP-8/10/12 
HM514256AJP-8/10/12 
HM514256AZP-8/10/12 

• HM514256API/AJPI/AZPI-6/7/8/10/12 262,144-word x 4-bit Dynamic Random Access Memory 651 

(EXTENDED TEMPERATURE 

RANGE VERSION) 

HM514256API-6/7/8/10/12 
HM514256AJPI-6/7/8/10/12 
HM51 4256AZPI-6/7/8/1 0/1 2 

• HM514256ALP/ALJP/ALZP-8/10/12 262,144-word x 4-bit Dynamic Random Access Memory 667 

HM514256ALP-8/10/12 
HM514256ALJP-8/10/12 
HM514256ALZP-8/10/12 

• HM514256H SERIES 

HM514256HP-6/7 
HM514256HJP-6/7 
HM514256HZP-6/7 

• HM514258S/HM514258A SEI 

HM514258P-8S/10S/12S 
HM514258JP-8S/10S/12S 
HM514258ZP-8S/10S/12S 
HM514258AP-8/10/12 
HM514258AJP-8/10/12 
HM514258AZP-8/10/12 

• HM514266AP/AJP/AZP-6/7/8/10/12 262,144-word x 4-bit Dynamic Random Access Memory 71 1 

HM514266AP-6/7/8/10/12 

HM514266AJP-6/7/8/10/12 

HM514266AZP-6/7/8/10/12 

• HM511000S/HM511000A SERIES 1,048,576-word x 1 -bit CMOS Dynamic RAM 725 

HM511000P-8S/10S/12S 

HM511000JP-8S/10S/12S 

HM511000ZP-8S/10S/12S 

HM511000AP-8/10/12 

HM511000AJP-8/10/12 

HM5110O0AZP-8/10/12 

• HM511000ALP/ALJP/ALZP-8/10/12 1,048,576-word x 1-bit Dynamic Random Access Memory 737 

HM51100OALP-8/10/12 

HM511000ALJP-8/10/12 

HM511000ALZP-8/10/12 

• HM511000H SERIES 1,048,576-word x 1-bit CMOS Dynamic RAM 751 

HM511000HP-6/7 

HM5110O0HJP-6/7 

HM511000HZP-6/7 

• HM511001S SERIES 1,048,576-word x 1 -bit CMOS Dynamic RAM 762 

HM511001P-8S/10S/12S 

HM511001JP-8S/10S/12S 

HM511001ZP-8S/10S/12S 



262,144-word x 4-bit CMOS Dynamic RAM 635 



262,144-word x 4-bit CMOS Dynamic RAM 682 



=ilES 262,144-word x 4-bit CMOS Dynamic RAM 696 



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v 



TABLE OF CONTENTS 



Section 5— MOS Dynamic RAM (continued) Page 

• HM511001 A SERIES 1,048,576-word x 1 -bit CMOS Dynamic RAM 773 

HM511001AP-8/10/12 

HM511001AJP-8/10/12 

HM511001AZP-8/10/12 

• HM571000JP-35R/40/45 1,048,576-word x 1 -bit (BiCMOS) Memory 785 

HM571000JP-35R/40/45 

• HM574256JP-35R/40/45 262,144-word x 4-bit (BiCMOS) 803 

HM574256JP-35R/40/45 

• HM511002S/HM511002A 1,048,576-word x 1 -bit CMOS Dynamic RAM 816 

HM511002P-8S/10S/12S 

HM511002JP-8S/10S/12S 

HM511002ZP-8S/10S/12S 

HM511002AP-8/10/12 

HM511002AJP-8/10/12 

HM511002AZP-8/10/12 

• HB56A18A/AT/B-6H/7H/8A/10A/12A 1,048,576-word x 8-bit High Density Dynamic RAM Module 831 

HB56A18A-6H/7H/8A/10A/12A 
HB56A18AT-6H/7H/8A/10A/12A 
HB56A1 8B-6H/7H/8A/1 0A/12A 

• HB56C18A/AT/B-8A/10A/12A 1,048,576-word x 8-bit High Density Dynamic RAM Module 837 

HB56C18A-8A/10A/12A 

HB56C18AT-8A/10A/12A 

HB56C18B-8A/10A/12A 

• HB56A19A/AT/B-6H/7H/8A/10A/12A 1,048,576-word x 9-bit High Density Dynamic RAM Module 843 

HB56A19A-6H/7H/8A/10A/12A 

HB56A19AT-6H/7H/8A/10A/12A 

HB56A19B-6H/7H/8A/10A/12A 

• HB56C19A/AT/B-8A/10A/12A 1,048,576-word x 9-bit High Density Dynamic RAM Module 849 

HB56C19A-8A/10A/12A 

HB56C19AT-8A/10A/12A 

HB56C19B-8A/10A/12A 

• HM514100JP/ZP-8/10/12 4,194,304-word x 1 -bit Dynamic Random Access Memory 855 

HM514100JP-8/10/12 
HM514100ZP-8/10/12 

• HM514100JP/ZP-7 4,194,304-word x 1 -bit Dynamic Random Access Memory 869 

HM514100JP-7 
HM514100ZP-7 

• HM514100LJP/LZP-8/10/12 4,194,304-word x 1 -bit Dynamic Random Access Memory 883 

HM514100LJP-8/10/12 
HM514100LZP-8/10/12 

• HM514400JP/ZP-8/10/12 1,048,576-word x 4-bit Dynamic Random Access Memory 897 

HM514400JP-8/10/12 
HM514400ZP-8/10/12 

• HM514410JP/ZP-8/10/12 1,048,576-word x 4-bit Dynamic Random Access Memory 911 

HM514410JP-8/10/12 
HM514410ZP-8/10/12 

• HM514400LJP/LZP-8/10/12 1,048,576-word x 4-bit Dynamic Random Access Memory 931 

HM514400LJP-8/10/12 
HM514400LZP-8/10/12 



Section 6 

MOS Dynamic RAM Module 

• HB561003 SERIES 262,144-word x 9-bit Dynamic Random Access Memory Module . . . 954 

HB561003AR/B-12/15 

• HB561409 SERIES 262,144-word x 9-bit Dynamic Random Access Memory Module . . . 958 

HB561409A-10/B-10 



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TABLE OF CONTENTS 



Section 6— MOS Dynamic RAM Module (continued) Page 

• HB561008 SERIES 262,144-word x 8-bit Dynamic Random Access Memory Module . . , 963 

HB561008AR/B-12/B-15 

• HB56D25608A/B-6H/7H/8A/10A/12A 262,144-word x 8-bit High Density Dynamic RAM Module 967 

H B56D25608A-6H/7H/8A/1 OA/1 2A 
H B56D25608B-6H/7H/8A/10A/1 2A 

• HB56D25609A/B-85A/10A/12A 262,144-word x 9-bit High Density Dynamic RAM Module 979 

H B56D25609A-85A/1 OA/1 2A 
HB56D25609B-85A/10A/12A 

• HB56D25636B-85/10/12 262,144-word x 36-bit High Density Dynamic RAM Module 991 

• HB56D51236B-85/10/12 524,288-word x 36-bit High Density Dynamic RAM Module 1003 

• HB56A48A/AT/B-8/10/12 4,194,304-word x 8-bit High Density Dynamic RAM Module 1015 

HB56A48A-8/10/12 

HB56A48AT-8/10/12 

HB56A48B-8/10/12 

• HB56A49A/AT/B-8/10/12 4,194,304-word x 9-bit High Density Dynamic RAM Module 1027 

HB56A49A-8/10/12 

HB56A49AT-8/10/12 

HB56A49B-8/10/12 

• HB56D136B-8/10/12 1,048,576-word x 36-bit High Density Dynamic RAM Module 1039 

• HB56D236B-8/10/12 2,097,152-word x 36-bit High Density Dynamic RAM Module 1049 

Section 7 
MOS Mask ROM 

• HN623257R HN623257F 32,768-word x 8-bit CMOS Mask Programmable 1060 

HN623257P Read Only Memory 

HN623257F 

• HN623258R HN623258F 32,768-word x 8-bit CMOS Mask Programmable ROM 1063 

HN623258P 
HN623258F 

• HN62321/HN62331 SERIES 131,072-word x 8-bit CMOS Mask Programmable ROM 1066 

HN62321P 

HN62321BP 

HN62331P 

HN62321F 

HN62321BF 

HN62331F 

• HN62331AP/F 131,072-word x 8-bit CMOS Mask Programmable 1069 

HN62331AP Read Only Memory 

HN62331AF 

• HN62331P/F 131,072-word x 8-bit CMOS Mask Programmable 1073 

HN62331 P Read Only Memory 

HN62331F 

• HN62321E/HN62331E SERIES 131,072-word x 8-bit CMOS Mask Programmable ROM 1077 

HN62321EP 
HN62332EP 
HN62321EF 
HN62331EF 

• HN62321A/HN62331A SERIES 131,072-word x 8-bit CMOS Mask Programmable ROM 1080 

HN62321AP 
HN62331AP 
HN62321AF 
HN62331AF 

• HN62412/HN62422 SERIES 131,072-word x 16-bit/262,144-word x 8-bit CMOS 1083 

HN62412P Mask Programmable ROM 

HN62422P 



HITACHI 

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TABLE OF CONTENTS 

Section 7— MOS Mask ROM (continued) Page 

• HN62404/HN62424 SERIES 262,144-word x 16-bit/524,288-word x 8-bit CMOS 1087 

HN62404P Mask Programmable ROM 

HN62424P 

HN62404FP 

HN62424FP 

• HN62304B/HN62324B SERIES 524,288-word x 8-bit CMOS 1091 

HN62304BP Mask Programmable ROM 

HN62324BP 

HN62304BF 

HN62324BF 

• HN62444 SERIES 262,144-word x 16-bit/524,288-word x 8-bit CMOS 1095 

HN62444P Mask Programmable Read Only Memory 

HN62444FP 

HN62444F 

• HN62414 SERIES 262,144-word x 16-bit/524,288-word x 8-bit CMOS 1101 

HN62414P-17/20 Mask Programmable Read Only Memory 

HN62414FP-17/20 

HN62414F-17/20 

• HN62314B SERIES 524,288-word x 8-bit CMOS Mask Programmable Read Only Memory 1 107 

HN62314BP-17/20 
HN62314BF-17/20 

• HN62344B SERIES 524,288-word x 8-bit CMOS Mask Programmable Read Only Memory 1111 

HN62344BP 
HN62344BF 

• HN62408 SERIES 524,288-word x 16-bit/1,048,576-word x 8-bit CMOS 1114 

HN62408P Mask Programmable ROM 
HN62408FP 

• HN62308B SERIES 1 ,048,576-word x 8-bit CMOS Mask Programmable Read 1119 

HN62308BF 

• HN66403P SERIES 524,288-word x 16-bit/1 ,048,576-word x 8-bit CMOS 1123 

HN66403P Mask Programmable Read Only Memory 

• HN624016 SERIES 1,048,576-word x 16-bit/2,097,152-word x 8-bit CMOS 1127 

HN624016P Mask Programmable Read Only Memory 

HN624016F 

Section 8 
MOS PROM 

• HN58064 SERIES 8,192-word x 8-bit Electrically Erasable and Programmable ROM. . . 1132 

HN58064P-25/30 

• HN58C65 SERIES 8,192-word x 8-bit Electrically Erasable and Programmable 1138 

HN58C65P-25 CMOS ROM 
HN58C65FP-25 

• HN58C66 SERIES 8,192-word x 8-bit CMOS Electrically Erasable and 1147 

HN58C66P-25 Programmable ROM 
HN58C66FP-25 

• HN58C256 SERIES 32,768-word x 8-bit Electrically Erasable and Programmable 1156 

HN58C256P-15/20 CMOS ROM 
HN58C256FP-15/20 

• HN27C256AG SERIES 32,768-word x 8-bit UV Erasable and Programmable ROM 1 158 

HN27C256AG-10/12/15 

• HN27C256HG SERIES 32,768-word x 8-bit CMOS UV Erasable and Programmable ROM . . 1 1 66 

HN27C256HG-70/85 

• HN27512G SERIES 65,536-word x 8-bit UV Erasable and Programmable ROM 1176 

HN27512G-25/30 

• HN27C1024HG SERIES 65,536-word x 16-bit CMOS UV Erasable and Programmable ROM . 1183 

HN27C1024HG-85/10 



HITACHI 

viii Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



TABLE OF CONTENTS 



Section 8— MOS PROM (continued) Page 

• HN27C101G SERIES 131,072-word x 8-bit CMOS UV Erasable and Programmable ROM . . 1 192 

HN27C101G-17/20/25 

• HN27C301G SERIES 131,072-word x 8-bit CMOS UV Erasable and Programmable ROM . . 1200 

HN27C301G-17/20/25 

• HN27C256FP SERIES 32,768-word x 8-bit CMOS One Time Electrically 1209 

Programmable ROM 

• HN27512P SERIES 65,536-word x 8-bit One Time Electrically Programmable 1215 

HN27512P-25/30 Read Only Memory 

• HN27C101P/FP SERIES 131,072-word x 8-bit CMOS One Time 1222 

HN27C101 P-20/25 Electrically Programmable ROM 
HN27C101FP-20/25 

• HN27C301P/FP SERIES 131,072-word x 8-bit CMOS One Time 1229 

HN27C301 P-20/25 Electrically Programmable ROM 
HN27C301 FP-20/25 

• HN27C101AG SERIES 131,072-word x 8-bit CMOS UV Erasable and Programmable ROM . . 1237 
CMOS 1Mb EPROM 

• HN27C4096 SERIES 262,144-word x 16-bit CMOS UV Erasable and Programmable ROM . 1247 

HN27C4096G-10/12/15 
HN27C4096CC-10/12/15 

Section 9 
ECL RAM 

• HM10494 SERIES 16,384-word x 4-bit Fully Decoded Random Access Memory 1258 

HM10494-10/12 
HM10494F-10/12 

• HM10490 SERIES 65,536-word x 1-bit Fully Decoded Random Access Memory 1263 

HM10490-10/12 

• HM10504-10/12 65,536-word x 4-bit Fully Decoded Random Access Memory 1267 

• HM 10500-15 262,144-word x 1 -bit Fully Decoded Random Access Memory 1268 

• HM100494 SERIES 16,384-word x 4-bit Fully Decoded Random Access Memory 1273 

HM100494-10/12 
HM100494F-10/12 

• HM100490-10/12 65,536-word x 1-bit Fully Decoded Random Access Memory 1277 

• HM100504F-10/12 65,536-word x 4-bit Fully Decoded Random Access Memory 1281 

• HM100500 SERIES 262,144-word x 1-bit Fully Decoded Random Access Memory 1282 

HM100500-18 

HM100500CG-18 

HM100500F-18 

• HM101494 SERIES 16,384-word x 4-bit Fully Decoded Random Access Memory 1285 

HM101494-10/12 
HM101494F-10/12 

• HM101490-10/12 65,536-word x 1 -bit Fully Decoded Random Access Memory 1289 

• HM101504F-10/12 65,536-word x 4-bit Fully Decoded Random Access Memory 1293 

• HM101500F-15 262,144-word x 1 -bit Fully Decoded Random Access Memory 1294 

HITACHI SALES OFFICES 1302 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 ix 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



INTRODUCTION 

• Quick Reference 

to Hitachi LC. Memories 

• Package Information 

• Reliability of 
Hitachi LC. Memories 

• Quality Assurance of 
LC. Memory 

• Outline of Testing Method 

• Application 



HITACHI 



HITACHI 

Hitachi America Ltd. • 2210 O'Toole Ave. • San Jose, CA 95131 • (408)435-8300 



QUICK REFERENCE GUIDE TO HITACHI MEMORIES 



■ MOS RAM 



Type No. 


Process 


Organization 
(word x bit) 


Access 
Time 
(ns) 
Max 


Time 
(ns) 
Max 


Sum* 

m 


Power 
Dissipation 
(W) 


Package 


rage 






Pin No. 


G 


p 


FP 


SP 


ZP 


CG 


CP 


JP 






HM6116-2' 2 






120 


120 




0.1U1/0.2 






• 


• 














64 


HM6116-3' 2 






150 


150 




0.1m/0.175 






• 


• 














64 


HM6116-4-* 






200 


200 








• 


• 














64 


HM6116L-2'* 






120 


120 




10^0.175 






• 


• 














64 


HM6116L-3 - 2 






150 


150 




10fi/0.15 






• 


• 














64 


HM6116L-4-2 


CMOS 


2048x8 


200 


200 








• 


• 














64 


HM6116A-12'2 


120 


120 










• 




• 












69 


HM6116L-15-2 






150 


150 




0.1m/15m 


24 




• 




• 












69 


HM6116A-20'2 






200 


200 








• 




• 












69 


HM6116AL-12'z 






120 


120 










• 




• 












69 


HM6116AL-15'2 






150 


150 




5,i/10m 






• 




• 












69 


HM6116AL-20"? 






200 


200 










• 




• 












69 


HM6716-25 






25 


25 














• 












74 


HM6716-30 


Bi-CMOS 


2048 x8 


30 


30 




0.28 










• 












74 


HM6719-25 


(with OE) 


25 


25 












• 












74 


HM6719-30 






30 


30 














• 












74 


HM6268-25 






25 


25 










• 
















80 


HM6268-35 






35 


35 




0.V0.25 






• 
















80 


HM6268-45 




4096x4 


45 


45 










• 
















80 


HM6268L-25 




25 


25 










• 
















80 


HM6268L-35 






35 


35 




5,</0.25 






• 
















80 


HM6268L-45 


CMOS 




45 


45 






20 




• 
















80 


HM6267-35 




35 


35 








• 
















87 


HM6267-45 






45 


45 




0.1m/0.2 






• 
















87 


HM6267-55 




16384x1 


55 


55 










• 
















87 


HM6267L-35 




35 


35 










• 
















87 


HM6267L-45 






45 


45 




5/J0.2 






• 
















87 


HM6267L-55 






55 


55 


+ 5 








• 
















87 


HM6719-25 


Bi-CMOS 


2048 x9 


25 


25 




0.28 


24 








• 












74 


HM6719-30 


30 


30 










• 












74 


HM6264-10' 2 






100 


100 




0.1m/0.2 






• 


• 














94 


HM6264-12'* 






120 


120 








• 


• 














94 


HM6264A-10 






100 


100 










• 


• 


• 












94 


HM6264A-12 






120 


120 




0.1m/15m 






• 


• 


• 












94 


HM6264A-15 






150 


150 










• 


• 


• 












94 


HM6264AL-10 






100 


100 






28 




• 


• 


• 












94 


HM6264AL-12 




8192x8 


120 


120 




10 M /15m 






• 


• 


• 












94 


HM6264AL-15 


CMOS 




150 


150 










• 


• 


• 












94 


HM6264AL-10L 






100 


100 










• 


• 


• 












94 


HM6264AL-12L 






120 


120 




10yi5m 






















94 


HM6264AL-15L 






150 


150 


























94 


HM6288-25 






25 


25 






22 
24 
(SOJ) 
















• 




103 


HM6288-35 






35 


35 




0.1m/0.3 
















• 




103 


HM6288L-25 






25 


25 


















• 




103 


HM6288L-35 






35 


35 




















• 




103 


HM6788-25 




16384 x4 


25 


25 




10m/0.23 






















111 


HM6788-35 




35 


35 
























111 


HM6788H-20 


Bi-CMOS 




20 


20 




0.28 


22 




















115 


HM6788HA-12 




12 


12 
























119 


HM6788HA-15 






15 


15 




.3 






















119 


HM6788HA-20 






20 


20 


























119 


HM6289-25 






25 


25 






















• 




124 


HM6289-35 


CMOS 


16384x4 


35 


35 




0.1m/0.3 


24 
















• 




124 


HM6289L-25 


(with OE) 


25 


25 


















• 




124 


HM6289L-35 






35 


35 






















• 




124 



Total 



16k-b 



18k-b 



16k-b 



64k-b 



(continued) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



QUICK 



■ MOS RAM 



GUIDE 



Type No. 


Process 


Organization 
(word x bit) 


Access 
Time 
(ns) 


Cycle 
Time 
(ns) 


Supply 
Voltage 
M 


Power 
Dissipation 
(W) 


Package*' 


Page 






Max 


Max 


Pin No 


G 


P 


fP 


SP 


ZP 


CG 


CP 




M 




UMC7QQ 9i; 






9^ 

C.0 


9R 
LO 




10^0.23 


















a 




1^ 
i jj 








ju 






















a 




100 


nlVID/ 03n ID 




16384x4 
(with OE 


15 


ID 














, 








a 






UMC70QU on 

niviu/ oyn-^u 


Ri-PMfK 

01 OIVIUO 


9fl 


20 






24 








( 








a 






HMfi7RQHfl 19 

nivio/oyriM- \c 




19 


19 
l^ 




0.28 










( 








a 




140 


HMR7RQHA. 1^ 

niviD/ oyntt- id 






ID 


ID 














a 








a 




14Q 


MHflK7Q0i4A 90. 

niviD/oynA-iiU 






on 


on 














a 








a 






HMR987 /1R 

niviO£Of-*tD 






HO 
















a 












I J/ 


UMCO07 RR 
nlvlOtOf-DD 






00 


DD 




0.1m/0.3 










a 












157 


niviDto/-/ u 






70 


70 






22 








a 












157 


HMK9R7I AR 






HD 


*fD 












a 












157 

ID/ 


HMR.9R7I R^ 


CMOS 




RE. 
00 


EC 

DD 




in»/o 1 

lU/x/ U . O 










a 












1^7 


MMfi9R7l 7fl 
n!vlDiiO/L-/U 




7n 
/ u 


7n 
/u 


























1^7 
ID/ 


HMfi9R7i-t 9R 






9R 


9R 




0.1m/0.3 


















• 




1R4 


HMR9Q7U QR 

nMO£t»n-JD 






OR 


QR 
JD 












a 








• 




1fi4 


HMR9R7HI 9R 




UJJ JU X I 


9R 
ZD 


^D 




KV/0.3 










a 








• 




1fi4 
ItH 


WMR9H7UI 9.R 






OR 


OC 
JD 












# 








• 




1R4 


HMR7R7 9c; 






9c; 
ZD 


^D 




38m/0.18 


22 








# 












173 
\fo 


UMR7R7 9.R 






OR 
Jo 


JD 




24 








# 












17Q 


WMK7R7M 1R 
nlVlO/O/n- ID 






1R 
ID 


1R 
ID 




0.21 


(SOJ) 








# 








• 




17Q 


UMR7R7U on 


DI-ljIVIUO 




on 
ZU 


on 




















• 




178 


WMK7R7UA ID 19 






10 
IZ 


10 






















• 




17Q 

I/O 


UMR7R7UA ID 1R 
nlViu/o/nAJr- ID 






1R 
ID 


15 














# 








• 




183 


UMK7R7UA ID Of) 






20 


20 














a 












183 


UMR99RR R 

nMb^Db-o 






oD 


85 










# 


■ # 














189 








100 


100 




0.2m/40m 






# 


# 














189 


HMbZzDb-1^ 






120 


120 
























189 








150 


150 










# 
















189 


nMb2zDbl_-o 






85 


85 


























189 


HMb<;2DoL-1u 






100 


100 




V)fJ40m 








# 














189 


UMC99RC! 19 

HMbZ^DbL- V 






120 


120 










# 














189 


UMfiOORfil 1R 

nMb^bbL-lD 






150 


150 


+ D 








# 
















189 


umroorri mci 

nlVIDZilDoL- IUbl_ 






inn 


mn 

IUU 












# 














189 


MMROORKI 19QI 




OCI 00 X 


ion 


ion 

liiU 




IU/i/4UIII 


28 




# 


# 














1QQ 

toy 


UMR99RRI 1RQI 
nlvlu^iDDL- IDoL 






iRn 

IDU 


150 


























189 


UMR9RT9 9.R 






35 


35 




75m/.3 










# 












197 


UMfi9ft0.9_/1K. 






AC- 
QS! 


AK 
HO 
























10.7 


UMK9R9.9I OR 






oO 


JD 




10m/.3 


















a 




1Q7 


niviD^oocL-*ta 


CMOS 




A% 














a 








a 




1Q7 

iy/ 


HM.R.9R39H 9C 






25 


25 














# 








a 




10,7 
iy/ 


HMfl9R9.9U 9.R 
nlVIOdOJ^n-JD 






OO 


JD 




.1m/.3 










# 








a 




1Q7 

iy/ 


HMR9fl'39H >1R 
nlvlOtOJ^rl-^D 






AZ 
QO 


Ad 
4D 






















a 




197 


MMR.9ftO.QUI 9R 
n IVIO£Oj£ n L-dO 








OR 














# 








a 




1Q7 

iy/ 


UMR9R99UI OR 






JD 


on 
JD 




JUIII/.O 


















a 




197 


UMRQQQQUI 






45 


45 






















a 




197 


UMfionn or 






JD 


JD 




0.1m/0.3 






• 
















203 


MMfiQAR AS. 
n IVIDdUo-4D 






HO 


*!D 








• 
















203 


HMROnfll OR 
nMOZUoL-JD 






JD 


35 




1IW0.3 






• 
















203 


UMRonai /r 






45 


45 








• 
















203 


WMfionRU 9fi 






OR 
£0 


25 




0.1m/0.3 










a 








a 




203 


umrohru or 






35 


35 




















a 




203 


UMRQHQUI 9k 






25 


25 




10/J0.3 


24 




















203 


UMROHRUI OR 
nMOZUonL-JD 






9R 
OD 


35 
























203 


HM6708-20'3 




65536 x4 


20 


20 




0.35 






















211 


HM6708-25'3 




25 


25 
























211 


HM6708A-15 






15 


15 












• 








• 






217 


HM6708A-20 






20 


20 




.4 








• 








• 






217 


HM6708A-25 


Bi-CMOS 




25 


25 












• 








• 






217 


HM6709-20 




20 


20 




.35 


















• 




222 


HM6709-25 






25 


25 




















• 




222 


HM6709A-15 






15 


15 






28 








• 








• 




229 


HM6709A-20 






20 


15 




.4 










• 








• 




229 


HM6709A-25 






25 


25 














• 








• 




229 



Mode 



Total 



Static 



256k-b 



(continued) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



QUICK REFERENCE GUIDE 



■ MOS RAM 



Mode 


Total 


Type No. 


Process 


Organization 
(word x bit) 


Access 
Time 

Max 


Cycle 
Time 

Max 


Voltage 

IV) 


Power 
Dissipation 

m 


Package 


Page 


Pin No. 


G 


P 


FP 


SP 


ZP 


CG 


CP 




M 


Static 


256k-b 


UMCOIY7 0.£ 

MIVtDZU/-00 


CMOS 


262144 x 1 


■3D 


OK 
OJ 


+ 5 


0.1m/0.3 


24 




















no? — 

236 


UMC0n7 AC 


AC 
45 


ACL 

4b 




















236 


nlvlDtUf L-JJ 


35 


35 


10^/0.3 




















236 


UIMftOfV7l AC 

HMozUf L-4b 


45 


AC 

40 




















236 


UMP.0H7U DC 


25 


25 


0.1m/0.3 
















# 




243 


UMP.on7U ox 
niviDiU/n-jO 




00 




















243 


uMc.0n.7m oc 


25 


25 


ioyo.3 








# 












243 


nlVlDtUmL-dD 


35 


OC. 
JO 








# 












243 


UMR7n7 On*1 


Bi-CMOS 


on 

OJ 


on 

cv 


0.35 
















# 




250 


nMOf U/-£ib J 


25 


25 








# 








# 




250 


nlvlb/WA-lo 


15 


15 


.4 




















255 


UMc.7n.7A on 
nlVlb/U/A-<:U 


20 


20 








# 








# 




255 


UMC7n7A OE 


25 


25 








— - 








— 




255 


1M-b 


UMMQ10Q 7*1 


CMOS 


131072 x 8 


70 


70 


0.1m/75m 


32 









— 













261 


UMC.OQ10Q t)"1 


85 


85 





















261 


HM628128-10' 3 


100 


100 




— 


— 














261 


HM628128-12' 3 


120 


120 






















261 


HM628128L-7' 7 


70 


70 


10/j/75m 




— 


— 














261 


HM628128L-8' 7 


85 


85 




— 


— 














261 


HM628128L-10' 7 


100 


100 






















261 


HM628128L-12' 7 


120 


120 




— 
















261 


HM624256-35' 3 


Z62144 x 4 


35 


35 


0.1m/0.35 


28 




— 


— 














269 


HM624256-45" :i 


45 


45 








— 








— 
-S- 




269 


n Mb*;42bbl_ -ob J 


— TT — 

35 


3b 


1m/.35 




















269 


HMb24,ibbL-4b J 


45 


45 








# 








# 




269 


UMGOdoc;7 ocm 


35 


35 


0.1m/0.35 


32 
















# 




275 


L nMbZ42b/-4b 4 


45 


45 
















— 




275 


UMC0vl0K7l IC-J 


35 


35 




















275 


UMCO<OC7l AC'A 

nlVlb242b/L-4b 4 


45 


45 
















— 




275 


Static 
RAM 
Module 


nMob2U4-12 4 


131072 x 8 

(with 
decoder) 


120 


120 


0.8m/50m 




















283 


Hlvlbb<:U4-1b 4 


150 


150 




















283 


HMbb2U4L-12 4 


120 


120 


40^50m 




















283 


HMbb204L-1b 4 


150 


150 




















283 


FIFO 


18k-bit 


HM63921 -20 


2kx9 


20 


30 


tow 

max. 


28 




— 
















289 


i_in flcononi nc 

HMbdy21-2b 


25 


35 




















289 


HM63921-35 


35 


45 




— 
















289 


36k-bit 


HM63941-25 


4kx9 


25 


35 




— 
— 
















289 


HMboy41-JO 


35 


45 




















289 


HMbjy41-4j 


45 


60 




— 
















289 


Cache 
Static 
RAMs 


120k-b 


umcoa -icq oc 
HIVlb^Albo-^D 


8kx16 
(2 way) 


25 


25 


< 11 > 


52 




















311 


UMC1A1CO OC 

Hlvlb2AlDo-3D 


35 


35 














# 






311 


nIVIb.; A 100-40 


45 


45 














— 






311 


128k-b 


UMC.OA1QQ oc 


8kx18 
(2 way) 


25 


25 














— 






311 


UMCO A i QQ OC 

HMb^Aloo-OD 


35 


35 




















311 


UMCO A -jOO j(C 

HMb^AlotMb 


45 


45 




















311 


256k-b 




Bi-CMOS 


32k x 9 
(4 way) 


20 


20 


TBD 


44 




















319 


HM67C932-25 


25 


25 




















319 


HM67B932-20 


20 


20 




















t 


HM67B932-25 


25 


25 




















t 


Fast 
SRAM 
Module 


HB66B1616A-25 


CMOS 


16k x 16 
(module) 


25 


25 


.4m/1.2 


36 


















• 


333 


HB66B1616A-35 


35 


35 


















• 


333 


2M-b 


HB66A2568A-25 


256k x 8 
(module) 


25 


25 


.8m/2.4 


60 


















• 


343 


HB66A2568A-35 


35 


35 


















• 


343 


TAG 
RAM 


32k-b 


HM644332-25 


2kx20 
(tag ram) 


25 


25 


1.0 
max. 


64 




















351 


HM644332-30 


30 


30 




















351 



tData sheet not included in this manual. Request data sheet for HM67B932. (continued) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 xv 



QUICK REFERENCE GUIDE 

■ MOS RAM 



Mode 



Video 
Memory 



Dynamic 



Total 


Type No. 


Process 


UiydlllZdllUII 

(word x bit) 


Access 
(ns) 


Cycle 
{ns} 


Supply 
vbnage 


Power 
Dissipation 
(W) 


Package " 1 


Page 








Max 


Max 


Pin No 


G 


? 


FP 


SP 




CG 


CP 




M 






HM65256B-10 






100 


100 










• 


• 


• 












369 




HM65256B-12 






120 


190 










• 


• 


• 












369 




HM65256B-15 






150 


235 










• 
















369 




HM65256B-20 




32768 x8 


200 


310 




2m/0.175 


28 




• 
















369 




HM65256BL-10 




100 


180 






• 
















369 




HM65256BL-12 

P IIVIUlJttJULjL it 






120 


190 










• 
















369 


256k-b 


HM65256BL-15 






150 


235 










• 
















369 


HM65256BL-20 

1 MVIUsJtUUUL- tU 






200 


310 










• 
















369 




HM658128D-10 






100 


180 


























376 




HM658128D-12 






120 


210 




5m/0.2 






• 
















376 




HM658128D-15 




131072 x8 


150 


250 






32 




















376 




HM658128L-10 




100 


180 
























376 




HMfi5fl19fil -19 






120 


210 




0.5m/0.2 






















376 










150 


250 










• 


• 1 




1 376 




HMfi30?1-98 

1 MVIUUUd P tU 






20 


28 


























388 


16k-b 


I UVIUOUt 1 iJ*t 




2048x8 


24 


34 




0.25 


18 




















388 










30 


45 


























388 


1M-b 


1 I1VIUOUU 1 ^rO 




262144 x4 


35 


45 




0.2 


28 




a 
















402 


I UVIUOUt 1 uu 




40 


60 






a 
















402 




1f) 

mvi johu i iu 






100 


190 










. 
















412 




HM^dfil-19 

1 UVUO'tU l ie 






120 


220 










a 
















412 


256k-b 


nivijiXD i to 




ODD JO X H 


150 


260 






24 




s 
















412 


niviooHOt- iu 


CMOS 


Multi-port 


mn 

IUU 


190 








a 
















425 




I HVIJOHUt l(_ 






120 


220 










s 
















425 




nivioo*tut io 






150 


260 


























425 




nlVIOOOIt I - IU J 






IUU 


iyu 






















• 




569 




HMS^ft191 19"3 
niviooo it i it 






120 


220 






















• 




569 




niviDoo i^i I- 10 J 






iRn 

IOU 


tOU 






















• 




569 




HIK4ft199 10*3 

nivioooitt- iu J 






100 

[UU 


1QO 

iyu 






















• 




444 




MMRQfllOO 19"3 
nlvlDoO Itt- It J 




111(179 v ft 
10 IU» t X 


ItU 


9on 

ttU 


+ J 




40 
















• 




444 




niVIOoo Itt- IO J 






i^o 


9R0 
tOU 






















• 




444 




mmwaio*? io - 3 
niviooo ito- iu •* 






mn 

IUU 


■i on 
iyu 






















* 




470 




WMR^fl191 19'3 






190 
ItU 


990 
ttU 


























HIV 




nivooo itj- id J 






150 


9R0 
tOU 


























470 


1M-b 


10"3 

mvioo^tto i- iu J 






100 
IUU 


1QO 

iyu 




35m/0.55 






















469 


nivioo*fcO I - 1 1 ° 






-inn 

IUU 


190 
























469 




HM l vt49 , i1-19*3 
rnvuottJ I it 






120 


220 


























469 




HiM^^^O^I 1»V3 

nivioo'ito 1- io 






150 


260 


























469 




HM I vW9 £ i9 1fl'3 

niviooMtOt iu J 




262144x4 
Multi-port 


100 


190 


























516 




mvioo^tOt- 1 1 3 




100 


190 






28 




















516 




HM51d959 19'3 

nlVIDoHtDt- It J 




120 


220 


























516 




HM'vl^'W 15*3 






150 


260 


























516 




HM514951 1(T3 

mvioj^ttoj- iu J 






ion 


190 


























542 




HMS'^'Vl 19"3 

niviOiWtoj it J 












• 




542 




NIVlJOHtJO U 








260 






















• 




542 




HMSfMfid 19 






120 


220 


























590 




i uvuytwt u 




65536 x4 


150 


260 






18 




















590 




nivi ju'tO't tu 


NMOS 




200 


330 




20m/0.35 






















590 




nivijut jit it 




120 


220 
























598 




HMSn9 c ifi-1 c i 

1 HVMUtJU \\) 






150 


260 


























598 




HM50256-20 






200 


330 


























598 


256k-b 


HM51256-8 






85 


155 


























606 


HM51256-10 






100 


180 






16 




















606 




HM51256-12 




262144 x 1 


1205 


210 






18 




















606 




HM51256-15 


CMOS 




150 


250 




10m/0.35 


plcc; 




















606 




HM51256L-8 




85 


155 
























606 




HM51256L-10 






100 


185 


























606 




HM51256L-12 






120 


210 


























606 




HM51256L-15 






150 


250 


























606 



(continued) 



HITACHI 

xvi Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



QUICK REFERENCE GUIDE 



■ MOS RAM 



Mode 



Type No. 


Process 


Organization 
(word x bit) 


Accgss 
Time 
(ns) 


Cycle 
Time 
(ns) 


Supply 
Ullage 

m 


Power 
Dissipation 
(W) 


Package ' ' 


Page 






Max 


Max 


Pin No 


G 


9 


FP 


SP 


ZP 


CG 


CP 


JP 






HM51258-8 






85 


150 










• 
















614 


HM51258-10 




Ibd. 144 x 1 


100 


180 




lum/u.ob 


16 




• 
















614 


HM51258-12 




120 


210 






• 
















614 


HM51258-15 






150 


250 










• 
















614 


HM514256-8 






80 


160 










• 






• 






• 




623 


HM514256-10 






100 


190 










• 






• 






• 




623 


HM514256-12 






120 


220 










• 






• 






• 




623 


HM514256-8S 






80 


160 










• 






• 






• 




635 


HM514256-10S 






100 


190 




10m/0.33 






• 






• 






• 




635 


HM514256-12S 






120 


220 










• 






• 






• 




635 


HM514256A-8 






80 


160 










• 






• 






• 




635 


HM514256A-10 






100 


190 










• 






• 






• 




635 


HM514256A-12 






120 


220 










• 






• 






• 




635 


HM514256API-6 






60 


120 




11/495 






• 






• 






• 




651 


HM514256API-7 






70 


130 




11/440 






• 






• 






• 




651 


HM514256API-8 






80 


160 




11/385 






• 






• 






• 




651 


HM514256API-10 






100 


190 




11/330 






• 






• 






• 




651 


HM514256API-12 






120 


220 




11/275 






• 






• 






• 




651 


HM514256H-6 






60 


120 




10m/0.45 






• 






• 






• 




667 


HM514256H-7 






70 


140 








• 






• 






• 




667 


HM514258-8S 






80 


160 










• 






• 






• 




696 


HM514258-10S 






100 


190 










• 






• 






• 




696 


HM514258-12S 






120 


220 




10m/0.375 






• 






• 






• 




696 


HM514258A-8 






80 


160 








• 






• 






• 




696 


HM514258A-10 






100 


190 










• 






• 






• 




696 


HM514258A-12 






120 


220 










• 






• 






• 




696 


HM514266A-6 






60 


120 




11/495 






• 






• 






• 




711 


HM514266A-7 






70 


130 




11/440 






• 






• 






• 




711 


HM514266A-8 


CMOS 




80 


160 


+ 5 


11/363 


18 




• 






• 






• 




711 


HM514266A-10 






100 


190 




11/303 






• 






• 






• 




711 


HM514266A-12 




1048576 x 1 


120 


220 




11/259 






• 






• 






• 




711 


HM514256-8 






80 


160 




11/363 






• 






• 






• 




711 


HM514256-10 






10 


190 




11/303 






• 






• 






• 




711 


HM514256-12 






12 


220 




11/259 






• 






• 






• 




711 


HM511000-8S 






80 


160 










• 






• 






• 




725 


HM511000-10S 






100 


190 




10m/0.35 






• 






• 






• 




725 


HM511000-12S 






120 


220 










• 






• 






• 




725 


HM511000A-8 






80 


160 










• 






• 






• 




725 


HM511000A-10 






100 


190 




10m/0.375 






• 






• 






• 




725 


HM511000A-12 






120 


220 










• 






• 






• 




725 


HM511000ALP-8 






80 


160 




1.7/385 






• 






• 






• 




737 


HM511000ALP-10 






100 


190 




1.7/330 






• 






• 






• 




737 


HM511000ALP-12 






120 


220 




1.7/275 






• 






• 






• 




737 


HM511000ALJP-8 






80 


160 




1.7/385 






• 






• 






• 




737 


HM511000ALJP-10 






100 


190 




1.7/330 






• 






• 






• 




737 


HM511000ALJP-12 






120 


220 




1.7/275 






• 






• 






• 




737 


HM511000H-6 






60 


125 




10m/0.45 






















751 


HM511000H-7 






70 


140 
























751 


HM511001-8S 






80 


160 


























762 


HM511001-10S 






100 


190 


























762 


HM511001-12S 






120 


220 


























762 


HM511001A-8 






80 


160 


























773 


HM511001A-10 






100 


190 




10m/0.35 






















773 


HM511001A-12 






80 


160 


























773 


HM511002-8S 






80 


160 


























816 


HM511002-10S 






100 


190 


























816 


HM511002-12S 






120 


220 


























816 














(cc 


ntinued) 



Dynamic 



1M-b 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 xvii 



QUICK REFERENCE GUIDE 



■ MOS RAM 



Type No. 


Process 


Organization 
(word x bit) 


Access 
Time 
(ns) 


Cycle 
Time 
(ns) 


Supply 

Voltage 
(V) 


Power 

niccinatinn 

URNMUatlul I 

(W) 


Package V 


Page 






Max 


Max 


PinNo 


G 




FP 


SP 




CG 


CP 


JP 






HM511002A-8 






80 


160 










• 






• 






• 




816 


HM511002A-10 


CMOS 


1,048,576x1 


100 


190 




10m/0.45 






• 






• 






• 




816 


HM511002A-12 






120 


220 










• 






• 






• 




816 


HM5710OJP-35R 






35 


70 






















• 




803 


HM57100JP-40R 






40 


80 






















• 




803 


HM57100JP-45R 


Dl-bMUc) 


1M x 1 


45 


85 


5V 


1W 


28 
















• 




803 


HM574256JP-35R 


35 


70 
















• 




816 


HM574256JP-40R 






40 


80 






















• 




816 


HM574256JP-45R 






45 


85 






















• 




816 


HM514100-8 






80 


150 




11m/.495 












• 






• 




855 


HM514100-10 




4,1S*4,JU4 x 1 


100 


180 




11m/.44 












• 






• 




855 


HM514100-12 




120 


210 




11m/.385 












• 






• 




855 


HM514100-7 






70 


140 


5v-5 


11m/.55 












• 






• 




869 


HM514400-8 






80 


150 




11m/.495 












• 






• 




883 


HM514400-10 




1,048,576 x4 


100 


180 




11m/.44 












• 






• 




883 


HM51440O-12 






120 


210 




11m/385 












• 






• 




883 


HM514101-8 


CMOS 




80 


150 




11m/.495 












• 






• 




883 


HM514101-10 




100 


180 




11m/.44 












• 






• 




883 


HM514101-12 




4,iy4,oU4 x 1 


120 


210 




11m/.385 












• 






• 




883 


HM514102-8 




80 


150 




11m/.495 












• 






• 




883 


HM514102-10 






100 


180 




11m/.44 












• 






• 




883 


HM514102-12 






120 


210 




11m/.385 












• 






* 




883 


HM514410-8 






80 


150 




11m/.495 












• 






* 




883 


HM514410-10 




1,048,576 x4 


100 


180 




11m/.44 












• 






• 




883 


HM514410-12 






120 


210 




11m/.385 












* 






* - 




883 


HB561008-12 




?fi?144 v ft 


120 


210 




0.12/2.42 






















963 


HB561008-15 


NMOS 


150 


260 




0.12/2.42 






















963 


HB561003-12 




120 


210 




0.135/2.55 




















• 


854 


HB561003-15 




262144x9 


150 


260 




0.135/2.16 




















• 


854 


HB561409-10 






100 


180 




60m/1.8 




















• 


958 


HB56A18-10S 






100 


180 
























• 


831 


HB56A18-12S 




1048578 x 8 


120 


210 




20m/1.4 




















• 


831 


HB56A18-10A 




100 


180 




20 


















• 


831 


HB56A18-12A 






120 


210 






















• 


831 


HB56A19-10S 






100 


180 


5V 






















• 


843 


HB56A19-12S 




1 048578 v Q 


120 


210 


20m/1.6 




















• 


843 


HB56A19-10A 




100 


180 






















• 


843 


HB56A19-12A 






120 


210 
























• 


843 


HB56C18-10 




104ft57fi v ft 

I U4U J ( U X O 


100 


190 




onm/1 R 
^Ul II/ I .o 




















• 


843 


HB56C18-12 




120 


220 






















• 


843 


HB56C18AT-8A 


CMOS 




80 


560 




88/3.08 






















837 


HB56C18AT-10A 




100 


A80 




88/2.6A 






















837 


HB56C18AT-12A 






120 


400 




88/2.20 






















837 


HB56C19-8 






80 


630 




99/3465 






















849 


HB56C19-10 




1048576 x9 


100 


190 
























• 


849 


HB56C19-12 






120 


220 






















• 


849 


HB56C19AT-8A 






80 


630 




99/3465 




















• 


849 


HB56C19AT-10A 






100 


540 




99/2970 




















• 


849 


HB56C19AT-12A 






120 


450 




99/2475 




















• 


849 


HB56D25608A-6H 






60 


180 




22/990 




















• 


967 


HB56D25608A-7H 






70 


160 




22/880 




















• 


967 


HB56D25608A-8A 




262,144 x8 


80 


132 




22/726 




















• 


967 


HB56D25608A-10A 






100 


110 




22/605 




















• 


967 


HB56D25608A-12A 






120 


94 




22/517 




















• 


967 


HB56D25609A-85A 






85 


202 




33/1.11 




















• 


979 


HB56D25609A-10A 




262,144 x9 


100 


170 




33/.94 




















• 


979 


HB56D25609A-12A 






120 


144 




33/J9 




















• 


979 



1M-b 



4M-b 



(continued) 



HITACHI 

xviii Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



QUICK REFERENCE GUIDE 



■ MOS RAM 



Mode 


Total 


Tuna Nn 


Process 


Organization 
(word x bit) 


Access 
Time 
(ns) 
Max 


Cycle 
Time 
(ns) 
Max 


Supply 
Ullage 

M 


Power 
Dissipation 

m 


Package *' 


Page 


Pin No. 




















DRAM 
Module 




HB56D25609B-85A 


CMOS 


262.144 x 9 


85 


202 




33/1.11 


30 


















• 


979 


HB56D25609B-10A 


100 


176 


33/94 


















• 


979 


HB56D25609B-12A 


120 


144 


33/79 


















• 


979 


HB56D25636B-85 


262,144 x 36 


85 


160 


126/4.24 


72 




















991 


HB56D25636B-10 


100 


190 


















— 


991 


HB56D25636B-12 


120 


220 


















— 


991 


HB56D51236B-85 


524,288x36 


85 


160 


252/4.58 


















— 


1003 


HB56D51236B-10 


100 


190 


252/3.91 


















— 


1003 


HB56051236B-12 


120 


220 


252/3. 36 


















— 
* 


1003 


4M-b 


HB56A49-8 


4,194.304 x9 


80 


160 


5V 


99m/4.455 


30 




















1027 


HB56A49-10 


100 


190 


99m/3.96 




















1027 


HB56A49-12 


120 


220 


99m/4.405 




















1027 


HB56A48-8 


4,194,304 x8 


80 


160 


88m/3.96 




















1015 


HB56A48-10 


100 


190 


88m/3.52 




















1015 


HB56A48-12 


120 


220 


88m/3.08 




















1015 


HB56D136-8 


1,045.576 
36 


80 


160 


5V 
±5% 


126m/5.25 


72 




















1039 


H656D136-10 


100 


190 


126m/4.62 




















1039 


HB56D136-12 


120 


220 


126m/3.99 




















1039 


HB56D236-8 


2,097,152 
x36 


80 


160 


252m/5.57 




















1049 


HB56D236-10 


100 


190 


252m/4.94 




















1049 


HB56D236-12 


120 


220 


252m/4.31 




















1049 



■ MOS ROM 



Program 


Total 
Bit 


Type No. 


Process 


Organization 
(word x bit) 


Access 
Time 
(ns) 
Max 


Supply 
Voltage 

(V) 


Power 
Dissipation 

m 


Package '1 


Page 


Pin No. 


G 


P 


FP 


Mask 


256k-b 


HN623257 


CMOS 


32768 x8 


150 


5 + 


5^/0.1 


28 








1060 


HN623258 


200 








1063 


1M-b 


HN6233T3 


131072 x8 


120 








1069 


HN62321 


150 








1066 


HN62321B 


200 








1077 


HN62331E-3 


120 








1077 


HN62321E 


200 








1077 


HN62331A-3 


120 


32 








1069 


HN62321A 


150 








1080 


2M-b 


HN62422'3 


131072 x 16 
or 262144 x8 


150 


40/44 








1083 


HN62412 


200 








1083 


4M-b 


HN62424-3 


262144x16 
or 524288x8 


150 


40/44 








1087 


HN62404 


200 








1087 


HM62324B-3 


524288 x8 


150 


32 








1091 


HN62304B 


200 








1091 


HN62414 


262144x16 
or 524288 x8 


200/170 


40 








1101 


200/170 


44/48 








1101 


HN62314 


512Kx8 


200/170 


32 








1107 


HN62444 


512Kx8 


100 


40 








1095 


256x 16 


100 


44/48 








1095 


8M-b 


HN62408-3 


524288x16 
or 1048576 x8 


200 


42/44 




• 




1114 



(continued) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 xix 



QUICK REFERENCE GUIDE 



■ MOS ROM 



Program 


Total 
Bit 


Type No. 


Process 


Organization 
(word x bit) 


Access 
Time 
(ns) 
Max 


Supply 
Voltage 
(V) 


Power 
Dissipation 

m 


Package " 1 


Page 


Pin No 


G 


P 


FP 


Electrically 
Erasable & 
Programmable 


16M-b 


HN62308B 




1Mx8 


200 


+ 5 


5u/0.1 


32 




• 


• 


1119 


HN66403P 


1Mx8 
512Kx16 


250 


42 




• 




1123 


HN624016-3 


1048576 x 16 
or 20978152 x 8 


200 




1127 


64k-b 


HN58C65-25 


CMOS 


8192x8 


250 


2m/20m 


28 








1138 


HN58C66-25 


250 








1147 


256k-b 


HN58C256-20'* 


32768 x 8 


200 


0V0.1 








1156 


ItV Frasahlp 
& Electrically 
Programmable 


256k-b 


HN27C256A-10-3 


100 








1158 


HN27C256A-12-3 


120 








1158 


HN27C256A-15'3 


150 









1158 


HN27C256H-70 


70 


0.15 


— 






1166 


HN27C256H-85 


85 









1166 


512k-b 


HN27512-25 


NMOS 


65536 x8 


250 


50m/0.2 


— 






1176 


HN27512-30 


300 


— 






1176 


1M-b 


HN27C1024H-85 


CMOS 


65536x16 


85 


0.2 


40 


— 






1183 


HN27C1024H-10 


100 








1183 


HN27C101-17 


131072 x8 


170 


0.5«/0.1 


32 


— 






1192 


HN27C101-20 


200 


— 






1192 


HN27C101-25 


250 








1192 


HN27C301-17 


170 








1200 


HN27C301-20 


200 








1200 


HN27C301-25 


250 








1200 


One Time 
Electrically 
Programmable 


256k-b 


HN27C256-25T 


32768 x8 


250 


0.5,i/50m 








• 


1209 


HN27C256-30T 


300 






• 


1209 


512k-b 


HN27512-25 


NMOS 


65536 x8 


250 


50m/0.2 








1215 


HN27512-30 


300 








1215 


1M-b 


HN27C101-20 


CMOS 


131072 x8 


200 


0V0.1 


32 






• 


1222 


HN27C101-25 


250 






• 


1222 


HN27C301-20 


200 






• 


1229 


HN27C301-25 


250 






• 


1229 


HN27C101-AG 


128k x 8 


15/12/10 


• 






1237 


15/12 


• 


• 


• 


1237 


HN27C4096 


256k x 16 


12/12/10 


40 


• 






1247 


12/15 


44 






I 


1247 



HITACHI 

XX Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



QUICK REFERENCE GUIDE 



■ ECL RAM 



Level 


Total 
Bit 


Type No. 


Organization 
(word x bit) 


Output 


Access 
Time 
(ns) 
Max 


Supply 
Voltage 
(V) 


Power 
Dissipation 
(W) 


Package -1 


Page 


Pin No 


G 


F 


CG 


JP 


ECL 10K 


64k-b 


HM10494-10 


16384x4 


Open 


10 


-5.2 


0.8 


28 


• 


• 






1258 


HM10494-12 


12 


• 


• 






1258 


HM10490-10 


65536-1 


10 


.57 


22 


• 


• 






1263 


HM10490-12 


12 


• 


• 






1263 


256k-b 


HM10504-10 


65536 x4 


10 


.50 


28 




• 






1267 


HM10504-12 


12 




• 






1267 


HM10500-15' 3 


262144 x 1 


Emitter 


15 


0.52 


24 


• 








1269 


ECL100K 


64k-b 


HM100494-10' 4 


16384x4 


10 


-4.5 


0.65 


28 


• 


• 




• 


1273 


HM100494-12' 4 


12 


• 


• 




• 


1273 


HM10O49O-10 


65536x1 


15 


0.57 


22 


• 


• 




• 


1277 


i uvi i uyj^oKj \l- 


20 


• 


* 




• 


1277 


HM 100490-15 


• 






• 


1277 


256k-b 


HMinnsodF-in 

i uvi luuuv^tr iu 


65536x4 


10 


.50 


28 










1281 


HM100504F-12 


12 










1281 


HM100500-18-3 


262144x1 


18 


0.5 


24/28 


• 




• 




1282 


64k-b 


HM101494-10 


16384x4 


10 


-52 


.75 


28 


• 








1285 


HM101494-12 


12 


• 








1285 


HM101490-10 


65536x1 


10 


.57 


22 


• 








1289 


HM101490-12 


12 


• 








1289 


HM101504-10 


10 














1293 


HM101504-12 


12 










1293 


HM101500-15-3 




.50 


24 










1294 



Notes) "1. The package codes of G. F and CG and applied lo the package material as follows. 
G: cerdip. F; Flat Package, CG: Ceramic Leadless Chip Carrier 
•2. Maintenance Only. This device is not available tor new application 
"3. Preliminary 
•4. Under Development 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 xxi 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • 



Package Information 



HITACHI 



■ PACKAGE INFORMATION 



• Dual-in-line Plastic 



Unit: mm (inch) Scale 1/1 



• DP-16B 



19.2(0 756) 
20 32m«» 




_J|Loj9 L3j U 

^Ti±03S) (0051)^,. 



762 
(0 300) 



2 54 * 0.25 aiT, .l ~ 2 ffTs- "+(0 0«--.«»' 
(0 100 - 0010) (0019* 0.004) S 



• DP-18B 



22.0(0.866) 



- 22Mfn»x.(0W0max.) ,J 
nnnnnnnnn 



U U U U u |-| u LJ TT 
1 .3(0.051) 



762 
, (0.300) . 





0.48 ±0.1 2.54 ±0.25 - 
(O.OI9±0.004) (0.1 00 ±0.0 10) 



• DP-18C 



• DP-20N 



22.26(0.876) 



22.86ni«.(0.900max.) 



R ill 

u u u u uj^j^u u c r — 



2 q (l.OODman.) 1 1 
nnonnnnnnn. 




762 

| j I 10 3001 | 



.uuuuuuuuuu 

_JUi9 i3jr_ _ 

~ 'V035) (o.bliT , E I 




INI 



7 62 
(0.300) 



0.48*0.1 2 54 ±0.25 — 
(0.0I9±0.004) (0.100+0.010) 



2 54 ±0 25 0.48* 1 

(0.100* 0.010) (0019* 0004) 




s <r- is- 



• DP-20NA 




• DP-22N 




(0.045) (0051) 



o IS (0° 



2 54 • 25 48 * I 
(0 100 -0010) (0019 • 0004) 




088(0.035) 



(0.300) 



oiotSB' 1 



2.54 ±0.25 
(O.OI9± 0.004) (O.IOO±O.OIO) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Dual-in-line Plastic 



PACKAGE INFORMATION 

Unit: mm (inch) Scale 1/1 



• DP-22NB 



27.90max.(l.098ma*.) 

nnnnnnnnnnn 



JJUUUUUUUUUIJ 

0-88(0.035) I -3(0.05 1 ) 



!J2 




.zs3.ll 



0.48 ± O.I 2.54 ±0.25 

(O.OI9±0.004) (0.I00±00I0) 



• DP-24 



24 32.5nTax.(l.280maic) , 3 

nnnnnnnnnnnn 




I ' 1(1047 




2 54 + 25 | 0.48 ±0 .1 

(0 100 ± 0-DI0) (0 0191 004) ~o '0'~I5' 



• DP-24A 



• DP-24N 




^ 2962(1.166) [J 

nnnnnnnnnnnn 



ll 



' 0->3 XL- 1300 12 ij ,1016(0.400), 

(0.035)*'"' (0.051) 



30.4(1.197) 

31.75max.(l.250max.r 



nnnnnnnnn nnn 



UUUUUUUUUUUU 

XL XL 12 




,5ow.(S^o l .S„4,,?:^,o, S °"' 5 ' ^ 




JX 2 54±0 25| |g S -X. 

(o'o?^^!o , o4) l|,lM ±°° |o, = = 




• DP-24NC 




29.88(1.176) 

30.48m«.(l.200ma«) 

n'n n n n n n n n n n n 



IUUUUULIUULI 




1.14(0.045) 



I 3(0 051) 




<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



3 



PACKAGE INFORMATION 



• Dual-in-line Plastic 



Unit: mm (inch) Scale 1/1 



• DP-28 



n •X.fmuO Mr™.] 




| (owoT 



• DP-28C 



21 35 5&nli (1 400rnai | ij 




(0.03SI ' ' 10.0511 



Jl 



(010010.010) (Q.litO.OM) "Sr-iV 



• DP-28N 



36.0(1-41?) 



37.32ma«.(l 470ma«.) 



31 1 1 



1.30(0.050 





0.48 + 1 2 54 + 0.25 

(0.0l9± 0.004) (0.100 + 0.010) 







• DP-32 



41.9(1.650) 




(0.1 00 ±0.0 10) 



(0.01 9 ± 0.004) Sg "~/5- ^^otSS" 1 



• DP-40 



54.0ma«.(M26max.) 



nnnnnnnnnnnnnnnnnnnn 



UUUUUUUUUUUUUUUUU 



111 




(0019 + 004) S g 0-is- " «j) 

~ 5 (O.O* '* 




HITACHI 



Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Dual-in-line Plastic 



Unit, mm (inch) Scale 1/1 



• DP-42 



53.7m.«.(2.ll4m»«.) 

42 22 
nnnr-inr-ir-ir-ir-ir-innr-ir-ir-innnnnr) 












CO 100 + 0.010) 




Applicable ICs 



DP 16B 


HM50256P Series. 1IM30257P Series. HM3P23liP Series. HM31236LP Series. HM31238P Series 


DP I8B 


IIM3II464P Series. HM3H465P Series 


DP-18C 


IIM53H5IP. II.M.H DAI' Series. HM5I lOOIISP Series. IIM31 10H0HP Series. IIM511II01AP Series. 11M5110(11SP Series. 

HM31 KHI2AP Series. HM51 1002SP Series 


DP-20N 


HM6168HP Series. HM6168HLP Series, HM6268P Series. HM6268LP Series. HM6167P Series. IIM6167LP Series. 
HM6W7HP Series. HM6167HLP Series, HM6267P Series. HM6267LP Series 


DP20NA 


IIM514256P Series. HM514236AP Series. I1M514236SP Series. HM514256HP Series. 11M.31 I238HI.P Series. 
HM5142SSSP Series 


DP22N 


HM6287P Series. HM6287LP Series 


DP-22NB 


IIM6288P Series. MM6288LP Series. HM6788P Series. HM6788HP Series. MM6287HP Series. HM6287HLP Series. 
NM6787P Series. HM6787HP Series 


01' -' I 


HM6116P Series. 11M8116LP Series. HMfil 16AP Series. HM6116ALP Sines 


DP-24A 


HM53461P Series. HM53482P Series 


DP-24N 


HM6116ASP Series, IIM6116ALSP Series 


DP-24NC 


IIM6716P Series, HM6719P Series. HM6789P Series. IIM6789HP Series. I1M62II8P Series. 11M6208LP Series, IIMfi2«8ltP Series. 
HM6208HLP Series. HM6708P Series. HM6207P Series. IIM6207LP Series. HM62()7Hi» Series. HM6207HLP Series. 11M67D7P Series 


DP 28 


HM6264P Series. HM6264LP Series. HM6264LP L Series, HM6264AP Series. HMG264ALP Series, HM6264ALP-L Series. 
IIM62256P Series. HM622S6LP Series. HM62236LP-L Series. HM65256AP Series. HM65256BP Series. HM65256BLP Series. 
IIN623257P. HN623258P. IIN62321P. HN62321BP. HN62.I31P. HN62321EP. HN62331EP. IIN62321AP. HN62331AP. HNSM64P, 
HN58C66P. HN58C256P, HN27128AP. HN27256P. HN27512P 


DP-28N 


HM6264ASP Series. IIM6264ALSP Series, 11M6264ALSP I. Series, HM65256ASP Series. MM65256BSP Series, 
HM65236BLSP Series. HM63021P Series 


DP-32 


IIM628128P Series. HM628128LP Series. HM658128DP Series. 1IM65256ASP Series. HM65256BSP Series. 
HN27C101P Series. HN27C301P Series 


DP-40 


HN62412P, HN62422P. HN62404P, HN62424P 


DP-42 


HN62408P. HN624U1SP 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 



PACKAGE INFORMATION 



• CERDIP 



Unit: mm (inch) Scale 1/1 



• DG-20N 

25.16(0.891) 



20 II 
nnnnnnnnnn 



ULJUUUUUULIU 

|| I 01 I 6<| |,IC 




(0040) (0061) 



■ftps pu 



2 54 : ?b 48 t I 

(0 lOOfOOiO) (0019x000a) 



I 4X- 



• DG-22N 




0.48 ± 1 2 54 10.25 

(0.01910.004) (010010.010) 



• DG-24V 



29.75 



run; 



'JLTT 

l.Ot 1.S4 

l uw (urn 




JiTlli 




iS4iO.« 0.41101 
(0 100 1 0.024) (0.0I9100O4) 



• DG-28 





2 541 25 

(0 10010010) 04810 I 5 o °' l5 ' 

(0019 1 0004) ~ 



.... 




• DG-28N 



34 71(1 367 ) 





48 to I 
(0.019 1 004) 




6 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • 



3 • (415) 589-8300 



• CERDIP 



PACKAGE INFORMATION 

Unit: mm (inch) Scale 1 /1 



• DG-32 



innnnnnn nnnn 



o 



■ []" .32 




l.lOOtO.llllll " (0.0I9± 0.004) 





• DG-40A 



40 




21 






o 
















J],! 32(0 05?) 


uu 


I 



2 54mai |. J | 2 54±0.25 
(O.lOOmai.) (0.100 ±0.010) 





Applicable ICs 



ix; 2on 


HM10480-15. HM10O48O-15 


DG22N 


HM10490 15, HM100490 Series 


DG-24V 


HM10500-15 


DG-28 


HN27128AG Series. MN27256G Series. HN27C256G Series. HN27C256AG Series. HN27C256HG Series. 
HN27512G Series 




DG-28N 


HM10494 Series, HM100494 Series 





DG-32 


HN27C101G Series, HN27C301G Series 


DG-40A 


HN27C1024HG Series 

i 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 




Applicable ICs 



ZP-16 IIM50256ZP Series. HM50257ZP Series. HM51256ZP Series. MM51256LZP Series 




HM514256ZP Series, HM5I4256AZP Series, HM514256SZP Series, HM514256HZP Series. HM51425SAZP Series 




ZP-20 


HM514258SZP Series. HM511000AZP Series. HM511000SZP Series. HMS1 1000HZP Series. HM511001AZP Series. 
HM511001SZP Series. HM511002AZP Series, HM511002SZP Series 




ZP-24 


HM53461ZP Series, HM53462ZP Series 


ZP-28 


HM534251ZP Series, HM534252ZP Series. HM534253ZP Series 



8 Hitachi America, Ltd. • Hitachi Plaza • 200o'sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Flat Package 



Unit mm (inch) Scale Vh 



• FP-24D 



3 OU'.U UUI 

I6 2lmax.(0 638ma« ) 

HHHHHBHHHHRfl 




; ■ 

V? 12 







40!gi, (0.050 t 0.006) J J 

(0016:888!) o 8 



• FP-28D 




lL_|_oi?:8it 







(0 03S) 








t 


40 'Si* 


j" 21 - 15 
(0.050 t 0.006 


1 


c 
£ 



• FP-28DA 




• FP-32D 



U.7Sm«i(0 750ma. ) 

flflHHRRHHflRRHHR 




28 15 





0' - 10 



) » 003) 



JJ7±0.I5 c 
Q ">'V~ IO 050r0.OO6) I 

(ooi6 ; =~;) 




(0.016-° ™) 



• FP-44A 




• FG-20D 



(0 006 ±0 002) 



60 



|o|o io(o.o oilH 



10.063) 



(0 031) 



u_T o.i 




0.43±0.l l.27±0.2 (0037 ± 0.007) 

(0.01 7 ±0.004) (0.050 1 008) 2.35max. 

(0.093max.) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 9 



PACKAGE INFORMATION- 



• Flat Packages (continued) 



• FG-28D 




• FG-24A 



11.31 l0.958IMAXil^r) 




53 



Applicable ICs 



FP-24D 


HMS116FF St-ries. HM6116LFP Series 


FP-28D 


HM6264FP Series. HM6264LFP Series. I1M6264LFPL Series. HM6264AFP Series, H.M626-IALFP Series 
1IM6264ALFP-L Series, HN58C65PP Series. HN58C66FP Series. HN58C256FP Series 


FP28DA 


HM6264FP Series. HM6264LFP Series. HM6264LFP-L Series. HM6264AFP Series. HM6264ALFP Series 
1IM62S4ALFP-L Series. HM62236FP Series. HM62256LFP Series. HM622S6SLFP Series. HM65256HFP Series. 
HM6r>2",6HLFP Series. HN6232f>7F. HN62323«F. HN62321F. 11N62321HF. IINH2331F. IIN62321EF. HN62331EF, HN58C65FP. 
HN58C66FP. HN58C256FP, IIN27C256FP 


FP32I) 


IIM628128FP Series. HM628128LFP Series. HM638128DFP Series. KM6S812SLFP Series. HN62321AF, 
HN62331AF. HN623II4BF. I1N62324HF. IIN27CKIIFP. I1N27C301FP 


FP--I4A 


HN62412F1'. HN62422FP. IIN624IMFP. IIN62424FP. IIN624II8F!' 


FG-20D 


HM10I50OI--I3 


FG-24A 


HMiOlSWF-iS 


FG-28D 


HMI0049F Series 



• TSOP Packages 



• TFP-32D 





17 




j 
















■0 


o 





(0.008*0.004) 



"'| [ii)".5o(o.o2o; 



[»To".oa(o.oo3)H 









1 • 2 


0.5010.10 






(0.020t0.004) 




~> 1 


20.0!0.2(0.787!0.008) 





«=£0-5' 



• TFP-32DA 



8.0(0.315) 



(0.00810.004) 



16 

| 10.50(0.020)1 
|»|0.08(0,00 3)®| 



ilD.Ha.D04) 



(0.02050. 004) 

i4.o;o.2 

(0.S5U0.0O8) 



-4 0-5' 



HITACHI 

1 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



PACKAGE INFORMATION 



• Leadless Chip Carrier 



• CG-22A 




1 1 1 il nnnnnnn Tl 



~ s 14 20_ 

uuuuuuu 



13 

10b 



nnnnnnn 



• CG-28 



-|S, uuuuluiiuu 



• CG-28A 




• CG-28B 



- "J 3 A 

ifra -fijaB B j I' 



• Flat Package (J-bend Leads) 



• CP-18 



im:»i!iOS;i:0OOS) 



i fir 

■illl 



| a|0 io(Q ~qq<H 



(SEATING Pl*« ) 



|| 0»:-V0 [7iii 

ID»I1;0MII jug 



"♦I Il.35±0 5(0 447 i0020) 



• CP-20D 



6 9(0 665) 



I7.27m.. (0 6«0m«. ) 



0.63min.(0.025mm.) 



1 M 

74(0 0?9) 




&l 0.1(0.004)1 



(SEATWG PLANE) 

431010 ^ 
(0.017 sO.004) 



s ? 



• CP-24D 



• CP-28D 



2 4!g £ 
(0.094 *S 

0.63mm. (O.OZSmin.) 




(0.094 
Q.63min. (0.025min.) 



^ o . i o i o ooa 7 ] 



0.a3±0. 10 
10 01 7±0 0041 



(SEATING PLANE) 

43±0 iO 
Oi 1±0 00* 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 1 



PACKAGE INFORMATION 

• Flat Packages (J-Bend Leads) (continued) 



Unit: mm (inch) Scale 1 1 / 2 



• CP-32D 




4* 



• CP-40D 




• CP-44 



• CD52 





Applicable ICs 



CG 22A 


HM6787CG Series. HM100490CG Series 


CG-28 


HM10490CG-15 


CG-28A 


HM2144CG Series. HMIOWflCG-13 HMIOI5WCG-I5 


CG-28B 


HM100500CG-18 


CP16 


HM.VI4fi4<T Series HMJieWCI* Series. |].Mii(>257CP Series. HM51256CP Series. HM51256LCP Series 


CP-20D 


HM5M256JP Series. IIM.iH256AJP. IIM514256SJP Series. IIM514256HJP Series. HM514258AJP Series. HM514258SJP Series. 
HM51inO(IAJP Series. 1IM511000SJP Series. HM51I000HJP Series. HM5110MAJP Scries. HM5U00JSJP Series. 
HM51 1002AJP Series. HM5I10II2SJP Series 


CP-24D 


HM6288JP Series. HM6288LJP Series. HM6289IP Series, HM6289LJP Series. HM6789JP Series. HM6789HJP Series. HM6287HJP 
Series. HM6287HLJP Series. HM6787HJP Series. HM6208I1JP Series. HM6208HLJP Series. HM6708JP Series. HM6207HJP Series. 
HM6207HLJP Series. HM6707JP Series, 


CP28D 


HM624256JP Series. HM534251JP Series. HM5342S2JP Series. HM 534253 JP Series 


CP-32D 


HM624257JP Series, HM624257I.JP Series 


CP-40D 


HM538121JP Series, HM538122JP Series. HM538123JP Series 


CP-44 


HM67C932 Series 


CP-52 


HM62A168 Scries. HM62AI88 Scries 



HITACHI 

12 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



■ RELIABILITY OF HITACHI IC MEMORIES 



1. STRUCTURE 

IC memories are basically classified into bipolar 
type and MOS type and utilized effectively by their 
characteristics. The characteristic of bipolar memo- 
ries is high speed but small capacity, instead, MOS 
memories have large capacity. There are also dif- 
ferences in circuit design, layout pattern, degree of 
integration, and manufacturing process. These 
memories have been produced with the standardized 
concept of design and inspection all through the 



processes of designing, manufacturing and inspec- 
tion. 

IC memories are constituted by the unit patterns 
called cells, which are integrated in high density. 
The knowhows based on our experience have been 
applied in every production stage. In addition, re- 
liability has been ensured using TEG (Test Element 
Group) evaluation. Examples of cell circuits of 
bipolar and MOS memories are shown in Table 1. 



• Table 1 Basic Cell Circuit of IC Memories 



Classification 



Bipolar memory 
(RAM) 



Bipolar memory 
(PROM) 



NMOS i 
(Dynamic RAM) 



NMOS, CMOS 

memories 
(Sialic RAM) 



NMOS memory 
(PROM) 



Application 



Buffer memory, 
control memory 
of high-speed 
computer 



Microcomputer 
control use 



Main memory of computer, 
microcomputer memory 



For 

microcomputer 
control 



Example of 
basic cell 
circuit 







T 



Jfi 



— 



X 




Dies of IC memories are produced in various pack- 
ages. In this process of packaging, Hitachi has also 
innovated new techniques and ensured to high level. 
As packages for IC memories, cerdip (glass-sealed) 
packages and plastic packages are currently used. 
Also such packages as LCC (Leadless Chip Carrier) 
or SOP (Small Outline Package) have been devel- 
oped for high density packaging. Cerdip packages 
sealed hermetically are suitable for equipment re- 
quiring high reliability. Plastic packages are widely 
applied to many kinds of equipment. Hitachi 
plastic packages have been improved the reliability 

• Table 2 IC Memory Package Outline 



level as highly as that of the hermetically sealed 
packages. Table 2 shows the outlines of the Hitachi 
packages. 



> Cerdip 
• 16 pin 



18 Pin 



' 20 Pin 



• 24 Pin 






HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 3 



Reliability of Hitachi IC Memories 

■ Cerdlp (continued) 



• 28 Pin with Lid • 32 Pin with Ud 




• 22 Pin • 24 Pin 



■ SOP ■ PLCC ■ SOJ 

• 24 Pin • 28/32 Pin • 18 Pin • 20/26/28/32 Pin 



■ Leadless Chip Carrier 
• 20 Pin 



HITACHI 

1 4 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Reliability of Hitachi IC Memories 



2. RELIABILITY 

Results of reliability tests are listed below. 

2.1 Reliability Test Data on Bipolar Memories 

The reliability test data on the bipolar memories are 
shown in Table 3 and 4. Since they are manufac- 
tured under the standardized design rules and quali- 



ty control, there is no difference in reliability 
among the various types. And the larger the capac- 
ity is, the higher the reliability per bit becomes. 



• Table 3 Results on Bipolar Memory Reliability Test (1) 





HM10480-15 


HM2144CG 


Test item 


Test 
condition 


Sam- 
ples 


Total 
component 
hours 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


Test 
condition 


Sam- 
ples 


Total 
component 
hours 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


High- 
temperature 
(Operating) 


r a =125°C 
VEE=-5.2\ 


340 


C.H. 
3.4x10 s 





1/h 
2.7x10"' 


7a=125°C 
VEE=-5.2V 


120 


C.H. 
1.2x10 s 





1/h 
7.7x10"' 


High-temp 
storage 


r a =200°C 


351 


3.51x10 s 

' 





2.6xl0" s 


r a =200°C 


120 


1.2x10 s 





7.7x10"' 



• Table 4 Results on Bipolar Memory Reliability Test (2) 



Test item 


Test condition 


HM10480-15 


HM2144CG 


Samples 


Failure 


Samples 


Failures 


Temperature cycling 


-55°C to +150°C, 10 cycle 


160 





180 





Soldering heat 


260"C, 10 seconds 


35 





22 





Thermal shock 


0°C to +100°C, 10 cycles 


50 





50 





Mechanical shock 


1500G, 0.5ms, Three times each for X, 
YandZ 


30 





22 





Variable frequency 


100 to 200 Hz, 20G, Three times each 
for X, Y and Z 


40 





22 





Constant-acceleration 




20000G, 1 minute, each for X, Y and Z 


40 





22 






2.2 Reliability test data on Hi BiCMOS memory 

Hi-BiCMOS memory is newly designed based on the 
latest fine machining technologies (2m ~ 1m), 
which features low electric consumption / high 
integrity by CMOS and high speed / high drivability 
by bipolar. This device also attains high speed close 
to ECL and low electric consumption as CMOS. 
Input and output level supports both ECL and TTL. 
Reliability test data of HM100490-15 (64k-words x 
1-bit) and HM6788P-25 (16k-words x 4-bits) are 



listed in table 5 and table 6. 

The above shows the sufficient reliability of high 
speed Hi-BiCMOS in the normal use with some 
limitations considered from its own circuit com- 
position. For further information, see each data 
sheet. Besides the caution points with CMOS and 
bipolar device, avoid abnormal use as in deformed 
or slow wave form which causes malfunction and 
latch up. 



Table 5 Results on Hi-BiCMOS Memory Reliability Test (1) 





HM100490-15 (Cerdip) 




HM6788P-25 (Plastic) 


Remarks 


Test item 


Test 
condition 


Samples 


Total test 
time 


Failures 


Failure 
rate 


Test item 


Test 
condition 


Samples 


Test test 
time 


Failures 


Failure 
rate 


High- 
tempera- 
ture 
pulse 
opera- 
tion 


Ta = 125°C 
F£E=-4.5V 


380 


C.H. 
3.8x10 s 





1/h 
2.4x10"' 


High- 
tempera- 
ture 
pulse 
opera- 
tion 


Ta - 125°C 
vcc - 5.0V 


420 


C.H. 
4.2x10 s 


i*» 


1/h 
4.8x10"' 


*1 

foreign 
matter 






Moisture 
endur- 
ance 


85°C85%RH 
5V 


210 


2.1x10 s 





4.8x10"' 




High- 
temp, 
storage 


Ta=200°C 


330 


3.3x10 s 





3.0x10"' 


Pressure 
cooker 


121°C100%RH 


80 


0.16x10 s 





6.3x10-' 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 5 



Reliability of Hitachi IC Memories- 



Table 6 Remits on Hi-BiCMOS Memory Reliability Test (2) 



Test item 


Test condition 


HM100490-15 (Cerdip) 


HM6788P-25 (Plastic) 


Samples 


Failure 


Samples 


Failure 


Temperature cycling 


-55°C ~ -150°C 100 cycles 


180 





180 





Soldering heat 


250°C 10 seconds 


22 





22 





Thermal shock 


0°C ~ 100°C 10 cycles 


50 





50 





Mechanical shock 


1500G, 0.5ms Three times each 
for X, Y and Z 


22 









Variable frequency 


100 ~ 200Hz, 20G Three times each 
for X, Y and Z 


22 









Constant acceleration 


20000G, 1 minute, each 
for X, Y and Z 


22 










2.3 Reliability test data on MOS memories 

2.3.1 Reliability test data on MOS DRAM and 
SRAM 

Table 7 and table 8 shows the reliability test data on 
the representative types of 1M DRAM (HM5110007 
HM514256), 256k SRAM (HM62256) 1M SRAM 
(HM628128FP). 

• Table 7 Reliability Data on 1M DRAM 



The life test is performed at high temperature and 
high voltage to evaluate the reliability of products 
using fewer samples. All failures are caused in 
manufacturing process, so we feedback the data into 
manufacturing process to improve the quality and 
reliability. 



Test item 


Test 
condition 


HM511000P/HM514256P 
Series (DIP) 


HM511000JP/HM514256JP 
Series (SOP) 


Remarks 


Sam- 
ples 


Total 
test time 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


Sam- 
ples 


Total 
total time 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


High- 
temperature 
pulse operation 


125°C/5.5V 


300 


6.00x10 s 





1.53x10-* 


200 


4.00x10 s 





2.30x10"' 


*1 

Oxide film 
Failure xl 


125°C/7V 


1252 


4.50x10 s 


1* 


4.48x10-' 


3186 


9.34x10 s 





9.85xl0" 7 


150°C/7V 


200 


4.00x10 s 





2.30x10"' 


200 


4.00x10 s 





2.30x10"' 


Moisture 
endurance 


85°C 85% RH 
5.5V 




8.40x10 s 






1.10x10"' 


682 


1.36x10' 





6.74x10"' 


Pressure 
cooker 


121°C/100% 
RH 


150 


4.50xl0 4 


2.04xl0" s 


200 


6.00xl0 4 





1.53xl0" s 



* Confidence level 60% 

• Table 8. Reliability Data on 256K and 1M SRAM 





Test 
condition 


HM62256FP (SOP) 


HM628128FP (SOP) 




Test item 


Sam- 
ples 


Total 
test time 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


Sam- 
ples 


Total 
total time 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


Remarks 


High- 
temperature 
pulse operation 


125°C/5.5V 


3088 


3.11x10' 





8.88x10"' 


1038 


1.04x10' 





8.86x10"' 




125°C/7V 


455 


4.55x10 s 





2.02x10"' 


951 


5.33x10 s 




3.79x10"' 


*1 

Foreign x 2 


150°C/7V 


103 


1.00x10 s 


l* 1 


2.02xl0" s 


80 


1.60x10 s 





5.75x10"' 


Moisture 
endurance 


85°C/85% 
RH 7V 


680 


6.80x10 s 





1.35x10"' 


127 


2.54x10 s 





3.62x10"' 


*2 Leak x 1 


Pressure 
cooker 


121°C/100% 
RH 


320 


6.40x10' 


l* 2 


3.16x10"' 


90 


2.70x10* 





3.41xl0" s 





* Confidence level 60% 



16 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Reliability of Hitachi IC Memories 



2.3.2 Reliability Test Data on EPROM 
EPROM has two types; conventional EPROM with 
transparent window and one time programmable 
ROM (OTPROM) packaged in plastic package. Table 



9 shows reliability test data on the representative 
EPROM types 512k EPROM (HN27512, 
HN27512P), 1M EPROM (HN27C101, HN27C301). 



• Table 9. Reliability Data on 512K and 1M EPROM 





Test 
condition 


HN27512 (Cerdip/Plastic) 


HN27C101/HN27C301 




Test item 


Sam- 
ples 


Total 

test time 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


Sam- 
ples 


Total 
total time 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


Remarks 


High- 
temperature 
operation 


125°C/5.5V 


200 


3.72x10 s 





2.47x10"' 


180 


3.24x10 s 





2.84x10"' 




125°C/7V 


530 


7.95x10 s 





1.16x10"' 


327 


6.54x10 s 





1.41x10"' 


*1 

Data 


High- 
temperature 
bake 


175°C 


260 


4.91x10 s 





1.87x10"' 


150 


7.5x10 s 





1.23x10"' 


dissipation x 49 


200°C 


240 


3.72x10 s 


] *1 


5.43x10"' 


130 


6.49x10 s 


1*1 


3.11x10-' 




250°C 


180 


1.89x10 s 


7 *i 


4.44xl0" s 


110 


3.07x10 s 


40*' 


1.30x40" 4 




Moisture 
endurance 


85°C/85% 
RH5.5V 


290 


5.22x10 s 





1.76xl0 -6 










Data of 512K 
OTPROM 


Pressure 
cooker 


'l21°C/100% 
RH 


50 


0.10x10 s 





9.20xl0" s 











* Confidence level 60%. 



The failure shown in table 9 is due to the data dis- 
sipation in memory cells. Getting thermal energy, 
electrons in memory cells are activated and go 
through the floating gate. In actual usage, however, 
it has no problem because this phenomenon de- 
pendes on temperature (about 1.0eV of activated 
energy) greatly. The moisture resistance of 
OTPROM is also satisfactory. 



Table 10 shows the example of PROM derating. 
When derating, the parameter is generally only the 
temperature because other operating conditions are 
specified. Especially to lower the junction tempera- 
ture during mounting is important for stabilizing the 
operation relative to access time, refresh time and 
other characteristics. 



• Table 10 Example of HN27C101/HN27C301 Derating 



Factor 


Temperature 


Failure criteria 


Electrical Characteristics, 
Function Test 


Failure mechanism 


Increase of leak current 
and others 



Results: 

The result from high temperature baking of PROM 
is shown in the right figure. 



£ to' 

i 











































L p 
/l t 


p p t. 

T 7 1 


T T 


7 



2.0 2.5 3.0 3.5 

lOVTj Or*) 



Note: Decreasing junction temperature shown in the figure will promise the higher reliability. The junction temperature 
can be calculated by a formula : T; = T a + 9i«-Prt 6-.~ in about 100°C/W with no air flow and about 60 to 
70°C/W with 2.5 m/s air flow. ' ' ' 



HITACHI 

Hitachi America, Ltd. • Hitachi Plara • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 7 



Reliability of Hitachi IC Memories 



2.3.3 Reliability Data on MASK ROM 

Table 9 shows the reliability test data on 2M and 

4M bit MASK ROM. MASK ROM is patterned ac- 



cording to ROM information in manufacturing 
process, so data dissipation isn't occurred in high 
temperature like EPROM and EEPROM. 



• Table 11. Reliability Data on 2M and 4M MASK ROM 



Test item 


Test 
condition 


HN62412P (Plastic) 


HN62404P (Plastic) 


Remarks 


Sam- 
ples 


Total 
test time 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


Sam- 
ples 


Total 
test time 


Fail- 
ures 


Failure 
rate* 
(1/hr) 


High-temp. 

pulse 

operator! 


125°C/5.5V 










200 


4.0xl0 5 









125°C/7V 


120 


1.2x10' 





7.67xl0 -6 


300 


3.0x10 s 





3.0xl0" 6 


Moisture 
endurance 


85°C/85% 
RH 5.5V 


120 


1.2x10 s 





7.67x1 0- 6 


120 


1.20x10 s 





7.67x10-* 


Pressure 
cooker 


m'ci 

100% RH 


45 


2.3x10" 





4.1xl0" s 


45 


2.3x10" 





4.1xl0" s 



* Confidence level 60%. 

2.3.4 Reliability Data on MOS Memory (The result 

of environment test) 
Table 12 shows examples of each environment test 
data. They show good results without any failure 
even in severe environment. 

V TH of MOS transistor is one of the basic process 

• Table 1 2 Reliability Data on MOS Memories 



parameters in MOS memory, which has almost no 
change using surface stabilization technology and 
clean process. Figure 4 shows the examples of time 
changes for 1M DRAM; V DD min. (V mln ) and 
access time (t RAC ) in high temperature pulse test. 



Test item 


Test condition 


HM511000P 
(DIP) 


HM511000JP 
(SOJ) 


HM62256FP 
(SOP) 


HM628128FP 
(SOP) 


EPROM 
(Cerdip) 


Remarks 


Sam- 
ples 


Fail- 
ure 


Sam- 
ples 


Fail- 
ures 


Sam- 
ples 


Fail- 
ures 


Sam- 
ples 


Fail- 
ures 


Sam- 
ples 


Fail- 
ures 


Temperature cycling 


-55°C to 150°C 
10 cycle 


3755 





2786 





3328 





710 





2790 







Temperature cycling 


-55°C to 150°C 
500 cycle 


150 





200 





482 





105 





450 





Thermal shock 


-65°C to 150°C 
15 cycle 


77 





100 





76 





77 





80 





Soldering heat 


260°C, 
10 seconds 


22 





22 





22 





22 





22 





Mechanical shock 


1.500G, 0.5ms 


















38 





Variable frequency 


100 to 2,000Hz 
20G 


















38 





Constant-acceleration 


6000G 


















38 





•6.000G 



2.4 Change of Electrical Characteristics on IC 
Memory 

The degradation of I C bo and h FE are the main 
factors of degradation in inner cell transistor of 
bipolar memory. In actual element designing, how- 



ever, it is designed to operate in the range at which 
no degradation happen. Therefore no change of 
characteristics including access time are observed. 
Time dependence in access time for HM10470 are 
shown in Fig. 1 . 



HITACHI 

1 8 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



-Reliability of Hitachi IC Memories 



Figure 1 Time change in access time for bipolar memory 



Example 



Example of time change in access time for Bipolar memory 



Device name 



Test condition 



Failure criteria 



Failure mechanism Surface degration 



HM10480-15 



7fl = 125°C, V EE = -5.2V 



'AA = l^ns 



Results: 

Access time is stabilized. 



20 ■ 



15- 



Test Condition 
V EE = -5.2V 
Ta = 25X: 

Marching Pattern 



i 



Maximum 
Ave rage 
Minimum 



500 



1,000 

Time Ihr) 



2.000 



Figure 2 Time change in access time for Ht-BiCMOS memory 



Example 



Example of time change in access time for Hi-Bi CMOS memory 




Device name 



Test condition 



Failure criteria 



Failure mec 



Results: 
Access time 



HM100490 



Ta = 125°C, K £ f = -4.5V 
all bit scanning 



l AA = l^ns 



Surface 



20- 



10 



Tot Condition 

V„ = -4.5V 

Ta=e5t; 

Marching Pattern 



— I 



500 1,000 

Time 1 hr 1 



2,000 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, GA 94005-1819 • (415) 589-8300 



19 



Reliability of Hitachi Memories 



Figure 3 Time change in Vqc min » ntl X AA ' or Hi-BiCMOS memory 



Example 



Examples of time change in Vqc min an d l AA f° r Hi-Bi CMOS 
memory 



Device name 



Test condition 



Failure criteria 



Failure mechanism 



HM6788P-25 



5 - 



Ta= 125°C, F CC = 5.0V 
all bit scanning 



V C C " 4.5V, tAA = 25ns 



Surface degradation 



„ 4 
> 

£ 3 
E 

s 2 



. s — § — fr- 



Results: 

Both of Vqq (min) and (44 are stabilized. 



Test Condition . . 

Maximum 

rjL. Marching Pattern 



Minimum 



500 1 ,000 
Time (hr) 



•30- 



25 



20 



15 



Test Condition 
Same as above 



500 1.000 
Time (hr) 



2,000 



Figure 4 Time change in VoD mm snd r /?/4C for MOS memory 



Example 



Example of time change in Vjjj) min and tRAC for MOS memory 



Device name 



Test condition 



Failure criteria 



Failure 



HM511000P 



Ta =125°C, K CC = 7V 
all bit scanning 



Surface degradation 



Results: 

Access time (f^yj) is stabilized and is within the failure 
criteria. 



1 



Test Condition 



w . . „ T Maximum 
Marching pattern i Ayerage 

1 Minimum 



r«=25"C 
N=200pcs 



Time (hr) 



Note: Test accuracy is 0.2V, 2ns. 



Test Condition 
Same as above 



1 



4—1 



■ 1 IW 



Time (hr) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Reliability of Hitachi Memories 



2.5 Failure Mode Rate 

Figure 5 and 6 show examples of failure mode 
happened in users' application. Since IC memories 
require the finest pattern process technology, the 
percentage of failures, such as pinholes, defects on 
photoresist and foreign materials, tends to increase. 
To eliminate the defects in the manufacturing 




Figure 5 Failure Mod. Rate of Bipolar Memory 

3. Reliability of Semiconductor Devices 

3.1. Reliability Characteristics for Semiconductor 
Devices 

Hitachi semiconductor devices are designed, manu- 
factured and inspected so as to achieve a high level 
of reliability. Accordingly, system reliability can be 
improved by combining highly reliable components 
along proper environmental conditions. This 
section describes reliability characteristics, failure 
types and their mechanisms in terms of devices. 
First, semiconductor device characteristics are 
examined in light of their reliability. 

(1) Semiconductor devices are essentially structure 
sensitive as seen in surface phenomenon. Fab- 
ricating the device requires precise control of a 
large number of process steps. 

(2) Device reliability is partly governed by elec- 
trode materials and package materials, as well as 
by the coordination of these materials with the 
device materials. 

(3) Devices employ thin-film and fine-processing 
techniques for metallization and bonding. Fine 
materials and thin film surfaces sometimes 
exhibit physically different characteristics from 
the bulks. 



process, Hitachi has improved the process and 
performed 100% burn in screening under high tem- 
perature. Hitachi has been collecting and checking 
customers' process-data and marketing data for 
higher reliability of our products. To analyze them 
is very helpful for the improvement of designing and 
manufacturing. 




Figure 6 Failure Mode Rate of MOS Memory 

(4) Semiconductor device technology advances 
drastically: Many new devices have been 
developed using new processes over a short 
period of time. Thus, conventional device re- 
liability data cannot be used in some cases. 

(5) Semiconductor devices are characterized by 
volume production. Therefore, variations 
should be an important consideration. 

(6) Initial and accidental failures are only con- 
sidered to be semiconductor device failures 
based on the fact that semiconductor devices 
are essentially operable semipermanently. 
However, wear failures caused by worn mate- 
rials and migration should be also reviewed 
when electrode and package materials are not 
suited for particular environmental conditions. 

(7) Component reliability may depend on device 
mounting, conditions for use, and environment. 
Device reliability is affected by such factors as 
voltage, electric field strength, current density, 
temperature, humidity, gas, dust, mechanical 
stress, vibration, mechanical shock, and radia- 
tion magnetic field strength. 



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Reliability of Hitachi IC Memories 



Initial failure region 

: Declining failure rates (m<l) 




Figure 7 Typical failure rate curve 

Device reliability is generally represented by the 
failure rate. 'Failure' means that a device loses 
its function, including intermittent degradation 
as well as complete destruction. 
Generally, the failure rate of electric com- 
ponents and equipment is represented by the 
bathtub curve shown in Fig. 7. For semicon- 
ductor devices, the configuration parameter of 
the Weibull distribution is smaller than 1, which 
means an initial failure type. Such devices 
ensure a long lifetime unless extreme environ- 
mental stress is applied. Therefore, initial and 
accidental failures can become a problem for 
semiconductor devices. Semiconductor device 
reliability can be physically represented as well 
as statistically. Both aspects of failures have 
been thoroughly analyzed to establish a high 
level of reliability. 

3.2 Failure Types and Their Mechanisms 
3.2.1 Failure physics 

Failure physics is, in a broad sense, a basic tech- 
nology of "physics + engineering". It is used to 
examine the physical mechanism of failures in terms 
of atoms and molecules to improve device reliabili- 
ty. This physical approach was introduced to the 
reliability field with the demand for minimized de- 
velopment cost and period, as technology rapidly 
developed and system performance increased, re- 
quiring more complex and higher levels of reliabili- 
ty. These conditions derived from the development 
of solid state physics (semiconductor physics) after 
World War II and associated device development. 
Failure physics have been employed to: 

1) Detect failed devices as soon as possible 

2) Establish models and equation used for failure 
prediction 

3) Evaluate reliability in short periods by acceler- 
ated life test 

The purpose of the failure physics approach is to 



contribute to reliability related fields such as 
product design, prediction, test, storage and usage 
by adding physics as a basic technology to conven- 
tional experimental and statistical approaches. 

3.2.2 Failure types and their mechanism 
Device failures are physically discussed in this 
section. Semiconductor device failures are basically 
categorized as disconnection, short-circuit, de- 
terioration and miscellaneous failures. These 
failures and their causes are summarized in Table 
11. Typical failure mechanisms are reviewed next. 

(1) Surface Deterioration 

The pn junction has a charge density of 10 14 — 
10 20 /cm 3 . If charges exceeding the above density 
are accumulated on the pn junction surface, partic- 
ularly adjacent to a depletion layer, electric 
characteristics of the junction tend to be easily 
varied. Although the surface of such devices as 
planar transistors is generally covered with a SiOj 
film and is in an inactive state, the possibility of 
deterioration caused by surface channels still exists. 
Surface deterioration depends heavily on applied 
temperature and voltage and is often handled by the 
reaction model. 

One example of recent failures is surface deteriora- 
tion caused by hot carriers. Hot carriers are 
generated when such devices as MOS dynamic 
RAMs are operated at a voltage near the minimum 
breakdown voltage BV DS by raising internal voltage 
and when a strong electric field is established near 
the MOS device's drain resulting from reduced de- 
vice geometry from 2 to 0.8 /im. Generated hot 
carriers may affect surface boundary characteristics 
on a part of the gate oxide film, resulting in de- 
gradation of threshold voltage (V TH ) and counter 
conductance (gm). Hitachi devices have employed 
improved design and process techniques to prevent 
these problems. However, as process becomes finer, 
surface deterioration may possibly become a serious 
problem. 

(2) Electrode-related Failures 
Electrode-related failures have become increasingly 
important as multi-layer wiring has become more 
complicated. Noticeable failures include electro- 
migration and Al wiring corrosion in plastic sealed 
packages. 

(T) Electromigration 

This is a phenomenon in which metal atoms are 
moved by a large current of about 10 6 A/cm J 
supplied to the metal. When ionized atoms collide 
with current of about scattering electrons, an 
'electron wind' is produced. This wind moves the 



22 



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Reliability of Hitachi IC Memories 



metal atoms in the opposite direction from the 
current flow, which generates voids at a negative 
electrode, and hillock and whiskers at an opposite 
one. The generated voids increase wiring resistance 
and cause excessive currents to flow in some areas, 
leading to disconnection. The generated whiskers 
may cause shortcircuits in multi-metal line. 

(2) Multi-metal line related failures 

Major failures associated with multi-metal line 
include increased leak currents, shortcircuits caused 
by a failed dielectric interlayer, and increased 
contact metal resistance and disconnection between 
metal wirings. 

(3) Al line corrosion and disconnection 

When Plastic encapsulated devices are subjected to 
high-temperatures, high-humidity or a bias-applied 
condition, Al electrodes in devices can cause corro- 
sion or disconnection (Fig. 8). Under high-tempera- 
ture and high-humidity, corrosions are randomly 



Moiture Resistance Test 



High Temp and 
High Humidity 



High Temp and 
High Himidity 
and Bias 



Higher Potential 




Lower Potential 


Are. 




Are. 



3 



Pit Corrosions Pit Corrosions 

Figure 8 Categorized Al corrosion mode 

generated over the element surface. However, after 
an extended period of time, the corrosions have not 
significantly increased. Accordingly, this failure is 
possibly due to an initial failure associated with 
manufacturing. It is also verified that this type of 
failure can be generated when the adhesion surface 
between an element and resin is separated or when 
foreign materials are attached to the element with 
human saliva. Under a bias-appllied, high-tempera- 
ture, high-humidity condition, on the other hand, 
corrosions are generated in higher potential areas 
while in lower potential areas, grain corrosion 
occurs. Once this failure occurs in part of a device, 
the device can become worn out in a relatively short 
time. This failure proves to depend on the hydro- 



scopic volume resistivity of sealed resin. The Al line 
corrosion mechanism described above is summarized 
in Fig. 9. 



Moisture 




Melting 




Penetration 




Corrosive Impurity 


Mechanism 




Chip-resin Boundary' 
Separated 



Figure 9 Plastic package cross section i 
mechanism 




Test Time (hrs) 



Figure 10 An Example of Moisture Resistance by High 
temp, and High humidity and bias 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 23 



Reliability of Hitachi IC Memories 



10' 



10' 



3 
J 

Iff 



10 























































































































































































































































































































































































































































































































. — 






































































































































































































u u 


J 


— u 








'.J 






































1 I 




-t- 















2.0 2.5 3.0 3.5 



TempenUure 1/T (10VTC) 

Figure 1 1 Relationship between temperature and 
Time to 1% failure (RH = 85%) 

(3) Bonding related failures 
(T) Degradation caused by intermetallic formation 
Bonding strength degradation and contact resistance 
increase are caused by compounds formed in con- 
nections between Au wire and Al film or between 
Au film and Al wire. These are the most serious 
problems in terms of reliability. The compounds 
are formed rapidly during bonding and are increased 
through thermal treatment. Consequently, Hitachi 
products are subjected to a lower-temperature, 
shorter-period bonding whenever possible. 
© Wire creep 

Wire creep is wire neck destruction in an Au ball 
along an intergranular system occurring when a 
plastic sealed device is subjected to a long-term 
thermal cycling test. This failure results from 
increased crystal grains due to heat application 
when forming a ball at the top of an Au wire, or 
from an impurity introducing to the intergranular 
system. Bonding under usual conditions with no 
loop configuration failures does not cause this 
failure unless a severe long-term thermal cycling test 
is applied. Accordingly, wire creep is not a problem 
in actual usage. 
(3) Chip crack 

With the increase in chip size associated with the 
increased number of incorporated functions, more 
problems have been occurring during assembly, such 
as chip cracks during bonding. Bonding methods 



include Au-silicon eutectic, soldering and Ag-paste. 
Soldering and Ag-paste exhibit few chip crack 
problems. For Au-silicon eutectic, in contrast, large 
stress is applied to a pellet due to its strength and 
high temperature resistance for attachment, which 
may result in critical chip defects. Today, the chip 
destruction limit can be determined by finite- 
element analysis and by distortion measurement 
using a fine accuracy gauge. Ideally, Au-silicon 
eutectic should be evenly applied over the entire 
surface. However, this is difficult due to the 
existence of a silicon oxide film on the silicon back 
surface. Therefore, specifications for Au-silicon 
eutectic have been established based on stress 
analysis and thermal cycling test results. 
(4) Reduced maximum power dissipations 
For power devices, heat fatigue due to thermal 
expansion coefficient mismatch among different 
materials deteriorates thermal resistance. This 
results in decreased maximum power dissipations. 

(4) Sealing related failures 

Hermetic sealing packages, including metal, glass, 
ceramic, and all other types, have the possibility of 
the following failures. 

1. Al line corrosion on the chip surface due to slight 
moisture and reaction between the different 
ionized materials. 

2. Intermittent moving foreign metals short 

3. Al line corrosion due to extraneous H 2 caused 
by hermetic failure 

Moving foreign matter, even if it is a non-active 
solid, can be charged up within a cavity during move- 
ment, thereby inducing parastic effects and metal 
shorts. The foreign matter detection method is 
specified by MIL-STD-883C, PIND (Particle Impact 
Noise Detection) Test. The PIND test consists of 
filtering a particle impact waveform (ultrasonic 
waveform), detecting it with a microphone, and 
then amplifying. 

(5) Disturbance 

©Electrostatic discharge destruction 
Destruction caused by electrostatic discharge is a 
problem common to semiconductor devices. A 
recent report introduced three modes of this failure; 
the human body model, charged device model and 
field induced model. 

The human body is easily charged. A person just 
walking across a carpet can be charged up to 15000 
V. This voltage is high enough to destroy a device. 
An equivalent circuit of the human body model is 
shown in Fig. 10. The human body's capacitance 
Cb and resistance Rb are 100 to 200 pF and 1000 
to 2000H, respectively. Assuming a body is charged 



HITACHI 

24 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



with 2000V, the dissipated energy is obtained as 
follows: With a time constant of 10" 7 sec, the dis- 
sipated energy is 2 KW, which is enough to destroy 
a small area of a chip. 

I |f — wv — w*— 

Cb Rb Rd Re 

Ttr 

Cb — Human Body Capacity 
Rb — Human Body Resistance 
Rd — Device Resistance 

Re — Resistance Between Device and Ground 

E= y CbV =0.2x 1(T 3 J 
Figure 12 Equivalent circuit of human body model 

In the charged device model, charges are accumulat- 
ed in a device, not a human body, and discharged 
through contact resistance during a short time. The 
equivalent circuit of this model is shown in Fig. 13. 
Device size and device position relative to GND are 
important parameters in this model since the model 
depends on device capacity. 

In the field induced model a device is left under a 
strong electric field or is affected by neighboring 
high voltage material. Since the capacitor of device 
or lead of device acts like an antenna, the following 
cases will possibly cause destruction. 1) a device is 
incorporated into a high electric field such as a 
CRT, 2) a device is left under a high-frequency 
electric field and 3) a device is moved with a con- 
tainer charged at high voltage, such as a tube. 



v»> WV 




Figure 13 Equivalent circuit of charging model 

(2) Latch up 

Latch up is a problem unique to CMOS devices. 
This problem is a thyristor phenomenon caused by 
a parasitic PNP or NPN transistor formed in the 
CMOS configuration. Latch up occurs when an 
accidental surge voltage exceeding a maximum 
rating, a power supply ripple, an unregulated power 
supply and noise is applied, or when a device is 
operated from two sources having different set-up 
voltages. These cases can cause input or output 
current to flow in the opposite direction from usual 
flow, which triggers parasitic thyristors. This results 
in excessive current flowing between a power supply 



Reliability of Hitachi IC Memories 

and ground. This phenomenon continues until the 
power is off or the flowing current is forced to be 
reduced to a certain level. Once latch upoccurs in an 
operating device, the device will be destroyed. 
Much effort should be made in designing circuits to 
prevent latch up. Latch up triggering input or 
output currents start to flow under the following 
conditions. 

Vin <Vcc or Vin < GND for input level 
Vout > Vcc or Vout < GND for input level 
Therefore, circuits should be designed so that no 
forward current flows through the input protection 
diodes or output parasitic diodes. 
(3) Soft errors 

When a particles are generated from uranium or 
thorium in a package the silicon surface of an LSI 
chip, electron-hole pairs are formed which act as 
noise to data lines and other floating nodes, causing 
temporary soft errors. This phenomenon is shown 
in Fig. 14. Only electrons from among the electron- 
hole pairs are only collected to a memory cell. As a 
result, the cell changes from a state of 1 to 0, which 
is a soft error. 

Hitachi devices have been subjected to simulation 
and irradiation tests to prevent soft errors. In some 
cases, organic material, PIQ, is applied to the surface 
of the device. 



a 




Figure 14 Soft error caused by a particles in dynamic 
msmory 



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Reliability of Hitachi Memories 



Table 1 3. Failure causes and mechanism 



Failure related causes 


Failure mechanisms 


Failure modes 


Passivation 


Surface oxide film, 
Insulating film between 
wires 


Pin hole, Crack, Uneven 
thickness, Contamination, 
Surface inversion, 
Hot carrier injected 


Withstanding voltage 
reduced, Short, Leak 
current increased, 
hpE degraded, Threshold 
voltage variation, Noise 


Metallization 


Interconnection, 
Contact, Through hole 


Flaw, Void, Mechanical 
damage, 

Break due to uneven 
surface, Non-ohmic 
contact. Insufficient 
adhesion strength, 
Improper thickness, 
Electromigration, 
Corrosion 


Open, Short, 
Resistance increased 


Connection 


Wire bonding, 
Ball bonding 


Bonding runout, 
Compounds between metals, 
Bonding position mismatch, 
Bonding damaged 


Open, Short 
Resistance increased 


Wire lead 




Internal connection 


Disconnection, 
Sagging, Short 




Open, Short 


Diffusion, Junction 


Junction diffusion, 
Isolation 




Crystal defect, 
Crystallized impurity, 
Photo resist mismatching 


Withstanding voltage 
reduced, Short 


Die bonding 


Connection between die 
and package 


Peeling chip, Crack 


Open, Short, Unstable 
operation, Thermal 
resistance increased 


Package sealing 


Packaging, Hermetic 
Seal, Lead plating. 
Hermetic pakage & 
plastic package, Filler gas 


Integrity, 
moisture ingress, 
Impurity gas, High 
temperature, Surface 
contamination. Lead 
rust. Lead bend, break 


Short, Leak current 
Increased, Open, Corrosion 
disconnection, Soldering 
failure 


Foreign matter 


Foreign matter in package 


Dirt, Conducting foreign 
matter, Organic carbide 


Short, Leak current 
increased 




Input/output pin 


Electrostatistics, 
Excessive Voltage, Surge 


Electron destroyed 


Short, Open, Fusing 


Disturbance 


a particle 


Electron hole generated 


Soft error 


High electric field 


Surface inversion 




Leak current increased 



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Reliability of Hitachi IC Memories 



(6) Fine geometry related problems 
In response to higher integration requirements for 
memories and microcomputers, LSI geometry has 
been reduced in the way of 3 ^im -* 2 pm ■* 1 .3 pm 
->-0.8 Mm. 



However power supply has not been scaled down 
used for 5V, only line dimensions have been fined 
increasingly. Problems associated with finer geo- 
metry are shown in Table 14. 



Table 14. Finer geometry related problems 



Item 


Problems 


Countermeasure 


5V single supply voltage 


• Breakdown voltage of gate oxide films 


Oxide film formation process improved 

• Cleaning 

• Gettering 

• Screening 


Horizontal dimension 
reduction 


• Soft errors by a particles 

• Al reliability reduced 

• CMOS latch up 

• Mask alignment margin reduced 

• Hot carriers 


Surface passivation film improved 

• Metallization improved 

• Design/layout improved 

• Process improved 


Vertical & horizontal 
dimension reduction 


• Higher breakdown voltage not permitted 

• Electrostatic discharge resistance reduced 


Use of low voltage examined 

• Configuration improved 

• Protection circuits enhanced 















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■ QUALITY ASSURANCE OF IC MEMORY 



1. VIEWS ON QUALITY AND 
RELIABILITY 

Hitachi basic views on quality are to meet individual 
users' purpose and their required quality level and 
also to maintain the satisfied level for general ap- 
plication. Hitachi has made efforts to assure the 
standardized reliability of our IC memories in actual 
usage. To meet users' requests and to cover expand- 
ing application, Hitachi performs the followings; 

(1 ) Establish the reliability in design at the stage of 
new product development. 

(2) Establish the quality at all steps in manufactur- 
ing process. 

(3) Intensify the inspection and the assurance of re- 
liability of products. 

(4) Improve the product quality based on market- 
ing data. 

Furthermore, to get higher quality and reliability, 
we cooperate with our research laboratories. 
With the views and methods mentioned above, 
Hitachi makes the best efforts to meet the users' re- 
quirements. 

2. RELIABILITY DESIGN OF 
SEMICONDUCTOR DEVICES 

2.1 Reliability Target 

Establishment of reliability target is important in 
manufacturing and marketing as well as function 
and price. It is not practical to determine the re- 
liability target based on the failure rate under single 
common test condition. So, the reliability target is 
determined based on many factors such as each 
characteristics of equipment, reliability target of 
system, derating applied in design, operating condi- 
tion and maintenance. 

2.2 Reliability Design 

Timely study and execution are essential to achieve 
the reliability based on reliability targets. The main 
items are the design standardization, device design 
including process and structural design, design 
review and reliability test. 
(1) Design Standardization 

Design standardization needs establishing design 
rules and standardizing parts, material, and 
process. When design rules are established on 
circuit, cell, and layout design, critical items 
about quality and reliability should be ex- 
amined. Therefore, in using standardized 



process or material, even newly developed prod- 
ucts would have high reliability, with the excep- 
tion of special requirement on function. 

(2) Device Design 

It is important for device design to consider 
total balance of process design, structure 
design, circuit and layout design. Especially in 
case of applying new process or new material, 
we study the technology prior to development 
of the device in detail. 

(3) Reliability Test by Test Site 

Test site is sometimes called Test Pattern. It is 
useful method for evaluating reliability of 
designing and processing ICs with complicated 
functions. 

1. Purposes of Test Site are as foilows; 

• Making clear about fundamental failure mode; 

• Analysis of relation between failure mode and 
manufacturing process condition. 

• Analysis of failure mechanism. 

• Establishment of QC point in manufacturing. 

2. Effects of evaluation by Test Site are as follows; 

• Common fundamental failure mode and 
failure mechanism in devices can be evaluated. 

• Factors dominating failure mode can be 
picked up, and compared with the process 
having been experienced in field. 

• Able to analyze relation between failure 
causes and manufacturing factors. 

• Easy to run tests. 

2.3 Design Review 

Design review is a method to confirm systematically 
whether or not design satisfies the performance 
required including by users, follows the specified 
ways, and whether or not the technical items 
accumulated in test data and application data are 
effectively applied. 

In addition, from the standpoint of competition 
with other products, the major purpose of design 
review is to insure quality and reliability of the 
product. In Hitachi, design review is performed 
in designing new products and also in changing 
products. 

The followings are the items to consider at design 
review. 

(1 ) Describe the products based on specified design 
documents. 

(2) Considering the documents from the standpoint 
of each participant, plan and execute the sub- 
program such as calculation, experiments and 



28 



Hitachi America, Ltd. • Hitachi Plaza 



# HITACHI 

■ 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 < 



) 589-8300 



investigation if unclear matter is found. 

(3) Determine the contents and methods of reliabil- 
ity test based on design document and drawing. 

(4) Check process ability of manufacturing line to 
achieve design goal. 

(5) Arrange the preparation for production. 

(6) Plan and execute the sub-programs of design 
changes proposed by individual specialists, for 
tests, experiments and calculation to confirm the 
design change. 

(7) Refer to the past failure experiences with 
similar devices, confirm the prevention against 
them, and plan and execute the test program 
for confirmation of them. 

In Hitachi, these study and decision at design review 
are made using the individual check lists according 
to its objects. 



Quality Assurance of IC Memory 

3. QUALITY ASSURANCE SYSTEM OF 
SEMICONDUCTOR DEVICES 

3.1 Activity of Quality Assurance 

The following items are the general views of overall 
quality assurance in Hitachi; 

(1) Problems is solved in each process so that even 
the potential failure factors will be removed at 
final stage of production. 

(2) Feedback of information is made to insure 
satisfied level of process ability. 

As the result, we assure the reliability. 



Step 


Contents 


Purpose 


Target 




Design Review 




Specification 







Design 

Trial 

i'rudufti 



Materials Paris 
Approval 



Characteristics Approval 



Quality Approval ( 1 ) 



Quality Approval (2) 



Mass 

Product ion 



Characteristics of Material and 
Parts 

Appearance 

Dimen.stun 

Heat Resistance 

Mechanical 

Eleclrtcal 

Others 



Reliability Test 
Life Test 
Thermal Stress 
Moisture Resistance 
Mechanical Stress 
Others 



Reliability Test 
Process Check same as 
Quality Approval ( 1) 



Figure 1 Flow Chart of Qualification 



Confirmation of 
Characteristics and 
Reliability of Materials 
and Parts 





Elect rical 
Cha racterisi ics 

Fund ion 

Voltage 

Current 

Temperature 

Others 
Appearance. Dimension 




Confirmation of Target 
Spec. Mainly about 
Electrical 
Characteristics 









Confirmation of Quality 
and Reliability in Design 



Confirmation of Quality 
and Reliability in Mass 
Production 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 29 



Quality Assurance of IC Memory 

3.2 Qualification 

To assure the quality and reliability, the qualifica- 
tion tests are done at each stage of trial production 
and mass production based on the reliability design 
described in section 2. 

The followings are the views on qualification in 
Hitachi* 

(1) From the standpoint of customers, qualify the 
products objectively by a third party. 

(2) Consider the failure experiences and data from 



customers. 

(3) Qualify every change in design and work. 

(4) Qualify intensively on parts and materials and 
process. 

(5) Considering the process ability and factor of 
manufacturing fluctuation, establish the control 
points in mass production. 

Considering the views mentioned above, qualifica- 
tion shown in Fig. 1 is done. 





Process 




1 




Material, Parts 


Material. 




Parts 









Quality Control 



Material and Par 



Products 







Manufacturing 






Sc reening 






100% Inspection 








Inspection on Materia! and 
Parts for Semiconductor 
Devices 



Manufacturing Equipment. 
Environment, Sub-material, 
Worker Control 



Inner Process 
Quality Control 



100% Inspection on 
Appearance and Electrical 
Characteristics 



Sampling Inspection on 
Appearance and Electrical 
Characteristics 



— 



Reliability Test 



Receiving J- 



X 



Shipment 
1 



Customer 



Quality Information, 
Cla im 

Field Experience 
General Quality 
In formation 



Lot Sampling, 
Confirmation of 
Quality Level 



Confirmation of 
Quality Level 



Lot Sampling, 
Confirmation of 
Quality Level 



Testing, 
Inspection 



Lot Sampling 



Confirmation of 
Quality Level, Lot 
Sampling 



- 



Feedback of 
Information 



Figure 2 Flow Chart of Quality Control in Manufacturing Process 



30 



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3.3 Quality and Reliability Control in Mass Produc- 
tion 

To assure quality in mass production, quality is 
controlled functionally by each department, mainly 
by manufacturing department and quality assurance 
department. The total function flow is shown in 
Fig. 2. 

3.3.1 Quality Control on Parts and Materials 

With the tendency toward higher performance and 
higher reliability of devices, quality control of parts 
and materials becomes more important. The items 
such as crystal, lead frame, fine wire for wire bond- 
ing, package and materials required in manufactur- 
ing process like mask pattern and chemicals, are all 
subject to inspection and control. 
Besides qualification of parts and materials stated in 
3.2, quality control of parts and materials is defined 
in incoming inspection. Incoming inspection is per- 
formed based on its purchase specification, drawing 
and mainly sampling test based on MIL-STD-105D. 
The other activities for quality assurance are as 
follows. 



• Table 1. Quality Control Check Points of Parts 
and Material (example) 



Material, 
Paris 


Important 
Control Items 


Point for Check 


Wafer 


Appearance 

Dimension 
Sheet Resistance 
Defect Density 
Crystal Axis 


Damage and Contamina- 
tion on Surface 
Flatness 
Resistance 
Defect Numbers 


Mask 


Appearance 
Dimension 
Resistoration 
Gradation 


Defect Numbers. Scratch 
Dimension Level 

Uniformity of Gradation 


Fine 
Wire for 
Wire 
Bonding 


Appearance 

Dimension 
Purity 

Elongation Ratio 


Contamination. Scratch, 
Bend, Twist 

Purity Level 
Mechanical Strength 


Frame 


Appearance 

Dimension 

Processing 

Accuracy 
Plating 
Mounting 

Characteristics 


Contamination. Scratch 
Dimension Level 

Bondahility, Solderability 
Heat Resistance 


Ceramic- 
Package 


Appearance 
Dimension 
Leak Resistance 
Plating 
Mounting 

Characteristics 
Electrical 

Characteristics 
Mechanical 

Strength 


Contamination, Scratch 
Dimension Level 
Airtightness 

Bondahility. Solderability 
Heat Resistance 

Mechanical Strength 


Plastic 


Composition 

Electrical 

Characteristics 
Thermal 

Characteristics 
Molding 

Performance 
M ounting 

Characteristics 


Characteristics of 
Plastic Material 

Molding Performance 
Mounting Characteristics 



Quality Assurance of IC Memory 

(1) Technology Meeting with Vendors 

(2) Approval and Guidance of Vendors 

(3) Analysis and tests of physical chemistry. 

The typical check points of parts and materials are 
shown in Table 1. 

3.3.2 Inner Process Quality Control 

To control inner process quality is very significant 
for quality assurance of devices. The quality 
control of products in every stage of production is 
explained below. Fig. 3 shows inner process quality 
control. 

(1) Quality Control of Products in Every Stage of 
Production 

Potential failure factors of devices should be re- 
moved in manufacturing process. Therefore, check 
points are set up in each process so as not to move 
the products with failure factors to the next 
process. Especially, for high reliability devices, 
manufacturing lines are rigidly selected in order to 
control the quality in process. Additionally we per- 
form rigid check per process or per lot, 100% 
inspection in proper processes so as to remove 
failure factors caused by manufacturing fluctuation, 
and screenings depending on high temperature aging 
or temperature cycling. Contents of controlling 
quality under processing are as follows: 

• Control of conditions of equipment and workers 
and sampling test of uncompleted produsts. 

• Proposal and execution of working improvement. 

• Education of workers 

• Maintenance and improvement of yield 

• Picking up of quality problems and execution of 
countermeasures toward them. 

• Communication of quality information. 

(2) Quality Control of Manufacturing Facilities and 
Measuring Equipment 

Manufacturing facilities have been developed with 
the need of higher devices in performance and the 
automated production. It is also important to de- 
termine quality and reliability. 
In Hitachi, automated manufacturing is promoted 
to avoid manufacturing fluctuation, and the opera- 
tion of high performance equipment is controlled to 
function properly. 

As for maintenance inspection for quality control, 
daily and periodically inspections are performed 
based on specification on every check point. 
As for adjustment and maintenance of measuring 
equipment, the past data and specifications are 
clearly checked to keep and improve quality. 



# HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 31 



Quality Assurance of IC Memory 



(3) Quality Control of Manufacturing Circumst- 
ances and Sub-material. 

Quality and reliability of devices are affected 
especially by manufacturing process. There- 
fore, we thoroughly control the manufacturing 
circumstances such as temperature, humidity, 
dust, and the sub-materials like gas or pure 
water used in manufacturing process. 



Dust control is essential to realize higher in- 
tegration and higher reliability of devices. To 
maintain and improve the clearness of manufac- 
turing site, we take care buildings, facilities, air- 
conditioning system, materials, clothes and 
works. Moreover, we periodically check on 
floating dust in the air, fallen dust or dirtiness 
on floor. 



Process 

V Purchase of Material 



Control Point 



Wafer- 



Package- 



> Surface Oxidation 

] Inspection on Surface 
Ox idation 
) Photo Resist 

) Inspection on Photo Resist 

OPQC Level Check 
)Diffusion 

3 Inspection on Diffusion 
OPQC Level Check 

> Evaporation 

) Inspection on Evaporation 

OPQC Level Check 
3 Wafer Inspection 

Inspection on Chip 
Electrical Characteristics 
Chip Scribe 
Inspection on Chip 
Appearance 

OPQC Lot Judgement 

6 Assembling 



OPQC Level Check 

Inspection after 
Assembling 

OPQC Lot Judgement 



y Sealing 

OPQC Level Check 
y Final Electrical Inspection 
OF.ilure Analysis 

Appearance Inspection 
Sampling Inspection on 
Products 
Receiving 

Shipment 



Wafer 
Oxidation 



Photo 
Resist 



Diffusion 



Evapo- 
ration 



Wafer 

Chip 



Assembling 



Sealing 
Marking 



Characteristics, Appearance 



Appearance, Thickness of 
Oxide Film 



Dimension, Appearance 

Diffusion Depth, Sheet 

Resistance 

Gate Width 

Characteristics of Oxide Film 
Breakdown Voltage 

Thickness of Vapor Film, 
Scratch, Contamination 



Thickness, Vth Characteris- 
tics 

Electrical Characteristics 
Appearance of Chip 



Appearance after Chip 
Bonding 

Appearance after Wire 
Bonding 

Pull Strength, Compresion 
Width, Shear Strength 
Appearance after Assembling 



Appearance after Sealing 
Outline, Dimension 
Marking Strength 

Analysis of Failures, Failure 
Mode, Mechanism 



Purpose of Control 



Scratch, Removal of Crystal 
Defect Wafer 
Assurance of Resistance 
Pinhole, Scratch 

Dimension Level 
Check of Photo Resist 
Diffusion Status 

Control of Basic Parameters 
(Vth, etc) Cleaness of surface 
Prior Check of Vih 
Breakdown Voltage Check 
Assurance of Standard 
Thickness 



Prevention of Crack, 
Quality Assurance of Scribe 



Quality Check of Chip 
Bonding 

Quality Check of Wire 
Bonding 

Prevention of Open and 
Short 



Guarantee of Appearance 
and Dimension 



Feedback of Analysis Infor- 
mation 



Figure 3 Example of Inner Process Quality Control 



HITACHI 

32 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Quality Assurance of IC Memory 



3.3.3 Final Tests and Reliability Assurance 

(1) Final Tests 

Lot inspection is done by quality assurance 
department for the product passed in 100% test 
in final manufacturing process. Though 100% 
of passed products is expected, sampling inspec- 
tion is subjected to prevent mixture of failed 
products by mistake. 



(2) 



The inspection is executed not only to confirm 
that the products meet users' requirement, but 
to consider potential factors. Our lot inspec- 
tion is based on MIL-STD-105D. 
Reliability Assurance Tests 
To assure reliability, the reliability tests are per- 
formed periodically, and performed on each 
manufacturing lot if user requires. 



r 





Customer 








Claim 

( Failures, In 


Sales Dept. 

Sales Engineering Dept. 








Quality Assurance Dept. 



Manufacturing Dept. 



Design Dept. 



1 



Report 



Quality Assurance Dept. 



Failure Analysis 



Countermeasure 
Execution of 
Countermeasure 



Report 



Follow-up and Confirmation 
of Countermeasure Execution 







Sales Engineering Dept. 



Reply 



Customer 



Figure 4 Process Flow Chart of Coping with Failure to a Customer 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 33 



■ OUTLINE OF TESTING METHOD 



1. INSPECTION METHOD 



2. MARCHING PATTERN 



Compared to conventional core memories, IC 
memories contain all peripheral circuits, such as the 
decoder circuit, write circuit and read circuit. As a 
result, assembly and electrical inspection of ICs are 
all performed by IC manufacturers. Consequently, 
as the electrical inspection of IC memories are 
becoming more systematic, conventional IC inspec- 
tion facilities are becoming useless. This has led to 
the development and introduction of a memory 
tester with pattern generator to generate the inspec- 
tion pattern of the memory IC at high speed. A 
function test for such as TTL gates can be per- 
formed even by a simple DC parameter facility. 
However, when the address input becomes multi- 
plexed as in 16K, 64K and 256K memory, even the 
generation of the function test pattern becomes a 
serious problem. 

In the memory IC inspection, its quality cannot be 
judged by DC test on external pins only, because the 
number of the element such as transistor which can 
be judged in the DC test is only 1/1000 of all ele- 
ments. The followings are the address patterns pro- 
posed to inspect whether the internal circuits are 
functioning correctly. 

(1) All "Low", All "High" 

(2) Checker Flag 

(3) Stripe Pattern 

(4) Marching Pattern 

(5) Galloping 

(6) Waling 

(7) Ping-Pong 

Those are not all, but only representative ones. 
There are the pattern to check the mutual inter- 
ference of bits and the pattern for the maximum 
power dissipation. Among the above mentioned 
patterns, those of (1) to (4) are called N pattern, 
which can check one sequence of N bit IC memory 
with the several times of N patterns at most. Those 
of (5) to (7) are called N 2 pattern, which need 
several times of N 2 patterns to check one sequence 
of N bit IC memory. Serious problem arises in using 
N 2 pattern in a large-capacity memory. For ex- 
ample, inspection of 16K memory with galloping 
pattern takes a lot of time - about 30 minutes. (1 ), 
(2) and (3) are rather simple and good methods, 
however, they are not perfect to find any failure in 
decoder circuits. Marching is the most simple and 
necessary pattern to check the function of IC 
memories. 



The marching pattern, as its name indicates, is a pat- 
tern in which "1"s march into all bits of "0"s. For 
example, a simple addressing of 16 bit memory is 
described below. 

(1) Clear all bits See Fig. 1 (a) 

(2) Read "0" from 0th address and check that the 
read data is "0". Hereafter, "Read" means 
"checking and judging data" 

(3) Write "1" on 0th address See Fig. 1(b) 

(4) Read "0" from 1st address. 

(5) Write "1" on 1st address. 

(6) Read "0" from nth address. 

(7) Write "1" on nth address See Fig. 1(c) 

(8) Repeat (6) to (7) to the last address. Finally, 
all data will be "1 ". 

(9) After all data become "1", repeat from (2) to 
(8) replacing "0" and "1". 

In this method, 5N address patterns are necessary 
for the N-bit memory. 




Figure 1 Addressing method of for 16 bit memory in the 
Marching pattern 



^HITACHI 

34 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



I APPLICATION 



1. Static RAM 

1.1. Static RAM Memory Cell 

The static RAM memory cell consists of flip-flops 
organized as 4 NMOS transistors and 2 load resistors 
as shown in figure 1-1. The data in the cell can be 
retained as long as power is supplied, and read out 
without being destroyed. 




Figure 1-1. 



RAM Memory Cell 



1.2. 



Data Retention Mode and Battery Back-up 
System 

The data in RAM is destroyed at power off. How- 
ever, CMOS static RAM has a data retention mode. 
In this mode, power consumption at standby is ex- 
tremely low and supply voltage can be reduced to 
2 V. So, it enables a battery back-up system to 
retain data during power failure. 
Data Retention Mode: The important point in 
designing a battery back-up system is the timing 
relation between the memory power supply during 
the change (ordinal source -» battery) and the chip 
select signal. If the timing for the change is missed, 
the data in memory might be destroyed. 
Figure 1-2. shows the timing for switching the 
power supply. The following explains the technical 
terms related to the data retention mode. 

Data retention mode 



ov 



CS(CE)£V„-0.2V- 



Figure 1 -2. Timing for Battery Back-up Application 

Data retention mode: The period that the power 
supply voltage is lower than the specified operation 
voltage. During this period, memory must be kept in 
non-select condition (e.g. CS = V DR - 0.2V). 



tcDR (time for chip select to data retention): The 
minimum time needed to change from operating 
mode to data retention mode. Normally ns. 
fft (Operation recovery time): The minimum time 
needed to change from data retention mode to 
operating mode. Normally, it is the same as the 
cycle time of the memory. 

V DR (data retention voltage): The voltage applied in 
data retention mode. Normally, the minimum 
supply voltage needed to retain memory data is 2 V. 
'CCD/? (data retention current): The current con- 
sumption in data retention mode. It depends on 
memory power supply voltage and ambient tem- 
perature. It is specified at supply voltage (V DR ) = 
3.0 V. 

Battery Back-up System: battery back-up sequence 
is described in the following: 

1. External circuit detects failure of system power 
supply. 

2. External circuit changes RAM to standby mode. 

3. External circuit separates RAM from system 
power supply. 

4. External circuit switches to Back-up power 
supply. 



Memory 
control pin 



Figure 1 -3. Example of Battery Back-up System 

The control circuit detects the power failure and 
cuts off the power after switching memories to 
standby mode. On recovery, it confirms power 
supply and after some delay, returns memories to 
operating mode. The memory control signals 
depend on the types of memories used in the 
system. 

* Using memory with only one CS. NAND signal 
between the control signal and chip select signal 
should be connected to CS. As the level of CS in 
data retention mode must be higher than Vpp — 
0.2V, the power supply for this NAND gate must 
either be shared with the memory power supply, 
or be pulled up to the memory power supply. 

* Using memory with two CS. Basically, the 
signals are the same as mentioned above. In 
general use, two pins should be used for the 
control signal and the chip select signal respec- 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 35 



Application 



tively. CS, which can intercept current path of 
other pins in the input buffers, is for control 
signal input of data retention mode. 
Using memory with CS and CS. As CS selects 
the chips at high level, it is better to use CS than 
CS as control signal input for data retention 
mode. As soon as power down is detected, 
signals should be brought to low level. So a pull- 



up to the memory power supply level is not 
needed and circuit organization is simplified. 
Figure 1-4 shows an example of a battery back-up 
system circuit. Hitachi recommends using CMOS 
logic for gate G] in control circuit and memory 
Vcc- The low Vce transistor Q t is required to 
switch regulating circuit from system power supply 
to back-up power supply. 




Fhjui» 1-4. Example of Battery Back-up System Circuit 



HITACHI 

36 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



2. Pseudo-Static RAM 

2.1 Pseudo-Static RAM Features 

A new type of memory, pseudo-static RAM has 
been developed providing the advantages of 
dynamic RAM (low cost, high density), and static 
RAM (easy usage). IC memory consists of memory 
cells for data storage, and input/output circuits for 
interfacing to the external circuits. PSRAM pro- 
vides the memory cell and peripheral circuits of 
DRAM and the external control circuits, which 
includes a part of the refresh control circuits not 
provided by dynamic RAM, and interface circuits 
similar to that of static RAM, on a chip, as shown in 
table 2-1. Address input is not multiplexed and 
data input/output is byte-wide like standard static 
RAM. With PSRAM x 8 organization, medium 
density memory system can be designed easily. 
PSRAM provides address refresh, automatic refresh 
and self refresh. 

Figure 2-1 shows examples of system design using 
PSRAM and DRAM. Using PSRAM, the circuits 

T. bl .2-1. PSRAM I 



I Features 





SRAM 


PSRAM | DRAM 


Memory Cell 


4 Tr + 2 R 


1 Tr + 1 C 


Organization 


xl, x4, x8 


x8 


xl, x4 


Address 


Single Address 


Multiplexed 
Address 


Refresh 


Nor 

Necessary 


Necessary 


External Circuits 


Simple< £• Complexed 



Address 
Selector 





Data 













— , ) 




Status 






Timer & 




Busy 


Control 





Figure 2-1. System Organization 



Refresh 
Address 
Counter 



CE — 
OE — 
WE — 



Control 
Logic 



Memory Array 
(lTr+lC/Cdl) 



Refresh 
Timer 



<Z>D,t« 



Column Decoder 



J 



Column Address 



Figure 2-2. Block Diagram (PSRAM) 



interfacing CPU to DRAM can be drastically 
reduced. 

Figure 2-2 shows block diagram of pseudo static 
RAM. 



2.2. 1 Mbit Pseudo-Static RAM Function 
Read/Write Cycle: Figure 2-3 and figure 2-4 show 
the timing chart for the read/write cycle of 1 Mbit 
pseudo-static RAM HM658128. The HM658128 



can perform 2 types of access in a read cycle, CE 
access (Figure 2-3 (a)) and OE access figure 2-3 (b)). 
It writes the data at the rising edge of WE (figure 
2-4 (a)) or at the rising edge of CE (figure 2-4 (b)). 
The C~S~ pin should be brought high when the ad- 
dress is latched at the falling edge of C"E in the read/ 
write cycle. The HM658128 has no UE" specifica- 
tion at the falling edge of CE as it provides both 0~E 
pin and RFSH pin. 



CE I 

«™ XXBC 
« TYV\ 


r 


"xmmxxx 






WE jJJJ 




* 111] ' 


1 wwwww 


(.) CE nm 

Figure 2-3. 



JET 



r 



i WWWW 



- 3 D °- > - 



(b) OE « 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



37 



Application - 



CS Standby Mode: The HM658128 enters CS 
standby mode for one_ cycle if CS turns to low 
at the falling edge of CE (figure 2-5). 




- 














ILL/ 




r 




\ 






ILL/ ' 


} WWW 


\\\ 


( Din 





CE 



r 



minimi 



Figure 2-5. CS Standby Mode 



(.] Wrile M the rising edge of WE (b) Wrile .1 the rising edge of CE 

Figure 2-4. Write Cycle 

Address Refresh: Address refresh mode performs distributed mode). In this mode, CS should be high 

refresh by access to row address (AO - A8) 0-511 at falling edge of CE. 
sequentially within 8 ms, as shown in figure 2-6 (in 



A9-AI6 

cs- 





n b r 


k n , p 


n , n 
























X 


^- )( S x 


* X ( X 


isr X f X 


Don 1 ! 
c«re 






9 K « 








i 1 — t 

. Refresh . . R/W , 




I tf < 





Figure 2-6. Address Refresh 

Automatic Refresh: The HM658128 goes to auto- address pins AO - A8, as it is generated internally, 
matic refresh mode if RFSH falls while CE is high Figure 2-7 shows the timing chart for distributed 
and it is kept low for more than 180 ns. refresh. In automatic refresh mode, the timing for 

It is not required to input the refresh address from only CE and RFSH are specified. 



J 



M 



180nsSRefresh<8//s 

Figure 2-7. Automatic Refresh 



Self Refresh: Self refresh mode performs refresh at enabled by keeping CE high and RFSH low for 
the internally determined interval. The HM658128 more than 8 jits (figure 2-8). 
enters the mode when the internal refresh timer is 

HITACHI 

38 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Application 



r 



2 Bus 

Figure 2-8. Stlf Refresh 

Considerations on Using HM658128: The following 
should be considered when using the HM658128. 

• Data retention. The HM658128 can retain the 
data with a battery (but not for long time). The 
HM658128L, low power version, offers typical 
self-refresh or standby current of 100/iA. 

A 1-Mbyte system (using eight HM658128Ls) 
can retain the data for about 1.5 months with 
battery of 100 mAh current. V cc = 5 V + 10% 
must be maintained for data retention. 

• Power on. Start HM658128 operation by 
executing more than eight initial cycles (dummy 
cycles) more than 100 us after power voltage 
reaches 4.5 V — 5.5 V after power on. 

• Bypass capacitor. Hitachi recommends inserting 
1 bypass capacitor per RAM. 

2.3 Pseudo-Static RAM Data Retention 
PSRAM with self refresh retains data CE and OE 
are fixed for more than defined period. The follow- 
ing explains considerations for PSRAM data reten- 
tion. 

First, PSRAM cannot retain the data at low supply 
voltage. 

They employ 1 MOS type memory cell as shown in 
figure 2-9. The charge is stored on the capacitor C 
as memory data. The data 1, written at low supply 



Second self refresh current increases at low supply 
voltage. 




Figure 2-9. Memory Call of PSRAM 

voltage, cannot be read as 1 at high supply voltage. 
Figure 2-10 indicates the operation voltage for self 
refresh and subsequent read of PSRAM. If the data 
is read out at more than 5 V of V C q, for example, 
after self refresh is performed at V cc = 3.7 V, it is 
destroyed. 

PSRAM must be used at supply voltage from 4.5V 
to 5.5V. 




Self Refresh Voluge 

Figure 2-10. PSRAM Operating Voltage 

PSRAM provides the voltage level detector circuit 
to reduce self refresh current. However, it should 
be noted that the circuit increases the current with 
low supply voltage in self refresh (figure 2-11). Self 
refresh current also increases at low temperature 
(figure 2-12). 









Spec 




| 4.5V 5.5V ^ 







Power Supply Voltage 

Figure 2-1 1 . Self Refresh Current vs. Voltage 



Spec 




Figure 2-12. Self-Refresh Current vs 



Please use PSRAM within the recommended opera- 
tion range ( Vqc more than 4.5 V, temperature more 
than 0°C) for data retention, especially using a 
battery. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, 



CA 94005-1819 



(415) 



589-8300 39 



3. Video RAM 

3.1. Multiport Video RAM 

Figure 3-1 shows general idea of video RAM. Multi- 
port video RAM provides an internal data register 
(SAM) with the memory (RAM). Both of them 
can be accessed asynchronously. Effective graphic 



display memory is realized by using the random 
port of the RAM part for graphic processor drawing 
and the serial port of the SAM part for CRT display. 



Dr.«ing 










I 




3 


a 



Graphic 

Processor 



Mm 

Figure 3 1. General Idea of Mufti port Video RAM 



— - <^crtJ 



Figure 3-2 shows the block diagram of the 256- shows the operation modes of the Hl\,,„w-,w ,. 
kbit multiport video RAM HM53461, and table 3-1 



DT/OE 




The operation modes shown in table 3-1 are described as follows. 

Table 3-1 . Operation Modes of HM53461 



At the falling edge of RAS 


RAM modes 


SAM modes 


CAS 


DT/OE 


We 


SOE 


SI/O direction 


Notes 


H 


H 


h 


X 


Read/write 


Sin/Sout 


1,2,3 


H 


H 


L 


X 


Temporary write mask data program 


Sin/Sout 


1,2,3 


H 


L 


H 


X 


Read transfer 


Sout 


2 


H 


L 


L 


L 


Write transfer 


Sin 




H 


L 


L 


H 


Pseudo transfer 


Sin 




L 


X 


X 


X 


CBR refresh 


Sin/Sout 


1,2 



H: High 
L: Low 
X: Don't Care 

Notes: i. Transfer cycle executed previously d efine s SI/O direction. 

2. SI/O is in high impedance state with SOE high, even if the direction is Sout. 

3. The H M5346 1 starts write operatio n if W E is low at the falling edge of CAS or become low between the falling 
edge of CAS and the rising edge of RAS. 



40 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Application 



Read/Write Operation: Read/write is performed 
on the random port in the same sequence as for a 
dynamic RAM (figure 3-3). The HM53461 starts 
the read operation with WE high and the write 
operation at the falling edge of WE. 



L 



5 




1 


c 


1 


I 


a 


1 


a 





A 



1/01 -1/04 

Figure 3-3. Read/Write Operation 



Temporary Write Mask Set and Temporary Masked 
Write Operation: The HM53461 provides tem- 
porary masked write operation which inhibits to 
write data bit-by-bit (write mask) during one RAS 
cycle. Temporary write mask set function defines 
the bits to be inhibited (figure 3-4). This operation 
puts the data on 1/01 — I/04 into the internal tem- 
porary write mask register. When is programmed 
to the register, writing to the corresponding bit is 
inhibited. 

The temporary write mask register is reset at the 



rising edge of RAS. 












1 


ector 




E 




a 






Q 











1/01-1/04 

Figure 3-4. Temporary Masked Write Operation 



Read Transfer Operation: In this cycle, the 
HM53461 transfers the data of one row in RAM 
(1024 bits), which address is specified at the falling 
edge of RAS, to SAM (figure 3-5). The start address 
in SAM can be programmed at the falling edge of 
CAS in this cycle. After data transfer, the serial 
port turns to serial read mode at the rising edge of 
DT/OE. 



Ink 



1l 







DRAM 




memory 




cell 













1 




i 









SI701- SI/04 



Figure 3-5. Read Transfer Operation 

Write Transfer Operation: In this cycle, the 
HM 53461 transfers the data in the SAM data re- 
gister (1024 bits) to one row in RAM, which address 
is specified at the falling edge of RAS (figure 3-6). 
The start address in SAM can be programmed in this 
cycle. After data transfer, serial port turns to serial 
write mode. 



L 



11 



DRAM 




memory 




cell 





1 



3 C=l SI/01 -SI/04 



Figure 3-6. Write Transfer Operation 

Pseudo Transfer Operation: This operation switches 
the serial port to serial write mode (figure 3-7). It 
does not perform data transfer between RAM and 
SAM. SAM start address can be programmed in this 
cycle. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 41 



Application 



H 



/ decoder \ 



I 



^ZD SI/Ol-SI/04 



Figure 3-7. Pseudo 



CAS-Before-RAS Refresh Operation: The HM53461 
performs refresh by using the internal address 
counter in this operation (figure 3-8). 





Row 




Refresh address 




latch 









DRAM 




memory 




cell 











i 









Serial Read/Write Operation: The HM53461 reads/ 
writes the contents of the SAM data register in serial 
at the rising edge of SC (serial clock input) (figure 
3-9). The address for serial access is generated by 
the internal address pointer, independently of 
random port operation. It should be considered 
that serial access is restricted in transfer cycles. The 
SAM, employing static-type data registers, requires 
no refresh. 



!§r] [tej 



/ Row \ 
/ decoder \ 







i 
a 

t 

3 


Selector 


a 





1 {^si/oi-si/cm 



Figure 3-9. Serial Read/Write Operation 

The HM53462 is a multiport video RAM, adding 
logic operation capability to the advantages of 
HM53461. 

Figure 3-10 shows the block diagram. Table 3-2 
describes the operation modes. 



Figure 3-8. CAS-Before-RAS Refresh 



r 

i 



Logic 
unit 



Write 
mask 
register 



Temporary 
write mask 
register 



DT/OE 



j, DRAM /■ 

' memory 



V 



Data 
register 



SC SOE 



Serial 
port 



Figure 3-10. Block Diagram of HM53462 



42 



Hitachi America, Ltd. 



HITACHI 

■ Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Application 



Table 3-2. Operation Modes of HM53462 



At the falling edge of RAS 


RAM modes 


SAM modes 


CAS 


DT/OE 


WE 


SOE 


SI/O direction 


Notes 


H 


H 


H 


X 


Read/write 


Sin/Sout 


1, 2, 3 


H 


H 


L 


X 


Temporary masked write 


Sin/Sout 


1, 2, 3 


H 


L 


H 


X 


Read transfer 


Sout 


2 


H 


L 


L 


L 


Write transfer 


Sin 




H 


L 


L 


H 


Pseudo transfer 


Sin 




L 


X 


X 


X 


CAS-before-RAS refresh 


Sin/Sout 


1,2 


L 


X 


L 


X 


Logic operation program 
(CBR Refresh) 


Sin/Sout 


1,2 



H: High L: Low X: Don t Care 

Notes: 1. Transfer cycle previously execu ted d efines SI/O direction. 

2. SI/O is in high impedance with SOE high, even if Sl/O d irection is Sout. 

3. HMS 3462 writes if WE is low at the falling edge of CAS or becomes low between the falling edge of CAS and the 
rising edge of RAS. 



Logic Operation Programming: This function 
programs a logic operation (figure 3-11). The logic 
operation is available until re-programmed or reset. 
In logic operation mode, HM53462 performs read- 
modify-write internally when data is written into 
random port. The result of the logic operation 
between memory data and written data is put into 
the address from which the memory data is trans- 
ferred. 

In the logic operation programming cycle, the mask 
register, which differs from the temporary mask re- 
gister, is also programmed. It is available until re- 



programmed. 




e write in logic operation mode) 

Figure 3-11. Logic Operation Programming 



Notes: Notes on using HM53461/HM53462 are as 
follows. 

• Dummy RAS cycle. Devices should be initialized 
by 8 dummy RAS cycles (minimum) before 
access to random port. Refresh cycle can be in- 
serted for initialization. It is reco mmend ed that 
the system be initialized by dummy RAS cycle in 
the automatic reset time of the processor. 

• Bypass capacitor. One bypass capacitor should 
be inserted between Vqq and V$s to each device. 
The Vqc Pin should be connected to the capaci- 
tor by the shortest path. A capacitor of several 
f/F is suitable. 

• Negative voltage input. Negative polarity input 
level to input pin or I/O pin should be under -1 
V. In this range, it has no effect on device 
characteristics or RAM/SAM data retention. 

• Initialization of logic operation mode 
(HM53462). The logic operation programming 
cycle should be executed before access to the 
random port to initialize logic operation mode 
after power on. At this time, the operation 
codes (0101) and all 1 write mask data are re- 
commended. 

3.2. Line Memory 

Hitachi has produced a line memory for line buffers 
with simple circuits, providing specific functions as 
described below. 

The line buffer can improve picture quality by 
storing 1 horizontal line data. It has following 
features. 

• Capacity to store 1 horizontal line data 

• High-speed operation matching the sampling 
speed of PAL TV signal (4 fsc/8 fsc) or NTSC TV 
signal (4 fsc/8 fsc). 



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Application 



• Separate data inputs/outputs and capability of 

serial data inputs and outputs. 
The conventional line buffer composed of high 
speed static RAMs requires separate input/output 
for double buffer organization. It also requires 
interleaving for high speed operation, matching 
4 fsc/8 fsc, where fsc is the subcarrier frequency. In 
addition, external circuits are needed for serial 
address scan. 

The line memory provides all of these functions. 
Figure 3-12 shows the standard organization of a 
conventional memory buffer and figure 3-13 
shows the block diagram of line memory. 



A 



Input 



r 

o 

L 



SRAM 



Output 



Address 
Control 



Figure 3-12. Standard Organization of Conventional 



Read 

Address 

Counter 



Input Output 
Buffer 1H Memory t Buffer 



Write. 
Clock 



Read 
Clock 



Output 



Write 
Address 



Figure 3-13. Block Diagram of Line Memory 



The Hitachi HM63021 is a 2048-word x 8-bit line 
memory storing 2 horizontal lines of data. 
It has five different modes for various video graphic 
system applications. It realizes high speed opera- 
tions for PAL and NTSC TV signals, and dissipates 
little power employing 1.3 fim CMOS technology 
and static-type memory cells. 

The features of the HM63021 are described as 
follows: 

• Five modes for various video graphic system 
applications 

- Delay line mode 

- Alternate 1H/2H delay mode 

- TBC (Time-Base Corrector) mode 

- Double speed conversion mode 

- Time-base compression/expansion mode 

• High speed cycle time 

- HM63021-34: 34 ns min (corresponds to 8 fsc 
of NTSC TV signal) 

- HM63021-28: 28 ns min (corresponds to 8 fsc 
of PAL TV signal). 

Line memory in the system using digital signal 
processing technologies offers following applica- 
tions: 

1. comb filter 

2. double-speed conversion (non-interlace) 

3. compression/expansion of graphics (picture- 
in-picture) 

4. dropout canceller 

5. time-base corrector 

6. noise reducer 



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4. Dynamic RAM 

4. 1 . Dynamic RAM Memory Cell 

The dynamic RAM memory cell consists of 1 MOS 
transistor and 1 capacitor, as shown in figure 4-1. It 
detects the data in the cell (1 or 0) by the charge 
stored in capacitor. Dynamic RAM offers higher 
density than that of static RAM because of fewer 
components per chip. 

However, Dynamic RAM must rewrite data, called 
refresh, in a defined cycle because the charge stored 
in the capacitor leaks. 




I 



Figure 4-1 . Memory Cell of Dynamic RAM 
4.2. Power On Procedure 

After turning on power, to set the internal memory 
circuitry, hold for more than 100 jus, then apply 
eight or more dummy cycles before operation. The 
dummy cycle may be either a normal read/write 
cycle or a refresh cycle. When using an internal re- 
fresh counter, eight or more CAS before RAS 
refresh cycles are required as dummy cycles. 



4.3 Address Multiplexing 

Dynamic RAMs are used to increase capacity be- 
cause of their smaller cell area. In using dynamic 
RAMs in systems, however, it is desirable to increase 
the memory density by using smaller packages. To 
reduce the number of pins and the package size, 
address multiplexing is used. 

Using a 1 -Mbit dynamic RAM, 20-address signals are 
necessary to select one of 1,048,576 memory cells. 
Address multiplexing allows address signals to be 
applied to each address pin. Thus only 10-address 
input pins are required to select one of 1048,576 
addresses. Multiplexed address inputs are latched 
as follows: RAS (Row Address Strobe) selects one 
of word lines according to the row address signal, 
and one of column decoders is selected by CAS 
(column address strobe) following column address 
signal. Although two extra signals, RAS and CAS, 
are required, the number of address pins is reduced 
to half. Figure 4-2 shows the pin arrangement, 
address latch waveform, and the block diagram of 
address-multiplexed 1-Mbit dynamic RAM. Systems 
need an address multiplexer in order to latch the 
multiplexed address signals into the device. 



AO - A9 


Address Inputs 


CAS 


Column Address Strobe 


Din 


Data In 


Dout 


Data Out 


RAS 


Row Address Strobe 


WE 


Read /Write Input 


vcc 


Power (+SV) 


vss 


Ground 


AO - A8 


Refresh Address Inputs 





Memory Cycle 




(b) Adart.sL.lch 



Eternal peripheral 



if 



Internal memory LSI 

RAS Row 
^ Address 



Letch 

Circuit 



| L-M Lstch 

1 — V Circuit 



CAS 



l=i 





Word Line 








Mat 




3 


J- 


P 





(c) Block diww. of Address Multiplexing 

Figure 4-2 Address Multiplexing of Dynamic RAMs 



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Application - 



4.4. Dynamic RAM Function 

Figure 4-3 shows the normal function of Dynamic 
RAM. 




High Z 



High 



(a) Read Cycle 




tRC'. Random Read or Write Cycle Time 

t R co- RAS to CAS Dela y Tim e 

'RAC- Access Time from RAS 

f CAC '■ Access Time from CAS 

R : Row Address 

C: Column Address 



WE 



wmmmnMMniL 
wrnn — 1 z 7777777 " 




High z 

(Early Write) 



(Delayed Write) 



(b) Write Cycle 



RAS 
CAS 
Address 
WE 

Dm 



7=1 



mm, 



'RWC Read-Write Cycle Time 



MZMZMDCJZZMm 



High Z 



3- 



(c) Read-Modify-Write Cycle 

Figure 4-3 Normal Function of Dynamic RAM 



Read Cycle: In the read cycle, a row address is 
latched at the falling edge of RAS, and a column 
address is latched at the falling edge of CAS after 
the RAS falling edge. If WET is high, the data is 
read out from Dout with the access time of tQAC 
(Access time from CAS) or tpAC (Access time 
from RAS). 

Tr >e tRCD maximum (RAS to CAS delay time) is 
specified only to guarantee the specified minimum 
value s of other timings such as the cycle time, 
RAS/CAS pulse width. Therefore, when using these 



timings with more than the specified minimum 
value, there is no need to limit the tffCD to the 
specified maximum value. 
Write Cycle: Dynamic RAM provides two write 
cycle modes: early write cycle and delayed write 
cycle. In the early write cycle, when WE is low, 
data is written into Din at the falling edge of CAS. 
In delayed write cycle, when WE is high, data is 
written into Din at the falling edge of WE after CAS 
falling. 

Read-Modify-Write Cycle: The read-modify-write 



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Application 



cycle is initiated by taking WE high. Data is read 
out from Dout at the falling edge of CAS with WE 
high. Then, when WE goes low, data is written into 
the same address from Din in the same cycle. 
The cycle time in the read-modify-write mode 
{tftwc) is longer than the cycle time in read/write 
mode (fffc)- 

4.5 High Speed Access Mode 

Dynamic RAM access time is typically longer than 
that of static RAMs. To realize higher speed opera- 
tion, they have high speed access modes. 
The read operation in dynamic RAM is performed 
as follows: 



When a word line is selected by row address, all data 
in the memory cells connected to the selected word 
line is transferred to sense amplifiers. One of these 
sense amplifiers is selected by the column address, 
and its contents are output. 

The output of data from other sense amplifiers is 

controlled only by the column address. 

Access controlled only by column address with the 

row address fixed is called high speed access mode. 

Table 4-1 compares each mode. 

Page Mode: This is the most typical access mode in 

dynamic RAM. The column address is switched 

synchronized with CAS falling. 

Nibble Mode: In a nibble mode dynamic RAM, 



Table 4-1 . Comparison of Dynamic RAM High Spaed Access Modes 



Normal 
Mode 




Ft : Row Address 
C : Column Address 



Page 
Mode 




Nibble 
Mode 




Static Column 

MOdc 





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data from 4 sequential addresses is stored in the 
4-bit output latch circuits. Output is provided by 
the CAS signal, which controls the latch circuits. 
When 4 addresses are accessed sequentially, the row 
addresses on and after second bit need not be 
selected. Therefore, it facilitates the timing design. 
In nibble mode, the operation is limited to 4 ad- 
dresses, however, it enables faster access (t/v^c) 
than that in page mode. 

Static Column Mode: In static column mode, the 
column address is switched without the synchro- 
nized signal by high-speed static RAM technology 
in the peripheral circuits. 

High Speed Page Mode: This mode is the advanced 
mode of static column mode, with CAS providing 
the address latch function. 



4.6 Refresh 

Refresh operation is performed by accessing every 
word line within the specified time (refresh cycle). 
Table 4-2 compares the following refresh modes in 
dynamic RAM. 

RAS Only Refresh: In RAS only refresh mode, 
refresh can be completed by selecting only row 
addresses synchronized with RAS. 
CAS Before RAS Refresh: This mode refreshes by 
the CAS falling edge before RAS in the period de- 
fined by the internal refresh address generator. This 
mode simplifies the external address multiplexer. 
Hidden Refresh: In hidden refresh, CAS before 
RAS refresh is performed while output data is valid. 




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Application 



5. EEPROM 

5.1. EEPROM Memory Cell 

EEPROM is electrically erasable and programmable 
ROM, which can be erased or written remotely 
while the system is in operation. 
The Hitachi EEPROM memory cell is MNOS (Metal 
Nitride Oxide Semiconductor) type, as shown in 
figure 5-1. 

An MNOS memory cell consists of two layers of 
oxide film and nitride film. The thickness of oxide 
film is about 20 A and that of nitride film is 300 to 
500 A. There are traps in the boundary of the 
oxide and nitride films to catch electrons. Electrons 
move by the tunneling phenomenon between the 
substrate and traps. 



*zzzzy 



Figure 5-1 . MNOS Type Memory Transistor 

5.2. 64-kbit CMOS EEPROM Function 
Page Write Function: The 64-kbit HN58C65 can 
latch 32 bytes (max) and write them in one write 
cycle. Writer cycle time is specified as 10 ms (max.). 
The effective byte write speed of HN58C65 in page 
write mode is: 

10 ms/32 bytes = 0.31 ms/byte 
Thus it takes only 2.56 seconds to write the whole 
HN58C65. Figure 5.2 shows internal operation. 
The following describes operation sequence: 

1. 32-byte memory cell data at the row address 
selected by address pins A5 - A12 is latched. 

2. Latched data at the column address specified by 
address pins AO - A4 is altered with write data, 
which is put into Din buffer from I/O pins I/O0 
- 1/07. 

The 32 bytes (max) of latched data are altered 
by repeating this operation 32 times. 

3. 32-bytes memory cell data in the selected row 
(1) are erased (All 1). 

4. Latched data is written into the selected row (3). 

5. CPU acknowledges the completion of write cycle 
by the internal timer. The HN58C65 provides 

Data polling to indicate the 



RDY/BUSY and 
write completion. 



MNOS memory cell 



RDY/ 



/BUSY * 



a 




Column Decoder 



IF 



7 



Figure 5-2. 



A0-A4 

HN58C65 Page Write 



Internal Timer: The HN58C65 indicates the 
completion of data write to the CPU by using the 
internal timer. The HN58C65 enters next cycle as 
soon as detecting the completion of write. This 
function offers high system throughput as the CPU 
can access other devices during write cycle. The 
HN58C65 has two functions, RDY/Busy and Data 
polling, to indicate the completion of data write. 
The RDY/Busy approach indicates the completion 
of data write by using pin 1. It is low when the 
HN58C65 is in data write operation (Busy) and 
turns to high impedance state at the end of data 
write (RDY). RDY/Busy pin should be pulled up as 
it uses open drain output. The RDY/Busy pins can 
be wired-OR when using several HN58C65s. 
The Data polling approach, implemented by soft- 
ware, indicates the completion of data write 
through pin 19 (1/07). While the data write is not 
completed, 1/07 shows the inverted data of what 
was written in the last cycle. In using this approach, 
RDY/Busy pin should be opened or grounded. 
The Data polling approach can acknowledge the 
completion of data write in an individual HN58C65, 
even if several HN58C65s are used in the system. 
Data Protection: EEPROM performs data write 
with a higher voltage (V PP ) than power supply 
voltage (V cc ). The HN58C65 internally generates 
Vp P by a high voltage generator with the combina- 
tion of control pins (CE, OE, WE). It supports the 
following functions to avoid accidental data write 
(data protection). 

1 . Data protection against the noise on the control 
pins (CE, OE, WE) during operation. 

2. Data protection against the noise at power-on/ 
power-off. 



Hitachi America, Ltd. • Hitachi Plaza 



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Application 



6. EPROM/OTPROM 

6.1. EPROM Programming 

Figure 6-1 shows the sectional structure of an 
EPROM memory cell. The upper gate, one of the 
gates made of two-layered polycrystalline silicon, is 
called the control gate and is connected to a word 
line. The lower layer is called the floating gate and 
is not connected. This memory cell is programmed 
as follows: With substrate and source grounded, 
apply high voltage between drain and control gate. 
Then, an electric potential incline occurs between 
source and drain so that intensity of the electric 
field becomes high near the drain. Because of this 
electric field, electrons are accelerated and so-called 
hot electrons are generated, which jump over the 
energy barrier of Si0 2 film. Hot electrons are 
pulled by the electric potential of the control gate 
and pour into the floating gate. Electrons stored in 
the floating gate remain stable, as they fall into a 
well surrounded by an energy barrier of SiOj film. 
Therefore, it is evident that the quality of SiOj film 
surrounding the floating gate is essential for good 
data retention characteristics. To keep data reten- 
tion in the 5- or 10-year range, high quality Si0 2 
film is needed. 

Figure 6-2. shows the fundamental characteristics of 
the EPROM transistor. While l D in a non-pro- 
grammed transistor begins to flow with V G of about 
1V, the current in a programmed transistor does not 
flow until V G rises to 7 V — 10 V. Therefore, if the 
voltage of word line applied to the control gate is 
about 5 V in readout, the non-programmed memory 
transistor will be on, and the programmed one will 
be off. This means that the data can be read out by 
means of the same structure as NOR-type mask 
ROM. 

6.2. Erasing EPROM 

When shipped, all bits of the EPROM are at logic 1 
with all electrons in the floating gate released 
(erase). Changing the logic 1 to logic through the 
application of the specified waveform and voltage, 
programs the necessary information. The higher the 
Vpp voltage and the longer the program pulse width 
t pw , the more electrons can be programmed in, as 
shown in Figure 6-3. If V PP exceeds the rated 
value, such as by overshoot, the p-n junction of the 
memory may yield to permanent breakdown. To 
avoid this, check V PP overshoot of the PROM 
programmer. Also, check negative-voltage-induced 
noise at other terminals, which can create a parasitic 
transistor effect and reduce the yield voltage. 



Hitachi's EPROMs can usually be written and erased 
more than 100 times. 



/Control Gate 
N' J [ N' / 



Figure 6-1. Cross Section of EPROM Memory Call 




■c 



Figure 6-2. Fundamental Characteristic of EPROM 
Memory Call 




0.1 0.2 0.5 1 2 5 
Program Pulse Width l n ms 

Figure 6-3. Standard Programming Characteristic* 
of EPROMs 

EPROMs are erased by ultraviolet light exposure 
through a transparent window on the package. 
Electrons in the floating gate get energy from 
photons and become hot electrons again with 
enough energy to go over the energy barrier of Si0 2 



50 



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film. The hot electrons go through to the control 
gate or the substrate and erasure is completed. 
Therefore, light with enough energy to get the 
electrons over the energy barrier of Si0 2 film is 
needed for erasure. Light energy is proportional to 
its frequency, and described as E = hv. E means the 
energy of light, h is Planck's constant, v is light 
frequency. Erasure isn't caused by light over certain 
wavelengths, and under certain wavelengths, erasure 
does occur. However, erasure time depends upon 
the quantity of photons, therefore erasure time 
cannot be shortened by shorter wavelength. Figure 
6-4 shows the relation between wavelength and 
erasure effectiveness. Erasure starts at about 4000 
A, and is saturated at about 3000A. 




Figure 6-4. Erasure Efficiency of EPROM 

For erasure, the wavelength and minimum irradia- 
tion rate of ultraviolet light must be 2,537 A and 15 
W-s/cm 2 respectively. These conditions can be met 
by placing the device 2 - 3 cm below a 12,000 
W/cm 2 UV lamp for about 20 minutes. 
The UV transmittance of the transparent lid 
materials is about 70%. However, it is influenced by 
contamination or foreign materials on the lid 
surface. Contamination or foreign materials should 




W • Irradiation (W • sec/cm 1 ) 

Figure 6-5. Standard Erasure Characteristics 



be removed with a solvent such as alcohol that does 
not damage the package. 

Figure 6-5 shows EPROM standard erasure charac- 
teristics. 

6.3. EPROM Data Retention Characteristic 

About 2 to 20 x 10" 14 coulomb of electrons are 
accumulated in the floating gate when programmed. 
However, these electrons dissipate with time. Then 
the data may be inverted. The mechanism of 
electron dissipation is generally explained as fol- 
lows. 

Data Dissipation by Heat: The electrons at the 
floating gate are in a non-equilibrium state, so the 
dissipation of electrons by thermal energy is un- 
avoidable. Therefore, the data retention time 
depends on temperature. Figure 6-6 shows typical 
data retention characteristics. The data retention 
time is proportional to the reciprocal of absolute 
temperature. 



10 : 
I 10' 

10' 





7 






-r 
i - 




— ft 







300 200 150 100 
Stored temperature I 'C 



Figure 6-6. EPROM's Data Rentention Characteristic 

Data Dissipation by Ultraviolet Light: Ultraviolet 
rays at a wavelength of not greater than 3,000 - 
4000A is capable of releasing the electric charge at 



40W fluorescent 
lamp 30cm away 



Llirect sunlight 



Ultraviolet eraser 
at 2537A. 6mVY/cr 




0.3 0.4 0.5 0.6 0.7 0.8 0.9 
Writing Charge I relative I 

Figure 6-7. EPROM's Data Retention Time 



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Application 



floating gate of the EPROM with varying efficien- 
cies. Fluorescent light and sunlight contain some 
ultraviolet light, and so prolonged exposure to these 
lights can cause data corruption as a result of 
electric charge dissipation. Figure 6-7 shows the 
standard, data retention time under an ultraviolet 
eraser, sunlight and fluorescent lighting. 

6.4 Optimized High-Speed Programming 

With the increase of EPROM density, the time for 
programming becomes more important. The 
method for high speed programming has been de- 
veloped and put into practical use according to 
each EPROM generation. 

Following explains three methods for High-Speed 
programming. 

(1) First generation ... conventional programming. 
This method is employed in the 3 urn and 5 urn 
process products. Programming is performed with 
a uniform pulse of 50 ms per byte. Although it is 
the advantage that it applies enough pulse to all 
bits, it takes much time to program high density 
devices. 

(2) Second generation ... High performance 
programming 

This method is employed in 2 Aim process product. 
"High Performance programming (figure 6-8) is 



performed with a base pulse of 1 ms width. It 
repeats programming and reading (verifying) until 
the data is programmed enough. There are two 
good points in this programming. 
First, the programming itself is performed with 
optimum program time depending on the capabili- 
ty of each memory cell. 

Second, after verification, the data is programmed 
using three times as long a pulse and assures high- 
reliability data retention. 

(3) Third generation ... Fast High Reliability Pro- 
gramming 

This method is employed in the 1 .3 urn process 
products. "Fast High-Reliability Programming" 
(figure 6-9) is performed with a base pulse of 0.2 
ms. It also shortenes a supplement pulse width to 
one-third of that of "High Performance Pro- 
gramming". As a result, this method realizes short 
programming time, reduced to one-tenth 
theoretically. 

1M bit EPROM series employ "Page Pro- 
gramming", which programs 32-bit at once (figure 
6-10), reducing programming time to a quarter of 
"Fast High-Reliability Programming" for 128k x 8 
organization and a half for 64k x 16 organization. 
Figure 6-1 1 shows the programming time of above 
methods. 



(start) 



SET PBOG./VERIFV MODE 
V >> =i;.St0.3VVct=60tO.?5V 



| Address=g "| 




(7ml) 



Figure 6-8. High-Speed Programming 

(High Performance Programming) 



SET PROG./VEWFY MODE 
V„=1?.5±0.3V Vcc=6 0±0.?5V 



| Addressee 



n + l-*n 



| Program 



=0.2ms±5% 




^VERIFY 

C5o 



NOGO 



Program t o ,» = 0.2n ms 



NO 




SET READ MODE 
Vcc=5.0±[).25V,V»=Vcc 




NO 



'n = 2S 




YES 



Figure 6-9. 0.2ms High-Speed Programming 

(Fast High-Reliability Programming) 



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Application 



( START ) 



SET PAGE PROGRAM LATCH MODE 
V,, =1 2.5V ± 0.3V, Vcc=6.0V±0.25V 



Address ="o~| 



| Address +1 —Address ] 



| Address + 1 --Address | 

| Latch | 
| Address + 1 -Address | 



SET PAGE PROG./VERIFY MODE 
V,r = 12.5V±0.3V, V cc = 6.0V ± 0.25V 



Address + 1— , 



| Program t,. = 0.2ms ± 5%] 

] < ^ > ^o_ 

[Program t O p w =0.2n ms| 
NO 




YE§_ 



CSET READ MODE 



.0V±0.25V, V,,=V C c 



NOGO 





Figure 6 10. Page -Mode Programming 



. Slims programming 




64k 128k 256k 512k 1M 2M 

Storage capacity! x 8 organization) 



4M 

(bit) 



(Note) Actual program time differs according to 
the programmer. 

Figure 6-11. Shortened Program Time by High- 



6.5 Device Indentifier Code 
EPROM programming conditions depend on 
EPROM manufacturers and device types, confusion 
may cause miss operation. As a countermeasure 
some EPROMs provide device identifier code in- 
cluding such information as manufacture and device 
type. Some newly developed commercial EPROM 
programmers can set write conditions automatically 
by recognizing this code. 

Different programming conditions are as follows: 
(1) program voltage, (2) program timing, (3) high- 
performance programming algorithm, (4) pin con- 
figuration. The Hitachi EPROM has a device 
identifier code area besides the memory access area, 
as shown in figure 6-12. 



f 

AJdrg.il ^ o 

y 



Device identifier code ■ 




M I N I M , 

Din c$ | I/O control circuit | r^> Dout 

Figure 6-12. Device Identifier Code 

Table 6-1 describes how to use the device identifier 
code. Setting A9 at 12 V and A1 - A8, A10 - A13 
at V| L access the device identifier code area and 
1/00 — 1/07 output the programming condition 
code with V| L or V, H of AO. 



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Application 



Tablel 6-1. Hitachi EPROM Device Identifier Code 





A„ 


I/08-I/015 


1/07 


1/06 


1/05 


1/04 


1/03 


1/02 


I/Ol 


I/OO 


Hex Data 


Manufacturer 
Code 


Hitachi 


VlL 



















1 


1 


1 


07 


ROM 

code 


HN27128A 

HN27256 

HN27C2S6 

HN27C256H 

HN27C256A 

HN27512 

HN27C1024H 


VlH 







1 




1 
1 














1 
1 
1 



1 





1 







1 


1 





1 




1 







1 


1 




1 
1 





OD 
10 
BO 
31 
31 
94 
BA 



A9: 12V 

Al -A8, A10-A13: V IL 
A14, A15: Don't care 



6.6 Shielding Label 

When using an EPROM in an environment where it 
can be exposed to ultraviolet light, Hitachi recom- 
mends putting a shielding label on its transparent lid 
to absorb ultraviolet light. In choosing a shielding 
label, the following points should be carefully 
checked. 

* Adhesiveness (mechanical strength). Avoid 
repeated attaching or exposure to dust that may 
reduce the adhesive strength. Ultraviolet erasing 
and reprogramming are recommended after 
stripping off an attached label. (When the need 
arises to change a label, it is advisable to put a 
new one on over the old one since peeling may 
create a static charge.) 

* Allowable temperature range. Use the shielding 
label in an environment whose temperature falls 
within the specified allowable temperature range. 
Beyond the specified temperature range, the 
paste on the label may harden or stick too fast.- 
When it hardens, the label may come off easily. 
When it sticks too fast, the paste may remain on 
the window glass after the label has been re- 
moved. 

* Moisture resistance. Use the shielding label in an 
environment whose humidity falls within the 
specified allowable humidity range. 

6.7 EPROM Programmer 

The EPROM programmer stores the user's program 
in its internal RAM and writes the program in the 
EPROM. For this programming, 3 functions at least 
are necessary: blank check function prior to pro- 
gramming, programming function, and the verify 
function after programming. Figure 6-13 shows the 
programming flow chart. Some programmers check 
for pin contact failure or the reverse insertion 
before the blank check. 
The outline of each block is as follows. 



Hitachi America, Ltd. • Hitachi Plaza - 



1. Pin contact check 
In the ROM pin and socket connection test, 
checking is normally performed by detecting the 
forward current at each EPROM pin. Care is 
necessary as this forward biased resistance differs 
in products of each company. 

2. Reverse insertion check 
This check detects the reverse insertion of the 
device, places the equipment in reset mode and 
protects the device and equipment. 

3. Blank check 
This check is performed before programming. It 
checks whether the device is an erased EPROM, 
or it preventing EPROM reprogramming. Since 
the output data in the erased condition are 1 
(high level), check whether or not data in 
EPROM are all 1. It will fail-stop even when one 
bit is (low level). Normally, it is designed to 
provide warning with a lamp or buzzer. 

4. Programming 
The function of programming the data in the 
internal RAM of the programmer into EPROM 
will fail-stop when programming cannot be done. 
The normal flow is as shown in figure 6-14. The 
EPROM data will be read out prior to pro- 
gramming and compared with programming data. 
If they coincide, programming will be skipped 
and if they differ, programming will be per- 
formed. Then, the data will be read out again 
and compared with the programming data, and if 
they coincide, the programmer will progress to 
the next address. 

5. Verify 

This function checks after programming com- 
pletion whether or not the programming is 
correct when comparing with the data in the 
internal RAM of the programmer. It performs 
fail-stop when they do not coincide. Normally, 
when it fails, it lights the fail lamp and displays 

HITACHI 

2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 




Figure 6-13. Programming Figure 6-14. Programming 
Flow Chart of EPROM Flow Chart of EPROM 

Programmer (1) Programmer (2) 

the address and data. 
6. How to input the program 

Table 6-2 shows several methods for inputting 
the program data to the internal RAM of the 
programmer. Normally, paper tape input and 
teletypewriter input are prefered options. 



Table 6-2. EPROM Data Input 



Method 


Content 


Copy input 


Input by copying the master ROM. 


Manual input 


Input by the keyswitch on the front 
panel. Used for correction or 
revision of program 


Paper tape input 


Read the paper tape furnished 
from the host system with the 
tape reader 


Teletypewriter 
input 


Input with the teletypewriter. 
Preparation, correction, and list 
preparation of the program can be 
made. 



6.8 Handling EPROMs 

Touched with a charged human body or rubbed 
with plastics or dry cloth, the glass window of an 
EPROM generates static electricity which causes de- 
vice malfunctions. Typical malfunctions are faulty 
blanking and write margin setting that give the false 
impression that information has been correctly 
written in. As already reported at the international 
conferences concerning the reliability of LSI chips, 
this is due to the prolonged retention of electric 
charge (resulting from the static electricity) on the 



Application 

glass window. Such malfunctions can be eliminated 
by neutralizing the charges by irradiating with ultra- 
violet rays for a short time. The EPROM should be 
reprogrammed after this irradiation since it reduces 
the electric charges in the floating gate, too. The 
basic countermeasure is to prevent the charging of 
the window, which can be achieved by the following 
methods as in the prevention of common static 
breakdown of ICs. 

1. Ground operators who handle the EPROM. 
Avoid using things such as gloves that may 
generate static electricity. 

2. Refrain from rubbing the glass window with 
plastic or other materials that may generate static 
electricity. 

3. Avoid the use of coolant sprays which contain 
some ions. 

4. Use shielding labels (especially those containing 
conductive substances) that can evenly dis- 
tribute established charge. 

6.9 Ensuring OTPROM Reliability 

One time electrically programmable ROM 
(OTPROM) has two kinds of packages: standard 
dual in-line package (DIP) and small outline package 
(SOP). It is one time only programmable because it 
has no window for ultraviolet light exposure; testing 
by programming and erasure cannot be performed 
after it is assembled. 

So, Hitachi performs screening test for program- 
ming, access time, and data retention on wafers at 
proving test. 

However, rare defects may occur in the assembly 
process cannot be completely removed in final test 
screening which is only a reading test. 
Therefore, Hitachi recommends that users perform 
high temperature baking after programming devices 
to ensure high reliability. 

Detailed conditions and procedures for screening are 
shown in figure 6-15. First, program and verify 
devices. Then, leave them without bias at 125 to 
1 50°C for 24 to 48 hours. 

After that, check read-out function and remove the 
chips with data retention failures. 
From the results of devices in which the recom- 
mended screening test is properly performed, we 
confirm that the data retention characteristics of 
OTPROMs are equal to general EPROMs. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 55 



Proving! 1) StafiJlS* 



Wafer 
Boeing 



Erasure 
I 



Dau 

Retention 



Wafer Screening 



Program and 
Verify 
by Programmer 



Baking at 
125 to lSCC 
for 24 to 48hrs 



1 



Screening Conditions 

Figure 6-15. Screening Flow Chart of OTPROM 



56 



<§► HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Application 



7. MASK ROM PROGRAMMING INSTRUCTION 

The writing of the custom program code into mask 
ROMs is performed by the CAD system on a large- 
sized computer. ROM code data should conform to 
specifications given below, using either paper tape, 
EPROM, or magnetic tape. Additional instructions, 
such as chip select and customers' part number, 
should be given in the "ROM Specification Identifi- 
cation Sheet" 

7.1 Specification of EPROM 

1. Submit the three sets of the EPROM-stored data. 
Specify the address of the EPROM in the case of 
two or four EPROMs. 

2. The ROM code data is input from the start 
address to Final Address in the EPROM. 

3. Type of EPROM 

HN482764 (8-kword x 8-bit, 2764 Compatible) 
HN4827128 (16-kword x 8-bit, 27128 Com- 
patible) 

HN27256 (32-kword x 8-bit, 27256 Com- 
patible) 

HN27C256 (32-kword x 8-bit, 27C256 Com- 
patible) 

7.2 Specification of Magnetic Tape 

1. Use the following type of magnetic tape which 



Length 2,400 feet, 1 ,200 feet or 600 feet 

Width 1/2 inch 

Channel 9 channels 

Bit density .... 800 B PI or 1,600 BPI (Clearly 
state which it is in the "ROM 
Specification Indetification 
Sheet".) 

2. Use EBCDIC as the use code. 

3. Follow the format of the magnetic tape as de- 
scribed below 

No leading tape mark 
No label 

Record size 80 byte/1 record 

Block size 10 records/1 block 

The end of the file should be indicated by 2 
successive tape marks (TM) (figure 7-1). 

4. HMCS6800 load module data mode. This mode 
is the object mode output from the assembler 
HMCS6800. 

Divide the 8-bit code into the upper and lower 
4-bit codes, and convert each into hexadecimal 
notation. 

Example: The code 1100 0110 is as follows 

under binary notation. 
(Upper 4-bits) (Low4-bits) Bit weight 
D7 D6 D5 D4 D3 D2 D 1 DO ( ROM output 
1 1 1 1 equivalence) 



can be used by a magnetic tape device 
patible with the IBM magnetic tape device. 


com- 


7-2. 










I 


T 


Block 1 


Block 2 


Biock a 


! 


T 
M 


T 
M 




E 

T 



Figure 7-1. Magnetic Tape Format 



Header 

record 



Record Stan 


5 3 


S 


5 3 


S 


S 3 


S 


Record Type 
Byie Couni 


3 





3 1 


1 


3 9 


9 


3 1 
3 6 


1 6 


3 
3 3 


3 


3 
3 6 


6 
0000 


Address Siie 


3 1 

3 1 
3 
3 


1100 


3 
3 
3 
3 




3 
3 
3 
3 


Dmt. 


3 4 
3 8 


48-H 


3 9 
3 8 


9 8 


4 6 
4 3 


cr 1 Check 
"- S...I 


3 
3 2 






Dku 


3 4 
3 4 


44-D 


2 




Dtia 


3 5 
3 2 


5Z-R 






4 1 
3 8 


AB [Check Sum 1 


Chech Sum 


3 1 

4 2 


IB ( Check Sum ) 



Figure 7-2. HMCS680O0 Load Module Data Format 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 57 



Application- 



SO indicates the head of the file and S9 indicates the 
end of the file. The actual data starts following S1. 
This means that the data starts from the address 
(hexadecimal) indicated in the address size. The 
address of the address size of the data recorder is 





compared with the next data recorder address by 
counting in increments of 1 byte of the data and 
checking whether it is sequential or not. The 
printed example of the HMCS6800 load module 
mode is as shown in figure 7-3. 





Header Record -S00B0000582045584 14D504CB5 

Data Record -S113F0O07EF5587EF7897EFAA77EF9C07EF9C47E24 

Data Record -SI 12F0 10FA657EFA8B7EFAA07EF9DC7EFA24 7E06 
End of 

File Record -$9030000 FC 

1 



Figure 7-3. HMCS6800 Load Module Example 



If an address is skipped, enter the skipped address 
into the "ROM Specification Identification Sheet" 
and the data (00 or FF) entered into the skipped 
address. 

5. BNPF mode 

One word is symbolized by the word start mark 
B, the bit content represented by 8 characters of 
P and N, and the BNPF slice composed of succes- 
sive 10 characters of the work end mark F. 
The contents from F of one BNPF slice up to B 
of the next BNPF slice are ignored. 
(Example) The code of AA (hexadecimal) is 

symbolized as shown in figure 7-4. 
It is necessary to designate the bit pattern (BNPF 
slice) on all ROM addresses. Therefore, the term 
of the ROM head address of "ROM Specification 
Identification Sheet" always becomes 0. 
B 
N 













7.3 Specification of Floppy Disk 

1. Use the following type of floppy disk (figure 
7-5): 

Type. ... 8 Inch Single Sided and Single Density 

Number of Sectors 26 

Number of Tracks 77 



Sector 21 



F Indicates end of 1 word. 




Track 00 
(Index -Track) 



Figure 7-5. 



2. Use EBCDIC as the use code. 

3. Format the floppy disk as described I 
Composition is described in table 7-1. 

Record size 80 byte/1 record 

Table 7-1 . Floppy Disk Composition 



Figure 7-4. BNPF Mode Example 



No. 


Item 


Location 


Track 


Sector 


1 


Standard Volume Label 


00 


07 


2 


Standard Head Label 


00 


08 - 26 


3 


Data Area 


01 - 73 


01 - 26 


4 


Alternal Track 


75,76 


01 - 26 


5 


Spare Track 


00 
74 


01 - 06 
01 - 26 



HITACHI 

58 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Application 



Use the sectors as in figure 7-6. Use one sector used for one record. 

for one record, that is, 80 bytes out of 128 bytes 4. Data Mode. See data mode for magnetic tape. 



"1 



(128 bytes) 


(128 bytes 




r» 

1128 bytes) 




Record 1 
(80 bytes! 


• 


Record 2 
(80 bytes! 




Record 3 
(80 bytes) 


1 





Sector 24 





(128 bytes) 



/ Record >i „ 
/ (KObylesI / 180 bytes) '/ 



Record 26 
180 bytes) / 



Figure 7*. Floppy Di«k Sector Formet 



ROM Coii 



Select 




I Suppl, I 



SEE 



"1 

Check tht 
^ ROM Sptiirmiion ^ 
^ IdtniUKiiion 5h«i ^ 

ROM Code 




[ Hit. Ertrmiiw ] 




Figure 7-7. Meek ROM Development Flowchart 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



59 



Application 



8. INSTRUCTIONS FOR USING MEMORY 
DEVICES 

8.1 Prevention of Electrostatic Discharge 

As semiconductor memory designs are based on a 
very fine pattern, they can be subject to malfunc- 
tion or defects caused by static electricity. Though 
the built-in protection circuits assure unaffected re- 
liability in normal use, devices should be handled 
according to the following instructions: 

1. In transporting and storing memory devices, put 
them in conductive magazine or put all pins of 
each device into a conductive mat so that they 
are kept at the same potential. Manufacturers 
should give enough consideration to packing 
when shipping their products. 

2. When devices touch a human body in mounting 
or inspection, the handler must be grounded. Do 
not forget to insert a resistor (1MH approx is 
desirable) in series to protect the handles from 
electrical shock. 

3. Keep the relative ambient humidity at about 50% 
in process. 

4. For working clothes, cotton is preferrable to 
synthetic fabrics. 

5. Use a soldering iron operating at low voltage (12 
V or 24 V, if possible) with its tip grounded. 

6. In transporting the board with memory devices 
mounted on it, cover it with conductive sheets. 

7. Use conductive sheets of high resistance (about 
10 9 ohm/a) to protect devices from electrostatic 
discharge. For, if dropped onto conductive 
materials like a metal sheet, devices may de- 
teriorate or even breakdown owing to sudden 
discharge of the charge stored on the surface. 

8. Never set the system to which memory devices 
are applied near anything that generates high 
voltage (e.g. CRT Anode electrode, etc.). 

8.2 Using CMOS Memories 

As shown in figure 8-1, the input of a CMOS 
memory is connected to the gate of an inverter con- 
sisting of PMOS and NMOS transistors. Figure 8-2 
shows the relationship between the input voltage 
and current in this inverter. The top and bottom 
transistors turn ON and make current flown when 
the input voltage becomes intermediate level. There- 
fore, it is necessary to keep the input voltage below 
0.2 V or above V cc - 0.2 V in order to minimize 
power consumption. The data sheet specifies the 
stand-by current for both the cases of input level 
with minimum V, H and maximum V lu and that 
with 0.2 V or — 0.2 V, and the difference in 
value is remarkably great. Some memory devices 



are designed to cut off such current flow in standby 
mode by the control of input signals, but it depends 
on device type. This should be confirmed in data 
sheets for each device type. 



Vcc 




Figure 8-1. CMOS Inverter 




1 2 3 4 5 6 
Input Voltase 



Figure 8-2. Relationship between Input Voltage & Current 
In CMOS Inverter 

Another problem particular to CMOS devices is 
latch-up. Figure 8-3 shows the cross section of a 
CMOS inverter and the structure of a parasitic 
bipolar transistor. The equivalent circuit of the 
parasitic thyristor is shown in figure 8-4. When 
positive DC current or pulse noise is applied (figure 
8-4 (a)), TR3 is turned on owing to the bias voltage 
generated between base and emitter. And trigger 
current flows into GND through R P , the base re- 
sistance of TR2. As a result, TR2 becomes conduc- 
tive and current flows from power supply (V cc ) 
through the base resistance of TR1 (R N ), which 
puts TR1 into conduction, too. Then, as the base 
of TR2 is rebiased by collector current from TR1, 
the closed loop consisting of TR1 and TR2 reacts. 
Thus current flows constantly between power 
supply (V cc ) and GND even without trigger current 
caused by outside noise. 

Latch-up can be caused by a negative pulse, too 
(figure 8-4 (bb)). Most of semiconductor memory 
manufacturers are trying to improve latch-up im- 
munity of their products. Hitachi provides enough 
guard band by applying diffusion layer around 
inputs and outputs, taking care not to connect input 
to p + diffusion layer. Input voltage for 64 kbit 



HITACHI 

60 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



static RAM HM6264A, for example, is specified as Thus almost no consideration for latch-up is re- 



follows: 

V )H max 6.0 V (not depending on V cc ) 
V| L min3.0V (pulse width = 50 ns) 
-0.3 V (DC level) 



in system 



Internal Inpul o- 

V«(+5V) Vcc 



Internal Input 




Figure 8-3. Cross Section Structure of CMOS Inverter 



Closed Loop 
Pin HiTrVf 




Positive T„ ON *! 
Voltage 



(a) Thyristor Effect by 
Positive Voltage 




lb) Thyristor Effect by 
Negative Voltage 



Figure 8-4. Equivalent Circuit of Parasitic Thyristor 



8.3 Noise Prevention 

Noise in semiconductor memories is roughly clas- 
sified into input signal noise and power supply 



8.3.1 Input Signal Noise 

Input signal noise is caused by overshoot and under- 
shoot. If either of them is out of recommended DC 
operating conditions, normal operation is hindered, 
and voltage over absolute maximum rating will 
break the device. In operating high speed systems, 
special care is required to prevent input signal 
noise. 

The noise can be prevented by inserting a serial re- 
sistance of less than 50 ohm into each input or a 
terminating resistance into the input line. Actually, 
however, input signal noise can be simply reduced by 
a stable power supply line, because it is often caused 
by unstable reference voltage (GND level). 



8.3.2 Power Supply Noise 

The power source noise can be classed as low- 
frequency noise and high-frequency noise as shown 
in figure 8-5. To assure stable memory operation, 
the peak-to-peak power supply voltage in the pre- 
sence of low-or high-frequency noise should be held 
below 10 percent of its standard level. 




Figure 8-5. Power Source Noise 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 61 



Application 



Devices like dynamic RAMs, which operate from 
clock signals, or high speed CMOS static RAMs, 
through which current flows during transition of 
signals, consume high peak current. When a power 
supply does not have enough capacity for the peak 
current, voltage drops. And if the recovery rate of 
the power supply synchronizes with its time con- 
stant, it may start oscillating. To reduce the in- 
fluence of the peak current, a bypass capacitor of 
0.1 — 0.01 fiF should be inserted near the device. 
The following points must be considered in design- 
ing pattern of the board: 

* For bypass capacitors, use titanium, ceramic, or 
tantalum capacitors which have better high- 



frequency characteristics. 

Bypass capacitors must be applied as near to the 
power supply pin of memory devices as possible, 
and inductance in the path from V cc pin to V ss 
pin through the bypass capacitor must be as little 
as possible. 

The line connected to the power supply on the 
board should be as wide as possible. 
It is preferrable for the power supply line to be 
at right angles to devices selected at the same 
time, lest too much peak current should flow 
through one power supply line at a time. 



cs 

Signal 




hmi 



4^ 



EOttfT 



-Faulls- 
. Bypath Lines are too 
Long. 
. Devices Selected at 
a Time are on the 
Same Mother Line. 



Figure 8-6. Examples of Power Supply Board Pattern 



8.4 Address Input Waveform of Hi-BiCMOS 
Memory 

Data stored in memory might be destructed in case 
that Address Input of the HM6716, HM6719, 
HM6787, HM6788 and HM6789 series becomes 
floating and sticks at and around threshold voltage, 
(e.g. CPU does Address Bus to off state in Figure 1.) 
Consequently, the following three methods are re- 
commended so as to preserve malfunction of 
memory device. 

A: Insert latch as shown in Figure 8-7 lest Address 

Input should become floating. 
B: Put CS into High while Address Input becomes 

floating. 

(Dotted line in Figure 8-8) 
C: Insert Pull-up Resistor (R) to hold time 
constant of Rising Edge wave form of Address 
Input pin (tr = R x C) below 150 ns. 
Stable operation can be assured if you have already 
adopted the above three method (A, B, C), while 
if you have any problem, please contact our sales 
offices. 



Address 
Input 



CS 



Pull-up 




Figure 8-7 



t, 











Floating 



Figure 8-8 



HITACHI 

62 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 




Section 1 
MOS Static RAM 



HITACHI 



HM6116 



Maintenance Only 



2048-word x 8-bit High Speed CMOS Static RAM 

■FEATURES 

• Single 5V Supply 

• High speed: Fast Access Time 120ns/150ns/200ns (max.) 

• Low Power Standby and Low Power Operation 

Standby: IOOjuW (typ.) 

10juW (typ.) (L-version) 
Operation: 200mW (typ.) 

175mW (typ.) (L-version) 

• Completely Static RAM: No clock or Timing Strobe Required 

• Directly TTL Compatible: All Input and Output 

• Pin Out Compatible with Standard 16K EPROM/MASK ROM 

• Equal Access and Cycle Time 

• Capability of Battery Back Up Operation (L-version) 



■ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6116P-2 
HM6116P-3 
HM6116P-4 


120ns 
150ns 
200ns 


600mi] 24pin 


HM6116LP-2 
HM6116LP-3 
HM6116LP-4 


120 ns 
150 ns 
200 ns 


Plastic DIP 


HM6116FP2 
HM6116FP-3 
HM6114FP-4 


120 ns 
150 ns 
200 ns 


24pin Plastic SOP 


HM6116LFP-2 
HM6116LFP-3 
HM6116LFP-4 


120 ns 
150 ns 
200 ns 



■FUNCTIONAL BLOCK DIAGRAM 




HM6116P Series 

(DP-24) 

HM6116FP Series 




IFH-24DI 



■ PIN ARRANGEMENT 



HZ ^ 




*LT 


2] | A. 


*E 


3* 


-LI 


We 


Aj rjr 


2" | OE 


A, fT 


1" | All 




~i«~|"c? 


a. rjr 


i7 1 tm 


i o, pr 


It | I/O 


i/oiQir 


~is"| i/n. 


i.o. fiT 


ii | l/a 


v.s QT 


13 | I/O. 



ITnp V„. 



Note) Thii device is not available 
for new application. 



HITACHI 

64 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM61 16 Series 



■ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


fnit 


Voltage on Any Pin Relative to Van 


r- 


0.5 - ' to + 7.0 


V 


Operating Temperature 


T... 


to +70 


"C 


Storage Temperature 


T.„ 


-55 to + 125 


"C 


Storage Temperature Under Bias 


T.„. 


-10 to +85 


'C 


Power Dissipation 


P, 


1.0 


w 



Nutcl » !. 3.5V for pulse widths."*!!:* 



■TRUTH table 



cs 


OF. 


WE 


Mode 




Vcr Current 


I/O Pin 


, 

Ref. Cycle 


H 


X 




Not Selected 


/sa. /in 


High Z 




L 


L 


H 


Read 


Ice 


Dout 


Read Cycle HMS 


L 


H 


L 


Write 


he 


Din 


Write Cycle (1) 


L 


L 


L 


Write 


he 


Din 


Write Cycle (2) 



■RECOMMENDED DC OPERATING CONDITIONS (7o-0 to +70C) 



Item 


Symbol 


min 


typ 


max 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vis 











V 


Input Voltage 


B« 


2.2 


3.5 


6.0 


V 


V, L 


-0.3" 




0.8 


V 



Note) » 1. -3.0V for pulse width S Sins 



■ DC AND OPERATING CHARACTERISTICS (Vcc = 5V + 10%, Vss = 0V, Tfl=0to+70°C) 



Item 


Symbol 


Test Conditions 


HM6116-2 


HM6116-3/-4 


Unit 


min 


typ*' 


max 
10 


min 


typ" 


max 


Input Leakage Current 


M 


Vcc = 5.5V. Vin= Vss to Vcc 










10 








2* 3 






2* 3 


Output Leakage Current 


\hx\ 


CS= K,«orOE = V/h, 
V:io = Vss to Vcc 






10 






10 


tt& 






2*3 






2* 3 


Operating Power Supply 
Current 


Ice 


CS— Vil, ho — 0mA 




40 


80 




35 


70 


mA 




35* 3 


70* 3 




30* 3 


60* 3 


Iccx' 2 


V;h=3.5V, Vi/.=0.6V. 
/fo=0mA 




35 






30 




mA 




30* 3 






25* 3 




Average Operating Current 


/CC2 


Min. cycle. duty =100% 
/; o=0mA 






40 


80 




35 


70 


mA 




35* 3 


70* 3 




30* 3 


60* 3 


Standby Power Supply 
Current 


I SB 


CS= Vm 




5 


15 




5 


15 


mA 




4.3 


12* 3 




4* 3 


12* 3 


Isb\ 


CS2 Vcc -0.2V. 0VS Vi»S 
0.2V or Vrr-0.2VSfe 




0.02 


2 




0.02 


2 


MA 




2* 3 


50* 3 




2* 3 


50* 3 


Output Voltage 


Vol 


/oi. = 4mA 






0.4 








V 


/<)L = 2.1mA 












0.4 


V 


Voh 


Ioh= — 1.0mA 


2.4 






2.4 






V 



Notes! »t. M. =5V. Tn=2?C 
»2 Reference Only 

♦ 3. This characteristics are Ruaranteed only for L-version. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



65 



HM611 6 Series 



■CAPACITANCE (/-1MHz, ra-25"C) 



Item 


Symbol 


Test Conditions 


typ 


max 


Unit 


Input Capacitance 


C. 


V..-0V 


3 


5 


pF 


Input/Output Capacitance 


Cl/Q 


su-av 


5 


7 


PF 



Note) This parameter is sampled and not 100% tested. 

■AC CHARACTERISTICS (Vcc-5V±10%, Ta-0 to + 7(TC) 
• AC TEST CONDITIONS 

Input Pulse Levels: 0.8 to 2.4V 

Input Rise and Fall Times: 10 ns 

Input and Output Timing Reference Levels: 1.5V 

Output Load: 1TTL Gate and Q. (100pF) (including scope and jig) 



•READ CYCLE 



Item 


Symbol 


HM6116-2 


HM6116-3 


HM6116-4 


Unit 


min 


max 


min 


max 


min 


max 


Read Cycle Time 


1 »c 


120 




150 




200 




ns 


Address Access Time 






120 




150 




200 


ns 


Chip Select Access Time 


ttcs 




120 




150 




200 


ns 


Chip Selection to Output in Low Z 


tCLl 


10 




15 




15 




ns 


Output Enable to Output Valid 


toe 




80 




100 




120 


ns 


Output Enable to Output in Low Z 


toLZ 


10 




15 




IE 




ns 


Chip Deselection to Output in High Z 


tCHI 





40 





50 





60 


ns 


Chip Disable to Output in High Z 


I OH l 





40 





50 





60 


ns 


Output Hold from Address Change 


ton 


10 




15 




15 




ns 


• WRITE CYCLE 


Item 


Symbol 


HM6116-2 


HM6116-3 


HM6116-4 


Unit 


min 


max 


min 


max 


min 


max 


Write Cycle Time 


twe 


120 




150 




200 




ns 


Chip Selection to End of Write 


tew 


70 




90 




120 




ns 


Address Valid to End of Write 


t«m 


105 




120 




140 




ns 


Address Set Up Time 


Ias 


20 




20 




20 




ns 


Write Pulse Width 


twp 


70 




90 




120 




ns 


Write Recovery Time 


twn 


S 




10 




10 




ns 


Output Disable to Output in High Z 


torn 





40 





50 





60 


ns 


Write to Output in High Z 


twHZ 





50 





60 





60 


ns 


Data to Write Time Overlap 


tow 


35 




40 




60 




ns 


Data Hold from Write Time 


ton 


5 




10 




10 




ns 


Output Active from End of Write 


tow 


5 




10 




10 




ns 



■ TIMING WAVEFORM 
• READ CYCLE (1) " 



IDE 



- WWWVk 




X 



IZZZZZl 



L7ZL 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM61 16 Series 



•READ CYCLE(2)"" 



X 



X 



• READ CYCLEO)'" " 4 ' 

fs 



im 



> 



NOTES. 1. Wis High for Read Cycle. 

2. Device is continuously selected, CTT= K/^,- 

3. Address Valid prior to or coincident with CTtransition Low. 



• WRITE CYCLEO) 



4. 



727 



tA* 

test. 



777777^ 



te\V 

Jf////// 

y 

— IO« 

)DCKX 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 67 



HM6116 Series - 



• WRITE CYCLE (2)' 



cs 



WE 



N 


— ilC 

< ) 


( 










W 


s\\\\< 


' : ? 


V 


— 7 7 7 7 — 7 — 7 — 7 

/////// 




\\\\ 


— lit 






•-1*1— 

SSSSSS v 


>SS\ 




tow - 

5 — "VVx^ 


ID* 

< 


(DM 



p) of a low £5 and a low WE. 
. orWgoing high to the end 



NOTES: 1. A write occurs during the overlap (twpl 

2. t\vn is measured from the earlier of CS o 
of write cycle. 

3. During this period, I/O pins are in the output state so that the input 
signals of opposite phase to the outputs must not be applied. 

4. If the CS" low transition occurs simultaneously with the "WE" low 
transitions or after the WE transition, output remain in a high im- 
pedance state. 

5. OT is continuously low. (OF = V /L ) 

6. D out is the same phase of write data of this write cycle. 

7. Dqu, is the read data of next address. 

8. If CS is Low during this period, I/O pins are in the output state. 
Then the data input signals of opposite phase to the outputs must 
not be applied to them. 



ILOW Vcc DATA RETENTION CHARACTERISTICS Ta-0 to +70"C ) 
This characteristics are guaranteed only for L-version. 



Item 


Symbol 


Test Conditions 


mm 


typ 


max 


Unit 


Vcc for Data Retention 


Vd, 


CSiVcc -0.2V, V..SVcc -0.2V or V..S0.2V 


2.0 






V 


Data Retention Current 




Vfr = 3.0V.CS^2.8V. Vw£2.8V or 0V4 W.v^0.2V 






30 


M 


Chip Deselect to Data Retention Time 


tcon 


See Retention Waveform 









ns 


Operation Recovery Time 


la 











Notes) 10^A max at 7a=0"C to f 40*C. V, L min= - 0.3V 
*2. /nc^Read Cycle Time. 

• Low Vcc Data Retention Waveform 




68 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6116A Series 



Maintenance Only 



2048-word x 8-bit High Speed Static CMOS RAM 



■ FURTURES 

• High speed: Fast Access Time 1 20ns/l 50ns/200ns (max.) 

• Low Power Standby and Standby: 100fiW (typ.) 

Low Power Operation 5juW (typ.) (L-version) 

Operation: 15mW (typ.) (f = 1 MHz) 
10 mW (typ.) (L-version) 

• Single 5V Supply and High Density 24 Pin Package 

• Completely Static RAM: No clock or Timing Strobe Required 

• Directly TTL Compatible: All Input and Output 

• Pin Out Compatible with Standard 16K EPROM/MASK ROM 

• Equal Access and Cycle Time 

• Capability of Battery Back Up Operation (L-version) 

■ORDERING INFORMATION 



Type No. Access Time 


Package 


HM6116AP-12 


120ns 




HM6116AP15 


150ns 




HM6116AP20 


200ns 


600mil 24pin 


HM6116ALP-12 


1 20ns 


Plastic DIP 


HM6116ALP-15 


150ns 




HM6116ALP-20 


200ns 




HM6116ASP-12 


120ns 




HM6116ASP-15 


150ns 




HM6116ASP-20 


200ns 


300mil 24pin 


HM6116ALSP-12 


120ns 


Plastic DIP 


HM6116ALSP-15 


150ns 




HM6116ALSP-20 


200ns 





IFUNCTIONAL BLOCK DIAGRAM 





Memory Matrix 
128 x 128 



I/O.o 



Data 



J A A. A, A. 



3^ 



HM6116AP Series 




HM6116ASP Series 




(DP-24N) 



IPIN ARRANGEMENT 



,j 




A, 


2 






As 


3 






A< 


« 






A, 


5 




~ 


A, 








At 


7 




1 


Au 




I/Oi 


9 


I Oj 


10 




I Oi 


11 


V.. 


1! 



n, 

A. 

A9 

WE 

OE 

Aid 

CS 

I/O. 

I/O. 

I/O. 

I/O. 

I/O. 



(Top View) 



Note) This device is not available for new application. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 69 



HM61 1 6A Series 

■ABSOLUTE MAXIMUM RATINGS 



hem 


Symbol 


Rating 


Unit 


Voltage on Any Pin Relative to Vss 


V, 


-0.5" to +7.0 


V 


Operating Temperature 


r„. 


to +70 


•c 


Storage Temperature 


T.„ 


-55 to +125 


t 


Storage Temperature Under Bias 


r.... 


-10 to +85 


•c 


Power Dissipation 


p, 


1.0 


w 



Note! *1. - 3.5V for pulse wtdth^50ns. 



■TRUTH TABLE 



cs 


OE 


WE 


Mode 


Vrr Current 


I/O P,n 


Ref. Cycle 


H 




X 


Not Selected 


Is.. Is.. 


High Z 




L 


L 


H 


Read 


Icr 


Do ui 


Read Cycle 111-13) 


L 


H 


L 


Write 


Ice 


Din 


Write Cycle 111 


L 


L 


L 


Write 


Ice 


Din 


Write Cycle 121 



■RECOMMENDED DC OPERATING CONDITIONS (T„-0 to +70C) 



Item 


Symbol 


min 


O-P 


max 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5 5 


V 


Vss 











V 


Input Voltage 


Vi„ 


2.2 


3.5 


6 


V 


v, L 


-0.3" 




0.8 


V 



Notel * 1. -3.0V (or pulse widthSSOns 



■ DC AND OPERATING CHARACTERISTICS (V CC = 5V ± 10%, V ss = OV, T a = to +70°C) 



Item 


Symbol 


Test Condition 


HM6116A-12 


HM6116A-15 


HM6116A-20 


Unit 


min 


typ* 1 


max 


min 


typ*' 


max 


min 


typ*' 


max 


Input Leakage 
Current 




K CC =5.5V, V in =V ss 
to Vcc 






2 






2 






2 


»k 


Output Leakage 
Current 


\Ilo\ 


CS=K///orOE=K /// , 

v i/o=Vss to V CC 






2 






2 






2 


„A 


Operating Power 
Supply Current 


ice 


CS = V IL ,I I/o = 0mA 
V in = V IH oiV JL 




5 


15 




5 


15 




5 


15 


mA 




4* J 


12* J 




4 *2 


12* 3 




4*2 


12* 3 


icci 


ViH=V C C,V IL = W, 
CS = V IL ' 

// /o =0mA,/=lMHz 




3 


6 




3 


6 




3 


6 


mA 




2* 1 


5* J 




2*' 


5*' 




2* 2 




Average Operating 
Current 


ICC2 


min. cycle, 7jyo=0mA 
duty =100% 




35 


60 




25 


45 




20 


35 


mA 




30 * 2 


50* 2 




20* 2 


40 " 2 




15* 2 


30* 2 


Standby Power 
Supply Current 




CS=K /W 




1 


4 




1 


4 




1 


4 


mA 




0.5* ! 


3»' 




0.5* 3 


3* 3 




0.5* 3 


3* 3 




CS§ V CC -0.2V 
0V g Vin 




0.02 


2 




0.02 


2 




0.02 


2 


mA 






50" 




1*' 


50* J 




1*2 


50*' 


MA 


Output Voltage 


Vol 


J L = 4mA 






0.4 






0.4 






0.4 


V 


V H 


IqH = -1.0mA 


2.4 






2.4 






2.4 






V 



Notes) *l.V cc =SV,T a = 2S°C 

*2. This characteristics is guaranteed only for L-version. 



HITACHI 

70 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM61 1 6A 



■CAPACITANCE (/-1MHz. To-25-C) 



Item 


Symbol 


Test Conditions 


<yp 


mai 


Unit 


Input Capacitance 


C.. 


V..-0V 


3 


5 


pF 


Input/Output Capacitance 




V„o-0V 


5 


7 


pF 




Note) This parameter is sampled and not 100% tested. 

■AC CHARACTERISTICS (Vcc-5V±10%, 
• AC TEST CONDITIONS 

Input Pulse Levels: 0.8 to 2.4V 



Ta-0 to +7G-C ) 



Input Rise and Fall Times: 10 ns 
Input and Output Timing Reference Levels: 1.5V 
Output Load: 1TTL Gate and C/_ - lOOpF (including scope and jig) 

READ CYCLE 



Item 


Symbol 


HM6116A-12 


HM6116A-15 


HM6116A-20 


Unit 






min 


max 


min 


max 


min 


max 




Read Cycle Time 


'rc 


120 




150 




200 




ns 


Address Access Time 


'AA 




120 




150 




200 


ns 


Chip Select Access Time 


'ACS 




120 




150 




200 


ns 


Chip Selection to Output in* Low Z 


'CLZ 


10 




10 




10 




ns 


Output Enable to Output Valid 


'OE 




55 




60 




70 


ns 


Output Enable to Output in Low Z 


'OLZ 


10 




10 




10 




ns 


Chip Deselection to Output in High Z 


<CHZ 





40 





50 





60 


ns 


Chip Disable to Output in High Z 


'OHZ 





40 





50 





60 


ns 


Output Hold from Address Change 


'OH 


10 




15 




20 




ns 


• WRITE CYCLE 


















Item 


Symbol 


HM6116A-12 


HM6116A-15 


HM6116A-20 


Unit 


min 


max 


min 


max 


min 


max 




Write Cycle Time 


'wc 


120 




150 




200 




ns 


Chip Selection to End of Write 


'cw 


70 




90 




120 




ns 


Address Valid to End of Write 


'aw 


105 




120 




140 




ns 


Address Set Up Time 


'as 

















ns 


Write Pulse Width 


'wp 


70 




80 




100 




ns 


Write Recovery Time 


'WR 

















ns 


Output Disable to Output in High Z 


'OHZ 





40 





50 





60 


ns 


Write to Output in High Z 


'WHZ 





35 





40 





50 


ns 


Data to Write Time Overlap 


'dw 


35 




40 




50 




ns 


Data Hold from Write Time 


'dh 

















ns 


Output Active from End of Write 


'ow 


10 




10 




10 




ns 



■ TIMNG WAVEFORM 
• READ CYCLE (1)'" 



-'rc~ 



-'aa- 



cs 



Dout 



'OE~ 

~'OLZ- 



'acs- 



-'CLZ- 



UZZZZl 



~'OH~ 

mzzzL 



'OHZ 

'CHZ 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



71 



• READ CYCLE (2)' 



Dout 



• READ CYCLEO) 

CS 
Dout 



'acs- 

- — 'CLZ 



ZD 


IRC 

[ ) 




; <aa 

'OH -\ 






- — 'OH— 


> 




< x 



— <CHZ 



3- 



NOTES: 1. Wis High for Re»d Cycle. 

2. Device is continuously selected, CT= V^. 

3. Address Valid prior to or coincident with CTtransition Low. 

4. or- v IL . 



(WRITE CYCLEO) 



ZD 


'wc 

( ) 


£ 








'wrM 


//> 




'cw 


S 


WW 


\Y 




! 41 / 


<////// 






'aw 








\ / 






<wr lU 


/////// 


'DH— 




72 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6116A Series 



• WRITE CYCLE (2)"' 



Address ) ( 

csXT 



WE 



->wc- 



-'cw- 



mzzzzzL 



-'AW- 



tS-l 'WHZ 



Din- 



— 'DW- 



>WR [2] 



-'OH- 



-'OW 



-'dh— 



|7| 



[8] 



NOTES: 



p I'ujp) of a l ow CT and a low WE. 
r of CIS or WE going high to the end 



1. A write occurs during the overlap (ly 

2. I is measured from the earlier < 
of write cycle. 

3. During this period, I/O pins are in the output state so that the input 
signals of opposite phase to the outputs must not be applied. 

4. If the C5" low transition occurs simultaneously with the W low 
transitions or after the WE transition, output remain in a high im- 
pedance state. 

5. 0~HTis continuously low. (0T= V/i) 

6. D ou( is the same phase of write data of this write cycle. 
1 D out is lhe read data of next address. 

8. If CS is Low during this period, I/O pins are in the output state. 
Then the data input signals of opposite phase to the outputs must 
not be applied to them. 



ILOW Vcc DATA RETENTION CHARACTERISTICS (To-0 to + 70"C> 
This characteristics is guaranteed only for L-version. 



item 


Symbol 


Test Conditions 


min 


typ 


IM1 


Unit 


Vcc for Data Retention 


Vo* 


CSiVVc -0.2V 


2.0 






V 


Data Retention Current 




Vcc-3.0V. CSi2.8V. OVS Vis 






30 


?*■ 


Chip Deselect to Data Retention Time 


1 cot 


See Retention Waveform 









ns 


Operation Recovery Time 


■ ■ 


l.c' 2 






M 



Notes) * I. 10„A max at To = 0'C In I 40T. Vn inin~ -0.3V 
* 2.fcc- = Read Cycle Time. 

• Low Vcc Data Retention Waveform 




0»U Rmnlion jfaaj 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



73 



HM671 6 Series 
HM6719 Series 



Maintenance Only 



2048-word x 8-bit High Speed Hi-BiCMOS Static RAM (with OE) 
2048-word x 9-bit High Speed Hi-BiCMOS Static RAM (with OE) 



■ Features 

• Fast Access Time: 25/30ns (max) 

• Low Power Dissipation (DC): 280mW (typ.) 

• +5V Single Supply 

• Completely Static Memory No Clock or Timing Strobe Required 

• Balanced Read and Write Cycle Time 

• Fully TTL Compatible Input and Output 



■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6716P-25 
HM6716P-30 


25ns 
30ns 


300 mil 24 Pin 
Plastic DIP 


HM6719P-25 
HM6719P-30 


25 ns 
30ns 




■ PIN ARRANGEMENT 



■ Block Diagram 



a<° -[£= 



A,o' 



I/Oi°- 



Row 
Decoder 



Memory Matrix 

128X128 
(144) 



>V CC 
J V SS 



1/0,°- 
(9) 



n 



Input 
Data 
Control 



Column I/O 



Column Decoder 



WE 



(OE)_ 






(Top View) 
• HM6719 



■ Absolute Maximum Ratings 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage to Vgs Pin 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


P T 


1.0 


w 


Operating Temperature Range 


Topr 


to +70 


°c 


Storage Temperature Range 


T stg 


-55 to +125 


°c 



A 7 
A 6 
As 
A« 
A 3 
Aj 
A, 
A 
I/O, 
I/0 2 
l/0 3 

v S s 



C 6 

C 
c 
c 
c 
c 
c 



: 

9 

10 



12 



24 DV CC 

23 I)A 8 

22 DA 9 

21 3WE 

20 HCS 

19 DA,„ 

18 Dl/0 9 

17 1)1/0, 

16 DI/O, 

15 Dl/0 6 

14 Dl/0 5 

13 DI/O4 



(Top View) 



HITACHI 

74 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6716, HM6719 Series 



■ Truth Table 
• HM6716 



cs 


OE 


WE 


Mode 


Vqc Current 


Pin 


Ref. Cycle 


H 


Hor L 


HorL 


Not selected 




HighZ 




L 


L 


H 


Read 


!CC' 1 CC1 


Dout 


Read Cycle (1)(2)(3) 


L 


H 


L 


Write 


IcC'lca 


Din 


Write Cycle (1) 


L 


L 


L 


Write 


Icc^cci 


Din 


Write Cycle (2) 


L 


H 


H 


Output Disabled 


r co tcci 


High Z 





• HM6719 



CS 


WE 


Mode 


Vqc Current 


I/O Pin 


Ref. Cycle 


H 


HorL 


Not selected 


J SB> f SBl 


HighZ 




L 


H 


Read 


Icc^cci 


Dout 


Read Cycle (2) (3) 


L 


L 


Write 


Icc^cci 


Din 


Write Cycle (2) 



■ Recommended DC Operating Conditions (Ta = to +70° C) 



Item 


Symbol 


min 


typ 


max 


Unit 


Supply Voltage 


v C c 


4.5 


5.0 


5.5 


V 


v S s 


0.0 


0.0 


0.0 


V 


Input High Voltage 


Vim 


2.2 




6.0 


V 


Input Low Voltage 


V, L *> 


-3.0 




0.8 


V 



*) Pulse Width: 20ns, DC: -0.5V 



■ DC and Operating Characteristics (V cc = 5V ± 10%, T a = to +70°C) 



Item 


Symbol 


Test Conditions 


min 


typ 


max 


Unit 


Input Leakage Current 


I/Li 1 


V CC =S.SV, V lN = V SS to V CC 






2 


MA 


Output Leakage Current 




CS=ViH,V, /0 =V ss ioV cc 






2 


"A 


Operating Power Supply Current 


l cc 


CS=P , /L ,/ 7 /o=0mA 






120 


mA 


Average Operating Current 


Icci 


Min. Cycle, Duty: 100%// /o =0mA 






130 


mA 


Standby Power Supply 
Current 


J SB 


cs=v 1H 






30 


mA 


fSBl 


CS^ V cc -0.2\ 

V, N g 0.2V or Vis ^ V CC -0.2V 






10 


mA 


Output Low Voltage 


Vol 


/ L=4mA 






0.4 


V 


Output High Voltage 


Vqm 




2.4 






V 



■AC Test Conditions 

Input pulse levels: V$s to 3.0V 
Input and Output reference levels: 1 .5V 
Input rise and fall time: 4ns 
Output Load: See Figure 




Dout 
o — 



<? + 5V 

9ion 



30pF« 



620£i$ 



-r-5pF* 



Output 



nr 

Output Load B 

i'CHZ- twHZ' 'CLZ. low. toUZ- 'OHzl 



'including 
scope and jig 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 75 



HM6716. HM6719 Series 



■ Capacitance (T a = 25°C,/= 1.0 MHz) 



Item 


Symbol 


Test Conditions 


min 


typ 


max 


Unit 


Input Capacitance 


Cin 


K 7A rOV 






6 


PF 


I/O Capacitance 


c i/o 








8 


pF 



Note) This parameter is sampled and not 100%, tested. 



■AC Characteristics (K cc 5V ± 10%, T a = to +70°C, unless otherwise noted.) 
• Read Cycle 



Item 


Symbol 


HM67 16-25 
HM6719-25 


HM6716-30 
HM6719-30 


Unit 


Notes 


min 


max 


min 


max 


Read Cycle Time 


<RC 


25 




30 




ns 




Address Access Time 


'AA 




25 




30 


ns 




Chip Select Access Time 


'ACS 




25 




30 


ns 




Chip Selection to Output in Low Z 


'CLZ 












ns 


*2 


Output Enable to Output Valid 


'OE 





20 





20 


ns 


•1 


Output Enable to Output in Low Z 


<OLZ 












ns 


*1,*2 


Chip Deselection to Output in High Z 


'CHZ 





10 





12 


ns 


*2 


Chip Disable to Output in High Z 


<OHZ 





10 





10 


ns 


*1,*2 


Output Hold from Address Change 


'OH 


5 




5 




ns 




Input Voltage Rise/Fall Time 


>T 




150 




150 


ns 


*3 


• Write Cycle 


Item 


Symbol 


HM6716-25 
HM6719-25 


HM6716-30 
HM67 19-30 


Unit 


Notes 


min 


max 


min 


max 


Write Cycle Time 


<wc 


25 




30 




ns 




Chip Selection to End of Write 


'cw 


20 




25 




ns 




Address Setup Time 


'AS 












ns 




Address Valid to End of Write 


'aw 


20 




25 




ns 




Write Pulse Width 


'wp 


20 




25 




ns 




Write Recovery Time 


'WR 












ns 




Output Disable to Output in High Z 


>OHZ 





10 





10 


ns 


*1,*2 


Write to Output in High Z 


'WHZ 





10 





12 


ns 


*2 


Data Valid to End of Write 


'dw 


15 




15 




ns 




Data Hold Time 


'dh 


5 




5 




ns 




Output Active from End of Write 


'ow 












ns 


*2 



Notes) *1. These parameters are for HM6716. 

*2. Transition is measured ±200mV from steady state voltage with Load(B). 
This parameter is sampled and not 100% tested. 

*3. If tf becomes more than 150ns, there is possibility of function fail. 

Please contact your nearest Hitachi's Sale Dept. regarding specification. 



HITACHI 

76 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6716, HM67 19 Series 



■ Timing Waveforms 
• Read Cycled)* 1 



Address 



fc AA 



OE 



Dout 



k)LZ ► 



— 'ACS ' 
-tCLZ — 



High impedance 



XY7TT7 



k)HZ 
tCHZ 



• Read Cycle (2)* 1 '' 2 ' 4 



Address 



tRC 



X 



tOH ► 



tAA 



Dout Previous Data Valid ^ ^ 



XXX) ( 



X 



•oh 



Data Valid 



Read Cycle (3)* 1 ' 3 ' 4 
CS — 



>RC- 



'acs 



tCLZ-> 



Dout 



High 



tCHZ 



Date Valid 



•1 . WE is High for Read Cycle. 

*2. Device is continuously selected, CS- V/t_. 

*3. Address Valid prior to or coincident with CS transition Low. 
*4. OE-W/z.. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



77 



• Write Cycled) 



>c 



OE 



~ZZ7 



cs 



WE 



twc 



tew 



•*-*-\ Us 



'AW 



) ) ) ) n 



Dout 



y 



-twp 



'•1 



7T - 



Din ■ 



-Ql 



< — ► 



>C 



High Impedance 



tDW tDH 



Data Valid ) ( 







xx: 



78 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Write Cycle (2) " 5 



-HM6716, HM67 19 Series 



Address 




( g va lid 



Notes) *1. A write occurs during the overlap ttyvp' of a low CS and low WE. 
*2. tyvR is measured from the earlier of CS or Wl going high to the end 
of write cycle. 

*3. During this period, I/O pins are in the output state so that the input 
signals_of opposite phase to the outputs must not be applied. 

*4. If the CS low transition occurs simultaneously with the WE low tran- 
sitions or after the WE transition, output remain in a high impedance 
state . 

*5. OE is continuously low. (OE=l//^). 

*6. Dout is the same phase of write data of this write cycle. 

*7. Dout is the read data of next address. 

•8. If CS is Low during this period, I/O pins are in the output state. 
Then the data input signals of opposite phase to the outputs must 
not be applied to them. 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



79 



HM6268 Series 



4096-word x 4-bit High Speed CMOS Static RAM 
■FEATURES 

• Single 5V Supply and High Density 20 Pin Package. 

• High Speed: Fast Access Time 25/35/45ns (max.) 

• Low Power Standby: 100/iW typ, 5jiW typ (L-version) 

Active: 250mW typ. 

• Completely Static Memory: No Clock or Timing 
Strobe Required 

• Equal Access and Cycle Times 

• Directly TTL Compatible - All Inputs and Outputs 

• Capability of Battery Back Up Operation (L-version) 



■ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6268P-25 


25ns 






HM6268P-35 


35ns 






HM6268P-45 


45ns 


300mil 20pin 




HM6268LP-25 


25ns 


Plastic DIP 


HM6268LP-35 








HM6268LP-45 









■block diagram 



let 

ill 





■absolute maximum ratings 



htm 


Symbol 


Rating 


Unit 


Voltage on Any Pin Relative to Vss 


Vt 


-0.5" to +7.0 


V 


Power Dissipation 


P, 


1.0 


W 


Operating Temperature 


T„. 


to +70 


■c 


Storage Temperature 


T... 


-55 to +125 


•c 


Temperature under Bias 


T t , tt 


-10 to +85 


•c 



Note) « 1. -3.5V for pulse widthSlOns. 






(DP-20N) 



■PIN arrangement 





IVr 


A*(T 


T5|a, 


At [T 


ufj a, 


A, [7 


77] ai 


tf[T 


T6] Ao 


A. (T 


7s] I/O: 


A 10 [T 


J«J I/O, 


a„[7 


TJ] i/O) 




Ti] i/o, 




IT) WE 



(Top View) 



HITACHI 

80 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6268 Series 



I TRUTH TABLE 





WE 


Mode 


Vcc Current 


I/O Pin 


Ref. Cycle 


H 


X 


Not Selected 


Isb, /sai 


HighZ 




L 


H 


Read 


Ice 


Dout 


Read Cycle 


L 


L 


Write 


Ice 


Din 


Write Cycle 



I RECOMMENDED OPERATING CONDITIONS ( 7a = to + 70T 



Parameter 


Symbol 


min 


typ 


max 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 











V 


Input High (logic 1) Voltage 


VlH 


2.2 




6.0 


V 


Input Low (logic 0) Voltage 


V,L 


-0.5*' 




0.8 


V 



Note) * 1. -3.0V for pulse widthglOns. 

■ DC AND OPERATING CHARACTERISTICS (V cc 



5V ± 10%, V ss = OV, T a = to +70°C 



Parameter 


Symbol 


Test Condition 


Min. 


T> p. ' 


Max. 


Unit 


Input Leakage Current 


Hul 


V cc = 5.5V. V i0 = V ss to V cc 






2.0 


IjlA 


Output Leakage Current 


HloI 


CS = V IH .V I/0 = V ss toV cc 






2.0 




Operating Power Supply Current 


'cc 


CS = V, L , I„ = OmA, min. cycle 




50*3 


90 


mA 


Standby Power Supply Current 


'SB 


CS = V, H , min. cycle 




15 


25 


mA 


Standby Power Supply Current ( 1 ) 




CS == V cc -0.2V. 




0.02 


2.0 


mA 


'SBI 


0V < V ]N s 0.2V or V cc - 0.2V <: V IN 




I* 2 


50" 


*h 


Output Low Voltage 


Vol 


I OL = 8mA 






0.4 


V 


Output High Voltage 


V OH 


I OH = -0.4mA 


2.4 






V 



Notes) * 1, Typical limits are at Vcc = 5.0V. Ta = +25"C and specified loading. 
* 2. This characteristics is guaranteed only for L-version. 
*3. 40mA typ. for 45ns version. 

■CAPACITANCE ( Ta=2yC,/=1.0MHz) 



Parameter 


Symbol 


Test Conditions 


min 


max 


Unit 


Input Capacitance 


ClN 


K//v = 0V 




6 


pF 


Input/Output Capacitance 


Ci/o 


Wo = 0V 




9 


pF 



Note: This parameter is sampled and not 100°* tested. 



■AC CHARACTERISTICS ( K<x = 5V±10%, Ta = to +70°C, unless otherwise noted.) 



• AC Test Conditions 

Input pulse levels: Vss to 3.0V 
Input rise and fall times: 5ns 

Output Load (A) 

5V 



Input and Output timing reference levels: 
Output load: See Figure 

Output Load (B) 
(for t H Z. 'LZ. 'WZ & tQW) 



1.5V 



•480Q 




' 480Q 



Dout 



255Q< 



7*7- 



* Including scope and jig. 



77T 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



81 



HM6268 Series 
• READ CYCLE 



rarameier 


o y 1 u uui 


HM6268-25 


HM6268-35 


HM6268-45 


Unit 


min 


max 


min 


max 


min 


max 


Read Cycle Time 


he 


25 


- 


35 


- 


45 


- 


ns 


— 

Address Access Time 


Ua 




25 


- 


35 




45 


ns 


Chip Select Access Time 


Ucs 




25 




35 




45 


ns 


Output Hold from Address Change 


tOH 






5 




5 




ns 


Chip Selection to Output in Low Z 


tLZ* 1 


10 




10 




10 




ns 


Chip Deselection to Output in High Z 


tar" 





15 





20 





20 


ns 


Chip Selection to Power Up Time 


M 












(i 




ns 


Chip Deselection to Power Down Time 


tPD 




25 




25 




30 


ns 


Note) * L Transition is measured ± 20flmV from steady state voltage w 


th Load(B) 



This parameter is sampled and not 100% tested- 



• Timing Waveform of Read Cycle No. 1 



(11,(2) 



) 


uc 

< ) 


( 




lot 


U 






) 


(XXXXX) 


( D.t. V.lid A 



• Timing Waveform of Read Cycle No. 2 

cs 



(1),(3) 



Vet Supply / f( . 
Curreni 



T 



50% 



Notes: 1. WE is High for Read Cycle. 

2. Device is continuously selected, CS = V/i. 

3. Address Valid prior to or coincident with CS transition Low. 

• WRITE CYCLE 



Parameter 


Symbol 


HM6268-25 


HM6268-35 


HM6268-45 


Unit 


min 


max 


min 


max 


min 


max 


Write Cycle Time 


fee 


25 




35 




45 




ns 


Chip Selection to End of Write 


few 


20 




30 




40 




ns 


Address Valid to End of Write 


u* 


20 




30 




40 




ns 


Address Setup Time 


Us 

















ns 


Write Pulse Width 


A*/ 1 


20 




30 




35 




ns 


Write Recovery Time 


At s 

















ns 


Data Valid to End of Write 


tm 


12 




20 




20 




ns 


Data Hold Time 


tDH 

















ns 


Write Enabled to Output in High Z 


kz" 





8 





10 





15 


ns 


Output Active from End of Write 


*w" 

















ns 



Note)* 1. Transition is measured ± 200mV from steady state voltage with Load (B). 
This parameter is sampled and not I00°i> tested 



82 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Timing Waveform of Write Cycle No. 1 (WE Controlled) 



Address 



CS 



WE 



Din 



> 


( > 




— Mr m. 






\Y 




OS//* 






—Us —J 


*l 

— MP — 


*2 






TsV 




*5 


... . 




I ■ Imv <m 

^3ok Data in v " iid 


(((((<( 


*3 


><x> — 

nee ^ .A. 




*6 



Timing Waveform of Write Cycle No. 2 (CS Controlled) 



cs 



WE 





- 1££ JL 

< > 


t 


, tAS 


IAW 

lew 


1.. (2) 






K 7 

lor (1) 


r 




5 7 


W/////////M 




m 




XMX)(XXYX)<)(YY) 


£ Daia in Valid 


aXXXXXXX 



Doui 



High Impedance («) 



Notes: 1. A write occurs during the overlap of a low C5 and a low WE. (twP)- 

2. twR is measured from the earlier of CS or WE going high to the end of write cycle. 

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs 
must not be applied. 

4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output 
buffers remain in a high impedance state. 

5. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to 
the outputs must not be applied to them. 

6. Dout is the same phase of write data of this write cycle, if t WR is long enough. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6268 Series 



ILOW Vcc DATA RETENTION CHARACTERISTICS (O'C ^ Ta^7Q'C ) 

This characteristics guaranteed only for L-version. 



Kates) ti l.. 



•WCk Tint. 



«2. V lt -3.0V 
,3. ft.-i.OV 



Parameter 


Symbol 


Test Conditions 


min 


typ 


max 


Unit 


Vcc for Data Retention 


V», 


C52 Vcc -0.2V 
V..2 V C1 - 0.2V or 
0VSV.S0.2V 


2.0 






V 


Dau Retention Current 


/cCO» 






30 ■« 
20" 


»* 


Chip Deselect to Data Retention Time 


'CM 


See retention waveform 









ns 


Operation Recovery Time 




l»c •} 






ns 



• LOW V tc DATA RETENTION WAVEFORM 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 




ACCESS TIME VS. SUPPLY 
VOLTAGE 



ACCESS TIME VS. LOAD 
CAPACITANCE 



1.2 









7i=25 - C 











































4.75 5.0 5.25 

Supply Voltw V« (V! 




ACCESS TIME VS. 
AMBIENT TEMPERATURE 



SUPPLY CURRENT VS. 
FREQUENCY 









Vcc=5.0V 











































60 80 

Ta AC) 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 85 



INPUT LOW VOLTAGE VS. SUPPLY 
VOLTAGE 



INPUT HIGH VOLTAGE VS. SUPPLY 
VOLTAGE 



J 




5.0 5.25 
Vo^ V« «V. 



r 

| 0-9 
* na 









r«=25-c 











































4.75 5.0 5.25 

Supply VolUB V„ (V) 



OUTPUT CURRENT VS. OUTPUT 
VOLTAGE 



OUTPUT CURRENT VS. OUTPUT 
VOLTAGE 



— \ 






T«-25 - C 
V„ = 5V 




















N 






















1 2 


1 4 5 









Ta=25'C 
Vcc = 5V 











































Outpi.1 Voluge V„„ (V) 



0.2 0.4 0.6 0.8 

Vot (V) 



STANDBY CURRENT VS. AMBIENT 
TEMPERATURE 



STANDBY CURRENT VS. SUPPLY 
VOLTAGE 









Vcc=3V 
CS = 2.8V 



















1 




m 


10 


( 


z 






0.8 






I 


0.6 


| 




1 






0.4 







































CS 


-25'C 

= V CC -0.2V 











Soppi, Volu*. r« (V) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6267 Series 



16384-word x 1-bit High Speed CMOS Static RAM 



FEATURES 

High Speed: Fast Access Time 35/45/55ns (max.) 
Low Power Standby and Low Power Operation 

Standby: 0.1mW (typ.)/5/uW (typ.) (L-version), 

Operation: 200mW (typ.) 
Single 5V Supply and High Density 20 Pin Package 

Completely Static Memory No Clock or Timing Strobe 

Required 

Equal Access and Cycle Time 

Directly TTL Compatible: All Input and Output 

Capability of Battery Back Up Operation (L-version) 



ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6267P-35 
HM6267P-45 
HM6267P-55 


35ns 
45ns 
55ns 


300 mil 20 pin 
Plactic DIP 


HM6267LP-35 
HM6267LP-45 
HM6267LP-55 


35ns 
45ns 
55ns 



■ BLOCK DIAGRAM 








Menwy Arriy 



— Vcc 

— Vs. 



Column Decode 



■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Voltage on Any Pin* 1 


V T 


-0.5«2 to +7.0 


V 


Power Dissipation 


P T 


1.0 


W 


Operating Temperature 


Topr 


to +70 


°C 


Storage 
Temperature 


T stg 


-55 to +125 


"c 


Storage Temperature Under Bias 




-10 to +85 


°c 



Notes) • 1 . With respect ot V s $. 

•2. -3.5V for pulse width § 20ns. 




■ PIN ARRANGEMENT 









•■E 




"is] An 


*E 




i7|ai, 


"E 




a- 


HE 




It] An 


a>[T 




IT) A, 






TTJa. 


Uooi ("TT 




77] a. 


wtfT" 






V,, [uj 




TTJcs 



(Top View) 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . B 



■ TRUTH TABLE 



cs 


WE 


Mode 


Vcc Current 


Dout Pin 


Rel. Cycle 


H 


X 


Not selected 


1st, I S3, 


High-Z 




L 


H 


Read 


Ice 


Dout 


Reid Cycle 


L 


L 


Write 


Ice 


High-Z 


Write Cycle 



■ RECOMMENDED DC OPERATING CONDITIONS (Ta = to +70°C) 

1 1 1 1 1 



Item 


Symbol 


min 


typ 


max 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


v S s 











V 


Input Voltage 


VlH 


2.2 




6.0 


V 


VlL 


-0.5 *1 




0.8 


V 



Note) *E -3.0V for pulse width g 20ns 



■ DC AND OPERATING CHARACTERISTICS (V C c = 5V ± 10%, V ss = 0V, T a = to +70°C) 



Item 


Symbol 


Test Conditions 


HM6267-35 


HM626745/55 


Unit 


min 


ty P *> 


max 


min 


typ* 1 


max 


Input Leakage Current 


l/i/i 


C C C=5.5V, V IN =V S S to V C C 






10 






10 


MA 


Output Leakage Current 




CS=K /Hl V UT=V S S to V C C 






10 






10 


ma 


Operating Power Supply Current 


'cc 


CS=K/^,/oj/7^0mA,min. cycle 




40 


100 




40 


80 


mA 


Stand by Power Supply Current 


ISB 


CS = Vjh, min cycle 




10 


20 




10 


20 


mA 


ISB1 


CS Z V C c - 0.2V, 
0V g V IN < o.2V or 

v cc - 0.2V ^v IN 




0.02 


2 




0.02 


2 


mA 




1*1 


50*2 




\*l 


50*2 


MA 


Output Voltage 


Vol 


I L = 8mA 






0.4 






0.4 


V 


Vqh 


I OH = -4mA 


2.4 






2.4 






V 



Notes) *1. Typical limts are at Vcc = 5V > T a = 25°C and specified loading. 
*2. This characteristics is guaranteed only for L-version. 



■ CAPACITANCE (T = 25°C,/= 1MHz) 



Item 


Symbol 


typ. 


max 


Unit 


Conditions 


Input Capacitance 


ClM 




5 


pF 


V,.-0V 


Output Capacitance 


CoUT 




7 


pF 


Vo„r-0V 



Note) Hill p.r.»«i.r it ..mplcd •nd not 100% mud. 



■ AC CHARACTERISTICS (V CC = 5V ±10%, T tt = to +70°C, unless otherwise noted) 
• AC TEST CONDITIONS 
Input pulse levels: V S s to 3.0V 
Input rise and fall times: 5ns 
Input and Output timing reference levels: 1.5V 
Output load: See Figure 



Output Load A 

♦ sv 
o 



2550 : ; 



• Including scope and jig. 



Output Load B 

(for In, In. In 4 tow) 

♦ sv 



• Including scope and jig. 



HITACHI 

88 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • E 



19 • (415) 589-8300 



HM6267 Series 



• Read Cycle 



Item 


Symbol 


HM6 267-35 


HM6267^»5 


HM6267-55 


Unit 


Notes 


min 


max 


min 


max 


min 


max 


Read Cycle Time 


tRC 


35 


- 


45 


- 


55 


- 


ns 


1 


Address Access Time 


tAA 


- 


35 


- 


45 


- 


55 


ns 




Chip Select Access Time 


'ACS 




35 




45 




55 


ns 




Output Hold from Address Change 


'OH 


5 




5 




5 




ns 




Chip Selection to Output in Low Z 




tLZ 


5 




5 




5 




ns 


2,3,7 


Chip Deselectio to Output in High Z 


*HZ 





30 





30 





30 


ns 


2,3,7 


Chip Selectio to Power Up Time 


tpu 

















ns 




Chip Deselection to Power Down Time 


'PD 




20 




30 




30 


ns 





• TIMING WAVEFORM OF READ CYCLE NO. 1 4) 5 > 

'bc- 



Address 



DC 



Data Out f, re , v i° us Da,a 



'aa — 

~'OH~\ 



Data Valid 



• TIMING WAVEFORM OF READ CYCLE NO. 2 



4) 6) 



V 

cs ^ 



Data Out 



| 'L2 

High Impedance 



Vcc Supply '°- c -- 
Current {s£_ 



-<RC- 



-'acs- 



<PU 



'HZ 



Data Valid 



I 



'PD 



High Impedance 



50% 



50% 



Notes) 1. All Read Cylce timing are referenced from last valid address to the first transitioning address. 

2. At any given temperature and voltage condition, i HZ max. is less than t LZ min. both for a given device and 
from device to device. 

3. Transition is measured *500mV from steady state voltage with specified loading in Load B. 

4. WE is High for READ cycle. 

5. Device is continuously selected, CS * V, L . _ 

6. Addresses valid prior to or coincident with CS transition low. 

7. This parameter is sampled and not 100% tested. 

• Write Cycle 



Item 


Symbol 


HM6267-35 


HM6267-45 


HM6267-55 


Unit 


Notes 


min 


max 


min 


max 


min 


max 


Write Cycle Time 


'wc 


35 




45 




55 




ns 


2 


Chip Selection to End of Write 


'CW 


30 




40 




50 




ns 




Address Valid to End of Write 


( AW 


30 




40 




50 




ns 




Address Setup Time 


'as 

















ns 




Write Pulse Width 


*WP 


20 




25 




35 




ns 




Write Recovery Time 


*WR 

















ns 




Data Valid to End of Write 


'DW 


20 




25 




25 




ns 




Data Hold Time 


<DH 

















ns 




Write Enabled to Output in High Z 


*WZ 





20 





25 





25 


ns 


3,4 


Output Active from End of Write 


l OW 

















ns 


3,4 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 89 



• TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Controlled) 



cs 





( ) 

Irm 








V 


/A 




us 


UP 


lm» 






^ j 


torn U 


t 


Dan In Valid 


)( ' 

(0* 


Dili UndtdneJ 


) 

A Huh Impedance 


r 



_ 



• TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS Controlled) 

<wc 



Address 



zx 



-Us- 



es 



-'cw- 



y 



Din 



Dout 



<wp- 



'dw- 



'wr- 



X 



/////////////. 



Data in Valid 



'dh 



'»z 


High Impedance 


Data Undefined ) 





Notes) 1. If CS goes high simultaneously with WE high, the output remains in a high impedance states. 

2. All Write Cycle timings are referenced from the last valid address to the first transitions address. 

3. Transition is measured ±500mV from steady state voltage with specified loading in Load B. 

4. This parameter is sampled and not 100% tested. 



90 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6267 Series 



■ LOW V cc DATA RETENTION CHARACTERISTICS (O'C S Ta£70'C ) 

This characteristics is guaranteed only for L-version. 



Perimeter 


Symbol 


Test Conditions 


min 


typ 


max 


Unit 


Vcc for Data Retention 


v.. 


C52 Vcc-0.2V 


2 






V 


Data Retention Current 


Iccbh 


V..2Vcc-0.2V or 0VSV..S0.2V 






30" 
20' 3 


M A 


Chip Deselect to Data Retention Time 


Icon 











ns 


Operation Recovery Time 




see retention waveform 


/.c M 






ns 



Notes) * 1. iii-Reid Cycle Tim*. * 2. V, , - 3 . 0V 

«3. ft. -2.0V 



• LOW V tt DATA RETENTION WAVEFORM 

DATA RETENTION MODE 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 91 



HM6267 Series 

ACCESS TIME VS. SUPPLY VOLTAGE ACCESS TIME VS. AMBIENT TEMPERATURE 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 93 



HM6264A Series 



Maintenance Only 



8192-word x 8-bit High Speed CMOS Static RAM 



■ FEATURES 

• Low Power Standby 



Standby: O.lmW (typ.) 
10/iW (typ.) L/LL-version 
Operating: 15mW/MHz (typ. 
100ns/120ns/150ns (max.) 



Low Power Operation 

• Fast access Time 

• Single +5V Supply 

• Completely Static Memory No clock or Timing Strobe Required 

• . Equal Access and Cycle Time 

• Common Data Input and Output, Three State Output 

• Directly TTL Compatible: All Input and Output 

• Capability of Battery Back Up Operation (L-/LL-version) 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6264AP-10 


100ns 




HM6264AP-12 


120ns 




HM6264AP-15 


150ns 




HM6264ALP-10 


100ns 


oUu mil zo pin 
Plastic DIP 


HM6264ALP-12 
HM6264ALP-15 


120ns 
150ns 


HM6264ALP-10L 


100ns 




HM6264ALP-12L 


120ns 




HM6264ALP-15L 


150ns 




HM6264ASP-10 


100ns 




HM6264ASP-12 


120ns 




HM6264ASP-15 


150ns 




HM6264ALSP-10 


100ns 


300 mil 28 pin 
Plastic DIP 


HM6264ALSP-12 
HM6264ALSP-15 


120ns 
150ns 


HM6264ALSP-10L 


100ns 




HM6264ALSP-12L 


120ns 




HM6264ALSP-15L 


150ns 




HM6264AFP-10 


100ns 




HM6264AFP-12 


120ns 




HM6264AFP-15 


150ns 




HM6264ALFP-10 


100ns 


28 pin 


HM6264ALFP-12 


120ns 


Plastic SOP 


HM6264ALFP-1S 


150ns 


(Note) 


HM6264ALFP-10L 


100ns 




HM6264ALFP-12L 


120ns 




HM6264ALFP-15L 


150ns 





HA6264AP Series 




(DP-28) 



HM6264ASP Series 




(DP-28N) 



HM6264AFP Series 




(FP-28D/DA) 



■ PIN ARRANGEMENT 



Note) T is added to the end of the type no. for a SOP of 3.00 mm (max.) 
thickness. 



nc[T 




li] ccc 


A,.fJ 




27] WE 


•VE 




H)cs, 


A. (7 




2S] A, 


Ms 




24] A, 


A.[T 




23]A, , 


A,(T 




H]oe 


A,rr 




2l]A,, 


A,n 




20]CS, 


a. [To 




[5] I/O. 


i/o,[n 




T|]i/o, 


1/0,(1] 




n] 1/0. 


i/o,[n 




]S] 1/0, 


p»[j3 




15] 1/0. 



(Top View) 



HITACHI 

94 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



■ BLOCK DIAGRAM 



CSio 
C5io 



1 



Rd* 
D»cod»r 



Memorv Mainx 
256x256 



Input 
Dm 

Control 



Timing Vulse Gen. 
Column Decoder 



r3 



■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage* 1 


Vt 


-0.5* 2 to +7.0 


V 


Power Dissipation 


Pt 


1.0 


W 


Operating Temperature 


Topr 


to +70 


•c 


Storage Temperature 


Tsii 


-55 to +125 


•c 


Storage Temperature (Under Bias) 


Tbias 


-10 to +85 


°c 



Notes) *1. With respect to V ss . 

*2. -3.0V for pulse width g 50ns 

■ TRUTH TABLE 



WE 


CS, 


CS, 


OE 


Mode 


I/O Pin 


Vcc Current 


Note 


X 


H 


X 


X 


Not Selected 


High Z 


IsbJsbi 




X 


X 


L 


X 


(Power Down) 


High Z 


I SB J SB I 




H 


L 


H 


H 


Output Disabled 


High Z 


ice 




H 


L 


H 


L 


Read 


Dout 


ice 


Read Cycle 


L 


L 


H 


H 


Write 


Din 


ice 


Write Cycled) 


L 


L 


H 


L 


Din 


'cc 


Write Cycle (2) 



X : H or L 

■ RECOMMENDED DC OPERATING CONDITIONS (T a = to +70°C) 



Item 


Symbol 


in in 


lyp 


max 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


v S s 











V 


Input Voltage 


VlH 


2.2 




6.0 


V 


Vu. 


-0.3* 1 




0.8 


V 



Note) *1. -3.0V for pulse width g 50ns 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



95 



HM6264A Series 



■ DC AND OPERATING CHARACTERISTICS (V C c = 5V ± 10%, V ss = OV, T a = to +70°C) 



Item 


Symbol 


Test Condition 


min 


typ* 1 


max 


Unit 


Input Leakage Current 


lu\ 


Vh^Vss to v cc 






2 


MA 


Output Leakage Current 


(%0l 


CST= V IH or CS2= V IL or OE= V m or WE= V, L , 

Vi/o=Vss to Vcc 


— 


— 


2 


mA 


Operating Power Supply Current 


'CCDC 


CST=K/ L , CS2=V IH , 7/ /o =0mA 


- 


7 


15 


mA 


Average Operating Current 


l CCl 


Min. cycle, duty=100%, CS1=V IL , CS2= Vih 
7//O=0mA 


_ 


30 


45*5 


mA 


30 


55** 


ICC2 


Cycle time = lus, duty = 100%, If/o = OmA, 
CSl < 0.2V, CS2 > V C C -0.2V 
K/// > K C C -0.2V, K/ L § 0.2V 




3 


5 


mA 


Standby Power Supply Current 


ISB 


CSl =K 7// or CS2=K /t 


- 


1 


3 


mA 


fall 


CST^Kcc-0.2V, CS2>Kcc-0 2V or 
0V < OS2 < 0.2V, 0V <■ V ln 




0.02 


2 


mA 




2* 3 


100* J 


MA 




2*4 


50*" 


Output Voltage 


Vol 


/ £. = 21mA 






0.4 


V 


VOH 


lQH=-l 0mA 


2.4 






V 



Notes) *1. Typical limits are at K CC =5.0V, r a =2S°C and specified loading. 

♦2. V IL min=-0.3V 

*3. This characteristics is guaranteed only for L-version. 

*4. This characteristics is guaranteed only for LL-version. 

•5. For 120ns/ 150ns version. 

•6. For 100ns version. 



■ CAPACITANCE (J = I MHz, T a = 25°C) 



Item 


Symbol 


Tesi Condition 


typ 


max 


Unit 


Input Capacitance 


On 


Vin = 0V 




5 


PF 


Input/Output Capacitance 


G/O 


Vuo = OV 






pF 



Note) This parameter is sampled and not 1009! tested. 



■ AC CHARACTERISTICS (V cc = 5V±10%. Ta = to +70°C) 

• AC TEST CONDITIONS 

Input Pulse Levels: 0.8V/2.4V 

Input Rise and Fall Time: 10ns 

Input Timing Reference Level: 1.5V 

Output Timing Reference Level: 0.8V/2.0V 

Output Timing Reference Level: HM6264A-10 1.5V 

HM6264A-12/15 0.8V/2.0V 
Output Load: 1TTL Gate and Cj_ (100pF) (including scope and jig) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Item 


Symbol 


HM6264A-10 


HM6264A-12 


HM6264A-15 


Unit 


min 


max 


min 


max 


min 


max 


Read Cycle Time 


'RC 


100 


- 


120 


- 


150 


— 


ns 


Address Access Time 


'AA 


- 


100 


- 


120 




150 


— 5! 


Chip Selection to Output 


CS1 


'CO! 


- 


100 


- 


120 


- 


150 


ns 


CS2 


'C02 




100 


- 


120 




150 


ns 


Output Enable to Output Valid 


<OE 




50 




60 




70 




Chip Selection to 
Output in Low Z 


CST 


'LZ1 






10 




\ 5 






CS2 




10 




10 




15 




ns 


Output Enable to Output in Low Z 


'OLZ 


5 




5 




5 




ns 


Chip Deselection to 
Output in High Z 


CST 


'HZ1 





35 





40 





50 


ns 


CS2 


'HZ2 





35 





40 





50 


ns 


Output Disable to Output in High Z 


tOHZ 





35 





40 





50 


ns 


Output Hold from Address Change 


ton 


10 




10 




10 




ns 



to output voltage levels. 

2. At any given temperature and voltage condition, tj/z max is less than tn min both for a given device and from 
d device to device. 



• READ CYCLE 



Address 



- tRC - 



y 







CS1 



CS2 



r AA- 



'COl- 



W///////////1 



-'LZ1 

'C02- 



-'LZ2- 



OE 



\\\\\\\\\\\\\\\\\\\\\W r 



-'OE 



-'OLZ- 



X 



— 



-'HZl- 



-<HZ2- 



l OHZ- 



Dout- 



Data Valid 



Note) 1. WE is high for Read Cycle 



:>®- 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 97 



HM6264A Series 



• WRITE CYCLE 



Item 


Symbol 


HM6264A-10 


HM6264A-12 


HM6264A-15 


Unit 


min 


max 


min 


max 


min 


max 


Write Cycle Time 


'wc 


100 


- 


120 


- 


150 


- 


ns 


Chip Selection to End of Write 


tew 


80 


- 


85 


- 


100 


- 


ns 


Address Setup Time 


'AS 





- 





- 





- 


ns 


Address Valid to End of Write 


'AW 


80 


- 


85 


- 


100 


- 


ns 


Write Pulse Width 


'WP 


60 




70 




90 




ns 


Write Recovery Time 


<WR 

















ns 


Write to Output in High Z 


'WHZ 





35 





40 





50 


ns 


Data to Write Time Overlap 


<DW 


40 




40 




50 




ns 


Data Hold from Write Time 


>DH 

















ns 


Output Enable to Output in High Z 


tOHZ 





35 





40 





50 


ns 


Output Active from End of Write 


tow 


5 




5 




5 




ns 



• WRITE CYCLE 11) (OEclockl 



Address 



X 



OE 



CSl 



-twe- 



X 



////////////// 



\\\\\\\\^ 



[6] 



CS2 ' 



777777? 

v///// 



//// 



7A 



tAW 



tAS [3] 



WE- 



twp\U 



///////////A 



tOHZ I 5 1 



'DW 



'DH 



Din- 



HITACHI 

98 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6264A Series 



• WRITE CYCLE (2) (OE Low Fix) 

'WC 



Address 



CS1 



CS2 



ss 



1 



WE- 



-'AW- 



St 



tcwW 



[6] 



' / / / 
//// 



'CW [2] 



7 



5 S 



MS [3] 



'W ['I 



|5] , 



Dout- 



)))>))))))))> ^ 



>WHZ 



Din- 



'IV/? [4] 



'0// 



tow 



tDH 







(?) 



[8] 



[9] 



NOTES: 1) A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transi- 
tion among CS1 going low, CS2 goi ng h igh and WE going low. A write ends at the earliest transition among 
CS1 going high, CS2 going low and WE going high, t W p is measured from the beginning of write to the end 
of write. 

2) 'cw's measured from the later of CS1 going low or CS2 going high to the end of write. 

3) 1 as > s measured from the address valid to the beginning of write. 

4 ) 1 wr is measured from the earliest of C5l or WE going high or CS2 going low to the end of write cycle. 

5) During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs 
m ust n ot be applied. 

6) If C5I goes low simultaneously with WE going low or after WE going low, the outputs remain in high im- 
pedance state. 

7) Dout is the same phase of the latest written data in this write cycle. 

8) Dout is the read data of next address. 

9) If CST is low and CS2 is high during this period, I/O pins are in the output state. Therefore, the input ! 
of opposite phase to the outputs must not be applied to them. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 99 



HM6264A Series 



■ LOW V C c DATA RETENTION CHARACTERISTICS (T a = to +70°C) 
This characteristics is guaranteed only for L/LL-version. 



Item 


Symbol 


Test Condition 


min 


typ 


max 


Unit 


V cc for Data Retention 


Vdr 


Loif ccc~u.i-V,Laib *CC~ 0.^ * or 
CS2 ^ 0.2V 


2.0 






V 


Data RetentionCurrent 


!CCDR 


V C c = 3.0V 

CS1 >K CC -0.2V 

CS2 > V C C -0 2V or 0V^CS2g0.2V,0V<K,„ 

i 




1*' 


50*' 


ItA 




1* J 


25* J 


Chip Deselect to Data Retention 
Time 


'CDR 


See Retention Waveform 









ns 


Operation Recovery Time 


'R 


f«C» 3 






ns 



Notes) M. V IL min = -0.3V, 20/uA max at r„=0 to 40 C, This characteristics is guaranteed only for L-version. 

•2. V IL min = -0.3V, 10nA max at T a = to 40°C, This characteristics is guarnteed only for LL-version. 
* 3 - 'RC = Read Cycle Time 



• LOW Vcc DATA RETENTION WAVEFORM 111 (CS1 Controlled) 

Data Retention Mode 




CSl^cc -0.2V 




0V 



• LOW Vcc DATA RETENTION WAVEFORM (2) (CS2 Controlled) 

Data Retention Mode 




Note) In Data Retention Mode. CS2 controls the Address, WE, CST, OE and Din buffer. If CS2 controls data retention 
mode, Vin for these inputs can be in the high impedance state. If CS1 controls the data retention mode, CS2 must 
satisfy either CS2 ^V C c-0-2V or CS2 g 0.2V. The other input levels (address, WE, OE, I/O) can be in the high 
impedance state. 



HITACHI 

1 00 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



SUPPLY CURRENT VS. 
SUPPLY VOLTAGE 



SUPPLY CURRENT VS. 
AMBIENT TEMPERATURE 




SUPPLY CURRENT VS. 
FREQUENCY 




I N * in 



ACCESS TIME VS. 
LOAD CAPACITANCE 



i.i. 




in' 51 *n *« sin 

l.«M< Capaciiincv ( i |»F ' 



ACCESS TIME VS. ACCESS TIME VS. 

SUPPLY VOLTAGE AMBIENT TEMPERATURE 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



I 



Ser 



INPUT LOW VOLTAGE VS. 
SUPPLY VOLTAGE 



INPUT HIGH VOLTAGE VS. 
SUPPLY VOLTAGE 



J 0.9 

i 




(.5 1.75 



1 \"|U> 



OUTPUT CURRENT VS. 
OUTPUT VOLTAGE 



OUTPUT CURRENT VS. 
OUTPUT VOLTAGE 





IUi MM 



Owlp.l Vol!.,. Vo. (V) 



STANDBY CURRENT VS. 
AMBIENT TEMPERATURE 



































L 


1 





STANDBY CURRENT VS. 
SUPPLY VOLTAGE 




Antrim TtrnmWM tk ' t I 



Suiipts v»tte»' in 'V 



102 



# HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6288 Series 



16384- word X 4-bit High 



CMOS Static RAM 



The Hitachi HM6288 is a high speed 64k static 
RAM organized as 16-kword x 4-bit. It realizes 
high speed access time (25/35/45 ns) and low 
power consumption, employing CMOS process 
technology. 

It is most advantageous for the field where high 
speed and high density memory is required, such 
as the cache memory for main frame or 32-bit 
MPU. 

The HM6288, packaged in a 300 mil plastic DIP 
and SOJ, is available for high density mounting. 
Low power version retains the data with battery 
back up. 

■FEATURES 

• Single 5V Supply and High Density Plastic Package. 

• High Speed: Fast Access Time 25/35/45 ns (max.) 

• Low Power dissipation 

Active mode 300mW (typ.) 
Standby mode 100;uW (typ.) 

• Completely Static Memory 

No Clock or Timing Strobe Required. 

• Equal Access and Cycle Times. 

• Directly TTL Compatible - All Inputs and Outputs. 

■ ORDERING INFORMATION 




(DP-22NB) 



(CP-24D) 



IPIN ARRANGEMENT 



Type No. 


Access Time 


Package 


HM6288P-25 


25 ns 


300 mil 


HM6288P-35 


35ns 


22-pin 


HM6288LP-25 
HM6288LP-35 


25 ns 
35 ns 


Plastic DIP 
(DP-22NB) 


HM6288JP-25 
HM6288JP-35 


25ns 
35ns 


300 mil 
24-pin 

SOJ (CP-24D) 


HM6288UP-25 
HM6288UP-35 


25 ns 
35ns 



■BLOCK DIAGRAM 




HM6288P Series 



A0C 1 
Al t 2 
A2 C 3 
A3 C 4 
A4 c 5 
A5C 6 
A6 C 7 
A7 c 8 
A8C 9 
CSC 10 
VssMI 



22 3 V cc 



□ A13 

□ Al 2 
3A11 
3 A10 
3 A9 

3 l/Ol 
3 I/02 
3 1/03 
3 I/04 
3 WE 



(Top View) 



• HM6288JP Series 





24 


3 Vcc 


2 


23 


3 A13 


3 


2Z 


□ A12 


4 


21 


3 All 


5 


20 


3 A10 


6 


19 


3 A9 


7 


18 


3 NC 


8 


17 


□ 1/01 


9 


16 


3 1/02 


10 


15 


3 1/03 


11 


14 


3 1/04 


12 


13 


5 WE 


(Top View) 





Pin Description 



Pin Name 


Function 


AO - A13 


Address 


I/01-I/04 


Input/Output 


CS 


Chip Select 


WE 


Write Enable 


Vcc 


Power Supply 




Ground 



► HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



103 



I 



I ABSOLUT 



hem 


Symbol 


Rating 


Unit 


Voltage on Any Pin Relative to Vss 


Vt 


-0.5"'to +7.0 


V 


Power Dissipation 


Pr 


1.0 


W 


Operating Temperature 


T„. 


to +70 


•c 


Storage Temperature 


T... 


-55 to +125 


•c 


Temperature under Bias 


T..., 


-10 to +85 


"C 



Note: *1. Vr min.= -2.0V for pulse widthSlOns 

■TRUTH TABLE 



cs 


VvT 


Mode 


Vcc Current 


I/O Pin 


Ref. Cycle 


H 


X 


Standby 


Isa, Isbi 


High Z 




L 


H 


Read 


Ice 


Dout 


Read'Cycle 1, 2 


L 


L 


Write 


Ice 


Din 


Write Cycle 1, 2 



DC OPERATING CONDITIONS ( 7a=0 to +70°C) 



Parameter 

' 


Symbol 


min 


typ 


max 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 











V 


, 

Input High (logic 1) Voltage 


VlH 


2.2 




6.0 


V 


Input Low (logic 0) Voltage 


V U 


-0.5" 




0.8 


V 



Note: * L Vil min.= -2.0V for pulse widths 10ns 

■DC AND OPERATING CHARACTERISTICS ( 7a=0 to +70"C, Vcc = 5V+10%, Kss=0V) 



Parameter 


Symbol 


Test Condition 


min 


typ*> 


max 


Unit 


Input Leakage Current 


1 Iu 1 


Vcc = MAX. V,*=Vss to Vcc 






2.0 


«A 


Output Leakage Current 


1 Ilo 1 


CS= ViH.Vi'0= Vss to Vcc 






2.0 


<<A 


Operating Power Supply Current 


Ice 


CS= V/L,//'O = 0mA, min. cycle 




60 


120 


mA 


Standby Vcc Current 


Isa 


CS= Via, min. cycle 




15 


30 


mA 


Standby Vcc Current 1 


/ssi» 2 


CSS Vcc — 0.2V 

0VS V;*S0.2V or Vcc -0.2V S Vm 




0.02 


2.0 


mA 


/sai* 3 




0.02 


0.1 


mA 


Output Low Voltage 


Vol 


/oi = 8mA 






0.4 


V 


Output High Voltage 


Voh 


Ioa= -4.0mA 


2.4 






V 


Notes: » I. Typical limits are at Vcc-S.OV, Ta= +25'C and specified loading. 

* 2. P version 

* 3. LP version 

■CAPACITANCE ( Ta=25'C,/ = 1.0MHz) 




Parameter 


Symbol 


Test Conditions 


min 


max 


Unit 


Input Capacitance 


Ci. 


V, = 0V 




6 


pF 


Input/Output Capacitance 


Ci/o 


V//o = 0V 




8 


PF 



Note: This parameter is sampled and not 100% tested 



HITACHI 

1 04 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6288 Series 



■AC CHARACTERISTICS 

• AC Test Conditions 

Input pulse levels: OV to 3.0V 
Input rise and fall times: 5ns 



480Q 



Dout 




Input and Output timing reference levels: 1.5V 
Output load: See Figure 



4800 



r: 3o p f' 



77T 



Output Load (A) 
•Including scope & jig. 




Dout 



±:5pF' 



Output Load (B) 

7^. (for t HZ , t LZ , t wz & 



<ow) 



■ READ CYCLE 



Parameter 


Symbol 


HM6288-25 


HM6288-35 


Unit 


min 


max 


min 


max 


Read Cycle Time 


'RC 


25 




35 




ns 


Address Access Time 


'aa 




25 




35 


ns 


Chip Select Access Time 


'ACS 








35 


ns 


Output Hold from Address Change 


'OH 


3 




5 




ns 


Chip Selection to Output in Low Z 


'LZ* 


5 




5 




ns 


Chip Deselection to Output in High Z 


'HZ* 





12 





20 


ns 


Chip Selection to Power Up Time 


'PV 












ns 


Chip Seselection to Power Down Time 


tpD 




25 




30 


ns 



* Transition is measured ± 20OmV from steady stale voltage with Load(B). 
This parameter is sampled and not 100"o tested 



• Timing Waveform of Read < 



iNo.1 



[1][2] 









> 


^ > 


< 














Previous \ 
Data Valid / 


(XXXXX) 


^ Data Valid ^ 





• Timing Waveform of Read Cycle No.2 [1] [31 



V'rc supply 





t«c 


/ 

tllZ 




tu 






1 


1 




/ Data Valid 


) 




High Impedaii 








/ Hudi 

Impedance 

\ 


Ice J 


/ 50% 50% \ 



Notes: 1 WE is HiRh for Read Cycle. 

2. Device is continuously selected. CS= Vil. 

3 Address Valid prior to or coincident with CS transition Low 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



105 



■ WRITE CYCLE 



Parameter 


Symbol 


HM6 288-25 


HM6288-35 


Unit 


min 


max 


min 


max 


Write Cycle Time 


*WC 


25 




35 




ns 


Chip Selection to End of Write 


'cw 


20 




30 




ns 


Address Valid to End of Write 


'aw 


20 


- 


30 


- 


ns 


Address Setup Time 


Us 












ns 


Write Pulse Width 


*WP 


20 




30 




ns 


Write Recovery Time 


f WR 












ns 


Date Valid to End of Write 


'dw 


12 




20 




ns 


Data Hold Time 














ns 


Write Enabled to Output in High Z 


>wz* 





8 





10 


ns 


Output Active from End of Write 


>ow 


5 




5 




ns 



This parameter is sampled and not 10A" & tested. 

• Timing Waveform of Write Cycle No.1 (WE Controlled) 



x 







)C 



(((((((( 



^£2 



7 



i- '°* >5 .i 



HITACHI 

1 06 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Timing Waveform of Write Cycle No.2 (CS Controlled) 



-HM6288 Series 



X 



X 



X 



XXXXXXXXXXX)X 



High Impedance ♦ 4 



Notes) 1. A write occurs during the overlap ofa lo w CS and a low WE. (twr) 

2. twR is measured from the earlier of CS or WE going high to the end of write cycle. 

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the 
outputsmust not be applied. 

4. If the CS low transition occurs simultaneously with the WE low transition or after the WE 
transition, the output buffers remain in a high impedance state. 

5. If CS is low during this period, I/O pins are in the output state after tow. Then the data input 
of opposite phase to the outputs must not be applied to them. 

6. Dout is the same phase of write data of this write cycle, if Iwr is long enough. 



• Low Vcc Data Retention Characteristics ( 7a = to +70°C) 
( This Characteristics is guaranteed only for L-version. ) 



Parameter 


Symbol 


Min 


Typ 


Max 


Unit 


Test Conditions 


Vcc for data retention 


Vol 


2.0 






V 


CSS Vcc -0.2V 
V„ 2 Vcc -0.2V or 
0VS V.S0.2V 


Data retention current 


ICCDR 






50 2 ' 
35 3 ' 


Ml 


Chip deselect to data 
retention time 


tCDR 









ns 


See retention waveform 


Operation recovery time 


rs 




tic" 






ns 


NOTE: I./Kc-Read cycle time 

2. Vcc = 3.0V 

3. Vcc = 2.0V 





Low Vcc Data Retention Waveform 



cs- 




Data Retention Mode 



— ^= 




HITACHI 



19 • 



107 



HM6288 Series 



SUPPLY CURRENT VS. SUPPLY VOLTAGE 



SUPPLY CURRENT VS. AMBIENT TEMPERATURE 



1.4 



1.2 



0.8 



0.4 



4.5 



4.75 5.0 5.25 

Supply Voltage Vcc (V) 



l.b 



I 1.2 



5.5 









V C c — 50V 











































20 40 60 80 

Ambient Temperature Ta (*C> 



ACCESS TIME VS. SUPPLY VOLTAGE 



ACCESS TIME VS. LOAD CAPACITANCE 



1.2 
11 
1.0 
0.9 
0.8 
0.7 









Ta=25'C 











































45 



4.75 5.0 5.25 

Supply Voltage Vcc (VI 



5.5 



1 16 



0.8 

0.6 



50 



100 150 

C L (pFl 



200 



ACCESS TIME VS. AMBIENT 



TEMPERATURE 



1.3 



1,1 



0.9 
0.8 



0.7 









V cc = 5.0V 











































SUPPLY CURRENT VS. FREQUENCY 

100 50 33 



20 40 60 

Ambient Temperature Ta (*C) 



80 



1 
5 



0.9 

0.8 



06 

0.5 































































10 20 3 


4 


5 



Frequency t (MHz) 



108 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6288 Series 






STANDBY CURRENT VS. INPUT VOLTAGE 




HITACHI 

1 1 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 58*8300 



HM6788 Series 



16384-word x 4-bit High Speed Hi-BiCMOS Static RAM 
■FEATURES 

• Super Fast Access Time : 25/30ns (max.) 

• Low power Operation 

Operating: 230mW (typ), Standby: 10mW (typ) 

• +5V Single Supply 

• Completely Static Memory - 

No Clock or Timing Strobe required 

• Balanced Read and Write Cycle Time 

• Fully TTL compatible Input and Output 



Maintenance Only 



■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6788P-25 


25ns 


300 mil 22 pin 


HM6788P-30 


30ns 


Plastic DIP 









■BLOCK DIAGRAM 





(Top View) 



■absolute maximum ratings 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage to Vss pin 


Vt 


-0.5 to +7.0 


V 


Power Dissipation 


Pt 


1.0 


W 


Operating Temperature 


T.„ 


to + 70 


•c 


Storage Temperature (with bias) 


T,.,(bias) 


-lOto +85 


•c 


Storage Temperature 


T.„ 


-55 to +125 


•c 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 1 1 



■truth table 



cs 


WE 


Mode 


Vcc Current 


Output Pin 


Ref. Cycle 


H 


X 


Not selected 


IsB, /SSI 


HighZ 




L 


H 


Read 


Ice, Icci 


Dout 


Read Cycle (1) (2) 


L 


L 


Write 


Ice, Icc\ 


Din 


Write Cycle (1) (2) 



RECOMMENDED DC OPERATING CONDITIONS (P C g Tag 70'C) 





Item 


Symbol 


min 


typ 


max 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 











V 


Input High Voltage 


V,H 


2.2 




6.0 


V 


Input Low Voltage 


V,L 


-0.5" 




0.8 


V 



-MV with 20ns p 



AND OPERATING CHARACTERISTICS ( Vfcc = 5V ± 10%, 7a=0'C to +70"C) 



Item 


Symbol 


Test Conditions 


min 


typ 


max 


Unit 


Input Leakage Current 


\lu\ 


Vcc = 5.5V, Vih= Vss to Vcc 






2 


uA 


Output Leakage Current 


\Ilo\ 


CS= Vih. V,/o= Vss to Vcc 






2 


fA 


Opearating Power Supply Current 


Ice 


CS= Vil, /;/ D =0mA 






80 


mA 


Average Operating Current 


Ice, 


Min. Cycle, Duty: 100% 






120 


mA 


Standby Power Supply Current 


Isa 


CS= Vm 






30 


mA 


Isa, 


CSi Vrr-0.2V. V K S0.2Vor Visi V cr -0.2V 






10 


mA 


Output Low Voltage 


Vol 


/<>;. = 8mA 






0.5 


V 


Output High Voltage 


V„h 


/oh = -4mA 


2.4 






V 



■AC CHARACTERISTICS (Vcc = 5V +10%, T. = to +70°C, unless ot 
► AC Test Conditions 



Input pulse levels: Vss to 3.0V 
Input rise and fall time: 4ns 



Input and Output reference levels: 1.5V 
Output Load: See Figure 



m 

Output Load A 



Q +5V 



] ; m& 



Output Load B 
CCHZ. 'WHZ. tCLZ. IOW) 



0HITACHI 

1 1 2 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • E 



589-8300 



HM6788 Series 



•READ CYCLE 



Notes) * t. This parameter is sampled and not 100% tested. 

* 2. Transition is measured ±200mV form steady slate voltage with Load IB). This parameter is sampled and not 100% tested 
*3. If tr becomes more than 150ns, there is possibility of function fail, 
please contact your ncaresl Hitachi Sales Dept. regarding spec i Ileal ion. 

• Timing waveform of Read Cycle No. 1 1,2 

'M 



— 



!),„„ Previous data Valid 




Data Valid 



i " - 1 

XX 



Item 


Symbol 


HM6788-25 


HM6788-30 


Unit 


min 


max 


min 


max 


Read Cycle Time 


toe 


25 


- 


30 


— 


ns 


Address Access Time 


t AA 




25 


— 


30 


ns 


Chip Select Access Time 


tACS 




25 


- 


30 


ns 


Chip Selection to Output in Low Z 


tciz' 2 












ns 


Chip Deselection to Output in High Z 


tCHZ' 2 





10 





12 


ns 


Output Hold from Address Change 


tOH 


5 




5 




ns 


Chip Selection to Power Up Time*' 


tpv 












ns 


Chip Deselection to Power Down Time* 1 


tFD 




20 




30 


ns 


Input Voltage Rise/Fall Time* 3 


it 




150 




150 


ns 




• Timing waveform of Read Cycle No. 2 

cs 



High Impedanc 



^(XXa 



Data Valid 



High Impedance 



Note) "J.. WE= Vffl 

*2. CS=K/ L _ 

•3. Address valid prior to or coincident with CS transition Low. 



• WRITE CYCLE 



Item 


Symbol 


HM6788-25 


HM6788-30 


Unit 


min 


max 


min 


max 


Write Cycle Time 


twe 


25 




30 




ns 


Chip Selection to End of Write 


tew 


20 




25 




ns 


Address Setup Time 


tAS 












ns 


Address Valid to End of Write 


Iaw 


20 




25 




ns 


Write Pulse Width 


twp 


20 




25 




ns 


Write Recovery Time 


twR 












ns 


Write to Output in High Z 


twHZ * ' 





10 





12 


ns 


Data Valid to End of Write 


tow 


15 




15 




ns 


Data Hold Time 


row 


5 




5 




ns 


Output Active from End of Write 


tow" 












ns 



* t Transition is measured i200mV from steady state voltage with Lood(B). 
This parameter is sampled and not 100% tested. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



113 



HM6788 Series 



• Timing waveform of Write Cycle No. 1 (WE Controlled) 



i 



WE 



Wv 



High Impedance 



/ 



©6 



Data Valid 



High Impedance 



• Timing waveform of Write Cycle No. 2 (CS Controlled) 



WE 



) 


\ 7 


( 




US 


tew 










I 7 


I 

• ti 






l AW 

IWP 


tWR 


WW 


\\\ ) 


¥////// 









High Impeda 



High Impedance 



Data Valid 



Notes) * 1 . A write occurs during the overlap (t^/p) of a low CS and a low WE. 

*2. During this period, I/O pins are in the output state so that the input signals of 

opposite phase to the outputs must not be applied. 
*3. Dout isjhe same phase of write data of this write cycle. 

*4. If the CS low transition occurs after the WE low transition, output remain in a 

high impedance state. 
*5. If CS is low during this period, I/O pins are in the output state. Then, the data 

input signals of opposite phase to the outputs must not be applied to them. 
*6. t WR is measured from the earlier of CS or WE going high to the end of write cycle 
ICAPACITANCE ( r a =25'C,/=1.0MHz) 



Item 


Symbol 


min 


typ 


max 


Conditions 


Input Capacitance 


t'l.V 






6.0 


Vi.v = 0V 


Input Output Capacitance 


Cilo 






8.0 


Voir-W 


Note) This parameter is sampled and nut 100% tested. 

114 Hitachi America, Ltd. • Hitac 


hi Plaza • 2 


HITACHI 

000 Sierra Point Pkwy. • Brisbane, C 


A 94005-1819 • (4 





HM6788H Series 



16384-word x 4-bit High Speed Hi BiCMOS Static RAM 



Features 

• Super Fast Access Time : 15/20ns (max.) 

• Low power Operation 
Operating: 280mW (typ) 

• +5V Single Supply 

• Completely Static Memory - 

No Clock or Timing Strobe required 

• Equal Access and Cycle Times 

• Fully TTL compatible Input and Output 




Ordering Information 



Type No. 




Access Time 


Package 




HM6788HP-15 




15ns 


300 mil 22 pin 




HM6788HP-20 




20ns 


Plastic DIP 















Block Diagram 











A 4 o— 
A s o- 



I/Oi °- 
I/0 2 o- 
I/0 3 o- 
VOt o. 



cs< 




Pin Arrangement 









,v,|T 




if}*,. 


.*rr 




»]a.i 


A 'E 




_js] A " 






|iT|Aia 


A 'E 




77] Ai 






]7|i/0i 


^£ 




7sjl/0i 


A«jT 




77Ji/o. 






jsji/o. 


v ss rjr 




71] we 




(Top View) 





Absolute Maximum Ratings 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage to Vss pin 


Vt 


-0.5 to +7.0 


V 


Power Dissipation 


Pt 


1.0 


1 W 


Operating Temperature 


T„, 


Oto +70 


•c 


Storage Temperature (with bias) 


T,„(bias) 


-10 to +85 


■c 


Storage Temperature 


T.„ 


-55 to +125 


•c 



Note) The specifications of this device are subject to change without notice. 
Please contact Hitachi's Sales Dept. regarding specifications. 



HITACHI 



115 



HM6788H Series 

Truth Table 

CS WE 



H x Not selected Isb, Isb\ High Z 



L H 


Read 


Ice, Icci 


Data Out 


Read Cycle (1), (2) 


L L 


Write 


Ice, Icci 


Data In 


Write Cycle (1), (2) 


X:HorL 












Recommended DC Operating Conditions (O'C £ Ta £ 70'C) 








Item 


Symbol 


min typ max 


Unit 






Supply Voltage 


Vcc 


4.5 5.0 5.5 


XT 






Vss 











Input High Voltage 


V,H 


2.2 6.0 


V 






Input Low Voltage 


V,L 


-0.5* 1 - 0.8 


V 






Note) *1. -3.0V with 10ns pulse width. 










DC and Operating Characteristics ( Vcc 


= 5V + 10%, Ta=0"Cto + 70'C 


) 






Item 


Symbol 


Test Conditions 


min 


typ 


max Unit 


Input Leakage Current 


l/ol 


Vcc = 5.5V. V,»=Vss to Vcc 






2 *iA 


Output Leakage Current 


I/1.0 1 


CS= V, H . V;/o = Vss to Vcc 






10 uA 


Opearating Power Supply Current 


Ice 


CS= Kn../;/o = 0mA 






100 mA 


Average Operating Current 


Icc\ 


Min. Cycle. Duty: 100% Il/O = 0mA 






120 mA 


Standby Power Supply Current 


Isb 


CS= Vib 








30 mA 


Ism 


CSi Vcc -0.2V. Vi«S0.2V or V/.vi Vcc -0.2V 




10 mA 


Output Low Voltage 


Vol 


/oi = 8mA 






0.4 V 


Output High Voltage 


Voh 


Ioh- -4mA 


2.4 




V 



AC Characteristics ( Vcc = 5V ±10%, T, = to +70°C, unless otherwise noted) 

• AC Test Conditions 

Input pulse levels: Vss t0 3.0V Input and Output reference levels: 1.6V 

Input rise and fall time: 4ns Output Load: See Figure 



+ SV 

O 



Output 
O — 



fir 



Output Load A 



I/O Pin 



Ref. Cycle 



Q+5V 



Output 
O— 



m 

Output Load B 

('HZ. 'LZ. 'WZ. >OW) 



HITACHI 

1 1 6 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6788H Series 



Read Cycle 



Item 


Symbol ■ 


HM6788H-15 


HM6788H-20 


- Unit 




■Jote 


min 


max 


min 


max 








Read Cycle Time 


l RC 


15 




20 






ns 






Address Access Time 


*AA 




15 




20 


ns 






Chip Select Access Time 


'ACS 




15 




20 


ns 






Chip Selection to Output in Low Z 


>LZ 


3 




3 




ns 


1.2 


Chip Deselection to Output in High Z 


>HZ 





6 





8 


ns 


1.2 


Output Hold from Address Change 


'OH 


3 




3 




ns 







— 

Note) *1 . This parameter is sampled and not 100% tested. 

*2. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

• Timing waveform of Read Cycle No. 1* 1 '* 2 





>RC 






Address - 


r : - ) 






'aa 






Data Out Previous Data Valid 7rY)w 







• Timing waveform of Read Cycle No. 2* 1 '* 3 



CS 



Data Out 



- f RC- 



7 



'ACS 



'LZ 



High Impedance 




'HZ 



Data Valid 



High 



Impedance 



Note) *1. WE= Vjh 
*2. CS= V IL 

*3. Address valid prior to or coincident with CS transition Low. 



Symbol 



HM6788H-15 



HM6788H-20 



min 



min 



Unit 



>Jote 



Write Cycle Time 


'wc 


15 




20 


ns 





Chip Selection to End of Write 


<cw 


10 




15 


ns 




Address Setup Time 


'AS 










ns 




Address Valid to End of Write 


Uw 


10 




15 


ns 




Write Pulse Width 


<WP 


10 




15 


ns 




Write Recovery Time 


{ WR 


1 




1 


ns 




Write Enable to Output in High Z 


'wz 





6 


8 


ns 


3,4 


Data Valid to End of Write 




9 




10 


ns 




Data Hold Time 












ns 




Output Active from End of Write 


'ow 










ns 


3,4 



Note) 1 . If CS goes high simultaneously with WE high, the output remains in a high impedance state. 

2. All Write Cycle timings are referenced from the last valid address to the first transitioning address. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

4. This parameter is sampled and not 100% tested. 



Hitachi America, Li 



HITACHI 



Brisbane, CA 94005-1819 • (415) 589-8300 



117 



• Timing waveform of Write Cycle No. 1 (WE Controlled) 



Address 



CS 



IDC 



• twc 



■ tew 



zZZZZZZZZZ 



t A S •» 



tAW 



WE 



Data In 



Data Out 



High Impedance 



• t W p*l 



*"«-t W R*2-» 



High Impedance 




• Timing waveform of Write Cycle No. 2 (CS Controlled) 



Address 



■ twc 



tAS ■ 



• tAW ■ 



" \\\\\\\\\\ 



■* tew 



*i — ► 



Data In 



Data Out 



tDW 



twR* 2 ■ 



innumi 



Data Valid 



| tPH > . 

D TOXXX 



High Impedance *4 



Note)*l. A write occurs during the overlap of a low CS and a low WE. (twp) 

*2. twR is measured from the earlier of CS or WE going high to the end of write cycle. 

•3. During this period, I/O pins are in the output state so that the input signals of opposite 
phase to the outputs must not be applied. 

*4. If the CS low transition occurs simultaneously with the WE low transition or after the 
WE transition, the output buffers remain in a high impedance state. 

•5. If CS is low during this period, I/O pins are in the output state. Then the data input 
signals of opposite phase to the outputs must not be applied to them. 

•6. Data Out is the same phase of write data of this write cycle. 



Capacitance (ra=25*C,/=i.0MHz) 



Item 




Symbol min 


typ 


max 


Conditions 


Input Capacitance 





C» 




6.0 


f;* = 0V 


Input/Output Capacitance 




Ci/o 




10 


K//O = 0V 



Note) Thi« pinmeter is sampled and not 1 00*„ tested. 

1 1 8 Hitachi America, Ltd. • Hitachi Plaza • 



<g> HITACHI 

2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6788HA Series — Preliminary 

16384-Word x 4-Bit High Speed Static RAM 

■ FEATURES 

• Super Fast 

Access Time 12/15/20ns (max.) 

• +5V Single Supply 

• Low Power Dissipation 

(DC) Operating 300mW (typ.) 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Fully TTL Compatible— All Inputs and Outputs 

■ ORDERING INFORMATION 




Type No. 


Access Time 


Package 


HM6788HAP-12 


12ns 


300 mil 22 pin 


HM6788HAP-15 


15ns 


Plastic DIP 


HM6788HAP-20 


20ns 





■ BLOCK DIAGRAM 



Ag o- 



A 7 o- 
A6 o 
A 5 o- 
A4 o- 
A3 o 
A2 O 

I/O,o 

1/020 
I/03O 
l/cuo 



CSc. 
WEo- 



■ PIN ARRANGEMENT 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 1 9 



HM6788HA Series 



ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Voltage on Any Pin Relative to V ss 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


Pt 


1.0 


W 


Operating Temperature 


Topr 


to +70 


°C 


Storage Temperature 


T sts 


-55 to + 125 


°C 


Temperature Under Bias 




-10 to +85 


°C 



RECOMMENDED DC OPERATING CONDITIONS (0°C < T a s 70°C) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 


0.0 


0.0 


0.0 


V 


Input High (Logic 1) Voltage 


V,H 


2.2 




6.0 


V 


Input Low (Logic 0) Voltage 


V IL 


-3.0* 




0.8 


V 



♦Pulse width < 10ns, DC: -0.5V 



TRUTH TABLE 



cs 


WE 


Mode 


V C c Current 


I/O Pin 


Ref. Cycle 


H 


X 


Not Selected 


•sb. Isbi 


High Z 




L 


H 


Read 


fee. Icci 


Data Out 


Read Cycle (1), (2) 


L 


L 


Write 


Ice !cci 


Data In 


Write Cycle (1), (2) 



DC AND OPERATING CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, V ss = 0V) 



Item 


Symbol 


Test Condition 


Min. 


Typ. 


Max. 


Unit 


Input Leakage Current 


UliI 


V cc = 5.5V, V IN = V ss to V cc 






2 


«A 


Output Leakage Current 


HloI 


CS = V IH , V I/0 = V ss to V cc 






10 


MA 


Operating Power Supply Current 


l cc 


CS = Vn,, I I/0 , = 0mA 






100 


mA 


Average Operating Current 


'cci 


Min. Cycle Duty: 100% I I/0 = 0mA 






120 


mA 


Standby Power Supply Current 


'.SB 


cs = V,„ 






30 


mA 


Standby Power Supply Current (1) 


ISBI 


CS > V cc - 0.2V 

V IN < 0.2V or V IN > V cc " 0.2V 






10 


mA 


Output Low Voltage 


Vol 


I l = 8mA 






0.4 


V 


Output High Voltage 


V OH 


Iqh = -4mA 


2.4 






V 



■ AC TEST CONDITIONS 

• Input Pulse Levels: V ss to 3.0V 

• Input Timing Reference Levels: 1.5V 

• Output Load: See Figure 



• Input Rise and Fall Times: 4ns 

• Output Reference Levels: 1.5V 



Dout 

o- 



255 fi 




Dout 



30 pF* 



i5fi L 



255 Q 




Output Load A 



Output Load B 
(for 'hz- 'lz- t WZ - & tow) 



♦Including scope and jig capacitance. 



HITACHI 

1 20 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



— HM6788HA Series 

■ CAPACITANCE (T a = 25°C, f = 1.0MHz) 



Item 


Symbol 


Max. 


Unit 


Conditions 


Input Capacitance 




6.0 


pF 


V IN = OV 


Input/Output Capacitance 


C I/0 


10.0 


pF 


V,/o = ov 



NOTE: This parameter is sampled ; 



■ AC CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, unless otherwise noted.) 
• Read Cycle 



Item 


Symbol 


HM6788HA-12 


HM6788HA-15 


HM6788HA-20 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


f RC 


12 




15 




20 




ns 


_ 


Address Access Time 


Ua 




12 




15 




20 


ns 


_ 


Chip Select Access Time 


Ucs 




12 




15 




20 


ns 


_ " 


Output Hold from Address Change 


tOH 


4 




4 




4 




ns 




Chip Selection to Output in Low Z 


«LZ 


3 




5 




5 




ns 


1,2 


Chip Deselection to Output in High Z 


l HZ 





6 





6 





8 


ns 


1,2 


NOTES: 1 . This parameter is sampled and not 100% tested. 
















2. Transition is measured ±200r 


nV from steady state 


voltage with specifi 


ed loading in Load B. 






• Write Cycle 




















Item 


Symbol 


HM6788HA-12 


HM6788HA-15 


HM6788HA-20 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


'wc 


12 




15 




20 




ns 


2 


Chip Selection to End of Write 


tew 


8 




10 




15 




ns 




Address Valid to End of Write 


l AW 


8 




10 




15 




ns 




Address Setup Time 


'as 

















ns 




Write Pulse Width 


l wp 


8 




10 




15 




ns 




Write Recovery Time 


•WR 

















ns 




Data Valid to End of Write 


l DW 


6 




7 




10 




ns 




Data Hold Time 


l DH 

















ns 




Write Enable to Output in High Z 


l WZ 





6 





6 





8 


ns 


3,4 


Output Active from End of Write 


•ow 


3 




3 




3 




ns 


3,4 



NOTES: 1 . If CS goes high simultaneously with WE high, the output remains in a high impedance state. 

2. All write cycle timings are referenced from the last valid address to the first transitioning address. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

4. This parameter is sampled and not 100% tested. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 21 



I 



HM6788HA Series 



■ TIMING WAVEFORM 
• Read Cycle (1)0) (2) 



Address 



tRC 



X 







tAA 



tOH 



Data Out Previous DataValkT^) (XXXX) ( Data Valid > ( 



tOH 



Read Cycle (2) OH 



CS 



Data Out 



X 



Ucs 



— 



■* — 



— 



High Impedence 



tHZ 



Data Valid 



High 

Impedence 



NOTES: 



1 . WE is High for READ cycle. 

2. Device is continuously selected, CS = Vil 

3. Address valid prior to or coincident with CS transition low. 



HITACHI 

1 22 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Write Cycle (1) (WE Controlled) 



Address 



CS 



twc 



X 



X 



tew 



WE 



Data In 



tAS 



Uw_ 



//////////////A 



High Impedance 



t W P(1) 



<X 



tDW 



tWR(2). 



z 



tDH(5) 



Data Valid 



twz(3) 



t0W (5) 



Data Out 



• Write Cycle (2) (CS Controlled) 



High Impedance 



High Impedance 



tOH (6) 



Address 



CS 



twe 



x 



tAS 







tew 



WE 



twp(i) 



y 



tWR(2) 



_ 



D-m xxxxxxxxxxxxxxm mk oatavand ^k xxxxxxxxx 

High Impedance (4) 



tow 



///////////////, 



Data Out 



NOTES: 1 . A write occurs during the overlap of a low CS and a low WE (twp). 

2. twR is measured from the earlier of CS or WE going high to the end of write cycle. 

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not 
be applied. 

4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output 
buffers remain in a high impedance state. 

5. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the 
outputs must not be applied to them. 

6. D 01 ,i is the same phase of write data of this write cycle. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 23 



HM6289 Series 



16384-Word x 4-Bit High Speed CMOS Static RAM (with OE) 

The Hitachi HM6289 is a high speed 64k static RAM organized 
as 1 6-kword x 4-bit. It realizes high speed access time (25/35/45 ns) 
and lowpowerconsumption, employing CMOS process technology. 

It is most advantageous for the field where high speed and high 
density memory is required, such as the cache memory for main 
frame or 32-bit MPU. 

The HM6289, packaged in a 300-mil SOJ, is available for high 
density mounting. Low power version ret 
back up. 

Features 

• Highspeed 

Access time: 25/35 ns (max) 

• High density 24-pin SOJ package 

• Low power 

Active mode: 300 mW (typ) 

Standby mode: 1 00 u.W (typ) 

• Single 5 V supply 

• Completely static memory 

No clock or timing strobe required 

• Equal access and cycle times 

• Directly TTL compatible: All inputs and outputs 



Pin Arrangement 



Ordering Information 



Type No. 



Access Time 



HM6289JP-25 
HM6289JP-35 



25 ns 
35 ns 



HM6289UP-25 
HM6289UP-35 



25 ns 
35 ns 



300-mil 

24-pin 

SOJ 

(CP-24D) 




Pin Description 



Pin Name 


Function 


A0-A13 


Address 


I/01-I/04 


Input/output 


CS 


Chip select 


OE 


Output enable 


WE 


Write enable 


Vcc 


Power supply 


Vss Ground 



Block Diagram 



A2 O- 
A3 0- 



A< O- 



A7 



1/01 O- 



1/02 O- 



1/03 O- 



I/04O- 



WEO- 



-&: 



ir 



Input 
D»u 

Control 



128X512 



Column Decoder 



' Vcc 



All A12 A13 A9 A10 AO Al 




HITACHI 

124 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



— HM6289 Series 

Function Table 



CS OE WE Mode 


Vcc Current 


I/O pin 




Ref. Cycle 


H X X Not selected 


Isb, Isbi 


High-Z 






L L H Read 


Ice 




Dout 




Read cycle (l)-(3) 


L H L Write 


Ice 




Din 




Write cycle (l)-(2) 


L L L Write 


Ice 




Din 




Write cycle (3)-(6) 


Note: x; H or L 

Absolute Maximum Ratings 


Item 


Symbol 




Value 


Unit 


Voltage on any pin relative to Vss 


Vi„ 




-0.5 M to+7.0 


V 


Power dissipation 


Pt 




1.0 




W 


Operating temperature range 


Topr 




to +70 


°C 


Storage temperature range 


Tst g 




-55 to +125 


°C 


Storage temperature range under bias 


Tbia, 




-10 to - 


^85 


°C 


Note: *1. Vin mirt =-2.0 V for pulse width < 10 ns. 










Recommended DC Operating Conditions (Ta = 


to +70°C) 






Item Symbol 


Min 




Typ 




Max Unit 


Supply voltage Vcc 


4.5 




5.0 




5.5 V 


Vss 












V 


Input high (logic 1 ) voltage Vm 


2.2 








6.0 V 


Input low (logic 0) voltage Vil 


-0.5" 








0.8 V 


Note: *1. Vtt. min = -2.0 V for pulse width < 10 ns. 










DC Characteristics (Ta = to +70°C, Vcc = 5 V + 10%, Vss = V) 




Item 


Symbol Min 


w 


1 Max 


Unit 


Test Conditions 


Input leakage current 


Ikil — 




2.0 


uA 


Vcc = Max 
Vin = 0V to Vcc 


Output leakage current 


IIloI — 




2.0 


HA 


CS = Vih 

Vi/o = V to Vcc 


Operating Vcc current 


Ice 


60 


120 


mA 


CS = Vil, Ii/o = mA, 
Min. cycle 


Standby Vcc current 


Isb — 


15 


30 


mA 


CS = Vm, Min. cycle 


Standby Vcc current (1 ) 


Isbi* 2 — 


0.02 


2.0 


mA 


CS > Vcc - 0.2 V 




ISBI* 3 


0.02 


0.1 


mA 


0V < Vin < 0.2 V or 
Vcc - 0.2 V< Vin 


Output low voltage 


Vol — 




0.4 


V 


Iol = 8 mA 


Output high voltage 


Voh 2.4 






V 


Ion = -4.0 mA 


Notes: *1. Typical limits are at Vcc= 5.0 V, Ta = +25°C and specified loading. 
*2. P-version 
*3. LP-version 






Capacitance (Ta = 25°C, f = 1MHz) 












Item Symbol 


Min 


Typ 


Max 




Unit Test Conditions 


Input capacitance Cin 






6 




pF Vin = V 


Input/output capacitance Cvo 






8 




pF V I/O = V 



Note: This parameter is sampled and not 100% tested. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 25 



HM6289 Series 



AC Characteristics (Ta = to +70°C, Vcc = 5 V ± 10%, unless otherwise noted.) 
Test Conditions 

Input pulse levels: Vss to 3.0 V 

Input rise and fall times: 5 ns 

Input and output timing reference le.vels: 1 .5 V 
Output load: See figures 



Douto- 



2550 




Output Load (B) 

(for ICI1Z, ICLZ, tOHZ, tOLZ, 1WIC& low) 

> + 5V 



Dout O- 



25505 




ing scope & jig. 



Read Cycle 



Item 


Symbol 


HM6289-25 


HM6289-35 


Unit 


Min 


Max 


Min 


Max 


Read cycle time 


tRC 






35 




ns 


Address access time 


tAA 




25 




35 


ns 


Chip select access time 


tACS 




25 




35 


ns 


Chip selection to output in low-Z 


tCLZ* 1 


5 




5 




ns 


Output enable to output valid 


tOE 




12 




15 


ns 


Output enable to output in low-Z 


tOLZ -1 












ns 


Chip deselection to output in high-Z 


tCHZ*' 





12 





20 


ns 


Chis disable to output in high-Z 


tOHZ*' 





10 





10 


ns 


Output hold from address change 


tOH 


3 




5 




ns 


Chip selection to power up time 


tPU 












ns 


Chip deselection to power down time 


tPD 




25 




30 


ns 



Note: *1. Output transition is measured +200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% 



tested. 



HITACHI 

1 26 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6289 Series 




Read Timing Waveform (2) 1 * 2 ' 4 




Read Timing Waveform (3) "**»••« 




Notes: * 1 . WE is high for read cycle. 

*2. Device is continuously selected, C 
*3. Address valid prior to or coincider 


S = VlL_ 

t with CS transition low. 












*4. OE = Vil. 
















Write Cycle 


















Item S 




HM6289-25 


HM6289-35 






vmbol — 


Min 


Max 


Min 


Max 


Unit 




Write cycle time 


twc 


25 




35 




ns 




Chip selection to end of write 


tew 


20 




30 


— 


ns 




Address valid to end of write 


tAW 


20 




30 




ns 




Address setup time 


Us 












ns 




Write pulse width 


tWP 


20 




30 




ns 




Write recovery time 


tWR 












ns 




Output disable to output in high-Z*' 


tOHZ 





10 





10 


ns 




Write to output in high-Z* 1 


tWHZ 





8 





10 


ns 




Data to write time overlap 


tow 


12 




20 




ns 




Data hold from write time 


tDH 












ns 




Output active from end of write* 1 


tow 


5 




5 




ns 





Note: *1. Output transition is measured ± 200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% 



HITACHI 

• 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 



127 



Write Timing Waveform (1) (OE = High, WE = Controlled) 




Write Timing Waveform (2) (OE = High, CS = Controlled) 



> 


■ 

( ) 


( 












"W > 


I 






WWW* } 


VXXXXX/ 








XXXXXXXX X 


:xxxx> 



HITACHI 

1 28 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Write Timing Waveform (3) (OE = Clocked, WE = Controlled) 



HM6289 Series 



X 



7 



J 



Din 



7 



Write Timing Waveform (4) (OE = Clocked, CS = Controlled) 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 29 



HM6289 Series 



Write Timing Waveform (5) (OE = Low, WE = Controlled) 



s 
/ 




< 












XXX 




i 7 


V/ 


7//// 




_ »« 






s 


AH J 


r 

~ ^ -J 






-H^H/— ^/rr 


)>)}))/) 

in* 

\/( Din Valid 




P 



Write Timing Waveform (6) (OE = Low, Us = Controlled) 



) 


t ) 


( 














\ 


X ? 


i 

In 






WW 


kV 


Iwr* I 

v > 


V////// 




tcu 








' •! ^ High ImpcdMOf 
-I '» 








— <x ~ i 


:xxxx> 



Notes: *1 A write occurs during the overlap of a low CS and a low WE. (twp) 

*2. tWR is measured from the earlier of CS or WE going high to the end of write cycle. 

*3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 
*4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain 
in a high impedance state. 

*5. If CS is low during this period, I/O pins are in the output state after tow. Then the data input signals of opposite phase to the 

outputs must not be applied to them. 
*6. Pout is the same phase of write data of this write cycle, if tWR is long enough. 

*7. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in high 
impedance state. 

HITACHI 

1 30 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6289 Series 

Low Vcc Data Retention Characteristics (Ta = to +70°C) 



This characteristics is guaranteed only for L-version. 



Item 


Symbol 


Min 


Typ Max 


Unit 


Test Conditions 


Vcc for data retention 


Vdr 


2 




V 


CS>Vcc-0.2 V, 


Data retention current 


Iccdr 




— 50" 2 
35" 


\iA 


Vin>Vcc-0.2Vor 
V < Vin < 0.2 V 


Chip deselect to data retention tin 


e tCDR 







ns 


See retention waveform 


Operation recovery time 


tR 


tec* 1 




ns 





Note: *1. IRC = Read cycle time 
*2. Vcc = 3.0 V 
•3. Vcc = 2.0 V 



Low Vcc Data Retention Waveform 



Data Retention Mode 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 31 




Supply Current vs. Supply Voltage Supply Current v.. Ambient Temperature 




Access Time vs. Supply Voltage 









Ta = 25'C 











































4.75 5.0 5.25 

Supply Voltage Vcc (V) 



5.5 



Access Time v*. Load Capacitance 



I u 
i 



t 



\2 



o 1.0 
P 

8 0-8 

I 

0.6 



50 100 150 200 

Load Capacitance Cl (pF) 



Access Time vs. Ambient Temperature 



Supply Current vs. Frequency 









V cc = 5.0V 











































20 



40 



60 



80 



Ambient Temperature Ta (°Q 




20 T (n 



Frequency f (MHz) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Low Level Input Voltage vs. Supply Voltage 



High I 



» vs. Supply Voltage 



■ja 

9 

> 



2 

I 



1.1 



i 
I 
J 









la=Z5V 











































4.5 4.75 5.0 5.25 5.5 

Supply Voltage Vcc(V) 



1 U 



a io 
> 

i 0.9 
J3 

i 

§ 0.7 









Ta=25t; 











































Supply Voltage Vcc(V) 



Output Current v». Output Voltage (1) 



Output Current vs. Output Voltage (2) 



j§ 1.2 



I 1.0 
9 

u 

§. 0.8 

<3 
■a 



0.4 









Ta = 25t; 
V CC =5V 






































V" 





1 2 3 4 5 

High Level Output Voltage Voh (V) 



1.6 



1.2 



u 0.6 
I 

J °' 4 









Ta = 25t 
'V CC = 5V 


































{ 









0.2 



0.4 0.6 0.8 

Low Level Output Voltage Vol (V) 



Standby Current vs. Ambient Temperature 



Standby Current vs. Supply Voltage 









V CC =3V 
CS=2.8V 



























20 40 60 80 

Ambient Temperature Ta (°Q 



1.4 
f 1.2 



1.0 
S 0.8 

I 06 

S 0.4 
I 

5 0.2 

















h 






























Ta = 2 
CS = V 


CC-0.2V 











Supply Voltage Vcc (V) 



<P HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



133 



Standby Current vs. Input Voltage 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6789 Series 



Maintenance Only 



16384-word x 4-bit High Speed Hi-BiCMOS Static RAM (with OE) 



Features 

• Super Fast Access Time: 25/30 ns (max) 

• Low Power Dissipation (DC) Operating 230 mW (typ.) 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Balanced Read and Write Cycle Time 

• Fully TTL Compatible Input and Output 



Ordering Information 



No. 



Access Time 



Package 



HM6789P-25 
HM6789P-30 



25ns 
30ns 



300 mil 24 pin 
plastic DIP 



HM6789JP-25 
HM6789JP-30 



25ns 
30ns 



300 mil 24 f 
Plastic SOJ 



Block Diagram 



A2 O— 
A3 O- 
A4 O- 
A5 0- 
A6 0- 
A7 0- 
A8 O- 



-Cs: 

-X 
-C3= 



Row 
Decoder 



Memory Matrix 



I/Ol O 
1/02 O- 
1/03 O- 
1/04 O 



CSO 
WEO- 
OEo- 



7^ 



Input 
Data 
Control 



Column I/O 



Column Decoder 



All A12 A13 A9 A10 AO Al 



SD=> 



Bi>1 




Absolute Maximum Ratings 


Item 


Symbol 


Rating 


Unit 


Terminal Voltage to Vss pin 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


P T 


1.0 


W 


Operating Temperature Range 


Topr 


to +70 


"C 


Storage Temperature Range under bias 


T stg (.bias) 


-10 to +85 


°C 


Storage Temperature Range T stg 


-55 to +125 


°C 



HM6789P Series 




(DP-24NC) 



HM6789JP Series 



4^ 



(CP-24D) 



Pin 







AO [T 




24] Vcc 


Al[7 




53] A13 


A2 (T 




22j A12 


A3(T 




H] All 


A4 (T 




20] A10 


A5[T 




19] A9 


A6 R 




l5J NC 


A7 [T 




}t\ 1/01 


A8|7 




w\ 1/02 


csQo 




IS] 1/03 


0¥[ll 




u] 1/04 


VssQi 




iij WE 




(Top View) 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 35 



Recommended DC Operating Conditions (T a = to +70°C ) 



Item 


Symbol 


min 


typ 


max 


Unit 


Supply Voltage 


v CC 


4.5 


5.0 


5.5 


V 


v S s 


0.0 


0.0 


0.0 


V 


Input High Voltage 


VlH 


2.2 




6.0 


V 


Input Low Voltage 


VlL 


-0.5*' 




0.8 


V 



Note) * 1. -3.0V for pulse width g 20ns. 



Function Table 



cs 


OE 


W¥ 


Mode 


V cc Current 


I/O Pin 


Ref. Cycle 


H 


H or L 


HorL 


Not selected 


'SB. 'SBI 


High Z 




L 


H 


H 


Output Disabled 


'cc. 'cci 


HighZ 




i 




L 


H 


Read 


•co •cci 


Dout 


Read Cycled) (2) (3) 


F 


H 


L 


Write 


•cc l CCl 


Din 


Write Cycle (1) (2) (3) (4) 




L 


L 




!CC. lCCl 


Din 


Write Cycle (5) (6) 



DC and Operating Characteristics (V CC =5V±10%, T a =0 to +70°C) 



Item 


Symbol 


min 


typ 


max 


Unit 


Test Conditions 


- 

Input Leakage Current 


UliI 






2 


"A 


V CC = 5.5V,V IN = V SS toV cc 


Output Leakage Current 


«loI 






2 


MA 


CS = V, H orOE = V IH orWE = V IL 

Vl/O = Vss t° v cc 


Operating Power Supply Current 


ice 






100 


mA 


CS= V IL. 'I/O = 0mA 


Average Operating Current 


'cci 






120 


mA 


Min. Cycle, Duty : 100%,Ii/o=0n> A 




'SB 






30 


mA 


CS = V, H 


Standby Power Supply Current 


»SB1 






10 


mA 


CS^ V C c -0.2V 

V IN g 0.2V or V IN g V CC - 0.2V 


Output Low Voltage 


Vol 






0.4 


V 


lOL = 8 mA 


Output High Voltage 


v OH 


2.4 






V 


'OH ~ -4mA 



AC Test Conditions 

• Input pulse levels 

• Input and Output reference levels 

• Input rise and fall time 

• Output Load: See Figure 




136 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6789 Series 



Capacitance (T a = 25°C,/= 1.0MHz) 



Item 


Symbol 


min typ 


max 


Unit 


Test Conditions 


Imput Capacitance 


C IN 




6 




V IN = OV 


Input /Output Capacitance 


Cl/O 




8 


P F 


V I/o =0V 



Note) This parameter is sampled and not 100% tested. 



AC Characteristics (V CC =5V±10%, T a =0 to +70°C, unless otherwise noted.) 
Read Cycle 







Item 


Symbol 




HM6' 


'89-25 


HM6 


789-30 


Unit 


min 


max 


min 


max 


Read Cycle Time 


l RC 


25 




30 




ns 


Address Access Time 


tAA 






25 




30 


ns 


Chip Select Access Time 


'ACS 






25 




30 


ns 


Chip Selection to Output in Low Z 


«CLZ*1 




3 









ns 


Output Enable to Output Valid 


( OE 




) 


15 





15 


ns 


Output Enable to Output in Low Z 


tOLZ'l 




D 









ns 


Chip Deselection to Output in High Z 


l CHZ*l 





10 





12 


ns 


Output Hold from Address Change 


<OH 




5 




5 




ns 


Input Voltage Rise/Fall Time 


tj" 






150 




150 


ns 


Write Cycle 


Item 


Symbol 




HM6789-25 


HM6789-30 


Unit 


min 


max 


min 


max 


Write Cycle Time 


'wc 


25 




30 




ns 


Chip Selection to End of Write 


<CW 


20 




25 




ns 


Address Setup Time 


*AS 












ns 


Address Valid to End of Write 


•aw 


20 




25 




ns 


Write Pulse Width 


*WP 


20 




25 




ns 


Write Recovery Time 


'WR 












ns 


Write to Output in High Z 


l WHZ*l 





10 





12 


ns 


Data Valid to End of Write 


'DW 


15 




20 




ns 


Data Hold Time 


'dh 


5 




5 




ns 


Output Disable to Output in Hihg Z 


tOHZ'l 





10 





10 


ns 


Output Active from End of Write 


l ow*i 












ns 



Notes) * 1. Transition is measured ±200mV from steady state voltage with Load (B). 
This parameter is sampled and not 100% tested. 
*2. If tx becomes more than 150ns, there is possibility of function fail. 
Please contact your nearest Hitachi Sales Dept. regarding specification. 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 137 



HM6789H Series - 



Timing Waveform 
I Cycled I' 1 



)( 



X 



5£k 



High 



A 



A 







7 



Read Cyde<2)' 1 ' 2 ' 3 



Dout Previovs Data Valid 



A 



/'X/V 



X 



ICyd. W'W* 




Notes) »1. WE = Vih 

*2. C3> V IL 

*3. OE=V, L _ 

*4. Address valid prior to or coincident with CS transition Low. 



HITACHI 

1 38 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6789 Series 



Writs Cyds (1) (OE = H. WE Controlled) 



> 




( 












\\\ 


XV 


Sl_ _l 




///// 






t„ 


tra 








t 




XXXXX) 


\ X X 7 D,u WM 


X 


XXXX) 



H«h Imp*<Un« 



Writs Cyds (2) (OE - H, CS Controlled) 



> 


( ) 
















In 






\ \ \ \ \ W 










lj>« 




XXXXXXX 


D«uVJid ^ 


:xxxx> 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 39 




HITACHI 

140 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6789 Series 



)( 



3 



High 



High I 



7 



p 



<a D ^ r > 



*5 High Impedance 



Write Cycle (6) (OE = L, CS Controlled) 



)( 



JJSL- 



X 







X 



1 



/ ♦< \ HUh 

\ i 



High Impedance 



Dm 





Notes) * 1 . A write occurs during the overlap (t W p) of a low CS and a low WE. 

*2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs 

must not be applied. 
*3. Dout isjhe same phase of write data of this write cycle. 

*4. If the CS is low transition occurs after the WE low transition, output remain in a high impedance state. 

*5. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to 

the outputs must not be applied to them. 
*6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain 

in high impedance state. 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 41 



HM6789H Series 



16384-word x 4-bit High ! 



Hi-BiCMOS Static RAM (with 



Features 

• Super Fast Access Time: 

• Low Power Dissipation (DC) Operating . . 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Balanced Read and Write Cycle Time 

• Fully TTL Compatible Input and Output 



15/20 ns (max) 
280 mW (typ.) 



Ordering Information 






Type No. 


Access Time 


Package 


HM6789HP-15 
HM6789HP-20 


15 ns 
20ns 


300 mil 24 pin 
plastic DIP 


HM6789HJP-15 
HM6789HJP-20 


15ns 
20ns 


300 mil 

24 pin plastic SOJ 


Block Diagram 








Memory Malrm 
128X512 



IE 



Column I/O 



Column Decoder 



WW 



A12 All A10 A9 Al AO A13 

- 




Absolute Maximum Ratings 


Item 


Symbol 


Rating 


Unit 


Terminal Voltage to V ss Pin 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


P T 


1.0 


w 


Operating Temperature Range 




to +70 


°c 


Storage Temperature Range under bias 


Tobias) 


-10 to +85 


°c 


Storage Temperature Range 


T stg 


-55 to +125 


°c 



HM6789HP Series 




(DP-24NC) 



HM6789HJP Series 




(CP-24D) 



Pin Arrangement 




Note) The specifications of this device are subject to change without notice. 
: contact Hitachi's Sales Dept. regarding specifications. 



142 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6789H Series 



Recommended DC Operating Conditions (T a = to +70°C) 





Item 


Symbol 


min 


typ 


max Unit 






Supply Voltage 


v C c 


4.5 


5.0 


5.5 V 






v S s 


0.0 


0.0 


0.0 V 






Input High Voltage 


Vih 


2.2 


- 


6.0 V 






Input Low Voltage 


VlL 


-0.5" 




0.8 V 






Note) 


♦1. -3.0V for pulse width g 10ns. 








Function Table 














cs 


51 


WE 




Mode 


Vcc Current 


I/O Pin 


Ref. Cycle 


H 


H or L 


H or L 


Not selected 


'SB< 'sbi 


High Z 




L 


H 


H 


Output Disabled 


'cc 'cci 


HighZ 




L 


L 


H 




Read 


•cc 'cci 


Data Out 


Read Cycle (1) (2) (3) 


L 


H 


L 




Write 


l CC [ CC1 


Data In 


Write Cycled) (2) (3) (4) 


L 


L 


L 




'cc 'cci 


Data Out 


Write Cycle (5) (6) 



DC and Operating Characteristics (Vcc =5V±10 %. T a=0 t0 +70°C) 



Item 


Symbol 


min 


typ max 


Unit 


Test Conditions 


Input Leakage Current 


UliI 




2 


MA 


V CC = 5.5V,V IN = V SS to V CC 


Output Leakage Current 


HloI 




10 


ma 


CS = V 1H or OE = V, H orWE = V IL , 
Vl/o = Vss «° v cc 


Operating Power Supply Current 


'cc 




100 


mA 


CS = Vil, I I/0 = 0mA 


Average Operating Current 


•cci 




120 


mA 


Min. Cycle, Duty: 100%,Ii/o=0mA 




ISB 




30 


mA 


CS= V IH 


Standby Power Supply Current 


'SBI 




10 


mA 


CSa V C c -0.2V 

V IN £ 0.2V or V, N ^ V c c - 0.2V 


Output Low Voltage 


Vol 




0.4 


V 


I OL = 8mA 


Output High Voltage 


V OH 


2.4 




V 


I OH = "4mA 


AC Test Conditions 






V ss to 3.0V 






• Input and Output reference It 

• Input rise and fall time . . . 

• Output Load: See Figure 














4 ns 









Output 
O 



Output 
o 



30pF- 



777 
Outpol Led A 



777 

Output Lo.d B 
(lc»«.l™ 2 .lom 
ten. to», ton) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point PKwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 43 



HM6789H Series 

Capacitance (T a = 25°C,/= 1.0MHz) 



Item Symbol min 


typ 


max 


Unit 


Test Conditions 


Imput Capacitance Cnx 




6 


pF 


ViN = OV 


Input/Output Capacitance Ct/o 




10 


PF 


V I/o =0V 


Note) This parameter is sampled and not 100% tested. 











AC Characteristics (V CC =5V+10%, T a =0 to +70°C, unless otherwise noted.) 
Read Cycle 



Item 




HM6789H-15 


HM6789H-20 




Symbol 


min 


max 


min max 


Unit 


Read Cycle Time 


'RC 


15 




20 - 


ns 


Address Access Time 


'AA 




15 


20 


ns 


Chip Select Access Time 


'ACS 




15 


20 


ns 


Chip Selection to Output in Low Z 


'CLZ*' 


3 




3 


ns 


Output Enable to Output Valid 


'OE 





12 


12 


ns 


Output Enable to Output in Low Z 


»OLZ'l 


3 




3 - 


ns 


Chip Deselection to Output in High Z 


'CHZ*> 





6 


8 


ns 


Output Hold from Address Change 


'OH 


3 




3 - 


ns 


Write Cvcle 

"rue wy*.iB 












■ 

Item 





HM6789H-15 


HM6789H-20 


— Unit 


Symbol 


min 


max 


min max 




Write Cycle Time 


'wc 


15 




20 


ns 


Chip Selection to End of Write 


'cw 


10 




15 


ns 


Address Setup Time 


'AS 










ns 


Address Valid to End of Write 


'aw 


10 




15 


ns 


Write Pulse Width 


'wp 


10 




15 


ns 


Write Recovery Time 


'WR 


1 




1 


ns 


Write to Output in High Z 


'WHZ* 1 





6 


8 


ns 


Data Valid to -End of Write 


'DW 


9 




10 


ns 


Data Hold Time 


'dh 










ns 


Output Disable to Output in High Z 


'OHZ'l 





6 


8 


ns 


Output Active from End of Write 


'ow'i 










ns 




Note) *1. Transition is measured ±200mV from steady state voltage with Load (B). 
This parameter is sampled and not 100% tested. 



@ HITACHI 

144 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 





HM6789H Series 



Timing Waveform 
Rud Cycle 



Address 



OE 



cs 



Data Out 



[igh Imped™* 



(XX 



Read Cycle (2,* 1 .'2.'3 



A 



V 



Diu vja 



Address 



) 


< > 


( 




In 






lorn 




Previous Data Valid ^ 


boo 


^ Data Vdid \ 


b< 



Read Cycle (3)' 1-3 M 



7 



Data Out 



Notes) *1. WE = V IH 

*2. C3 = V, L 

•3. OE= V, L _ 

*4. Address valid prior to or coincident with CS transition Low. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 145 



HM6789H Series - 



Writ* Cyd. (1) (OE = H. WE Controlled) 



Address 



CS 



WE 



Datal 



Data Out 



) 


( 








( 




- 




\\\ 


\v 


\ / 


iU 


///// 

L L L L 1— 








It 








m '" 


I 

Im 




XXXXXXXX) 


( )( 


:xxxx> 


Hfcbk, 













Writ. Cyd. (2) (OE - H. CS Controlled) 



X 



CS 



WE 



1 



\x\\x\r 



- xxxxxxxx 



Data Out 



'rZUUL 



mm 



— 



HITACHI 

146 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



HM6789H Series 



Write Cyde (3) (OE - Clocked, WE Controlled) 



Address 



OE 



)( 







cs 



WE 



L!I_ 



Data Out 



Data In 



31 



High 



High Impedance 



Impedance 



Writ* Cyd* (4) (OE - Clocked, CS Controlled) 



Address 



OE 



CS 



WE 



Data In 



Data Out 



) 


< > 


( 








/// 


//> 


















s 


\ / 


1 




~ ^ ■ 

twr*l 




\\\\\\\^ 


V////// 




ton 




XX* - f 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



147 



HM6789H Series 

Writ* Cyd» (5) (OE - L, WE Controlled) 



Address 



CS 



WE 



Data Out 



Data In 



)( 



' 



DC 

izzzz 



))>)))) i 



— 



High Impedance 



7 



i 



5 High Impedance 



Writ* Cyd. (S) IOE = L, CS Controlled! 



Address 



CS 



WE 



Data Out 



Data In 



) 


( ) 


< 














\ 


\ / 


/ 

In 




i«» 


WW 




\ ? 


V////// 




leu 


1 WHZ 

f *4 \ High Impedance 






v / 








High Impedance 


-A) 




XXXX) 



Notes) * 1 . A write occurs during the overlap (t WP ) of a low CS and a low WE. 

*2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs 

must not be applied. 
♦3. Data Out is the same phase of write data of this write cycle. 

*4. If the CS is low transition occurs after the WE low transition, output remain in a high impedance state. 

*S. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to 

theoutputs must not be applied to them. 
*6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output i 

in high impedance state. 

HITACHI 

148 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



HM6789HA Series 

16384-Word x 4-Bit High Speed Static RAM (with OE) 
■ FEATURES 

• Super Fast 

Access Time 



. . . .Add. J2/15/20ns (max.) 
OE 6/7/8ns (max.) 
Low Power Dissipation 

(DC) Operating 300mW (typ.) 

+ 5V Single Supply 
Completely Static Memory 

No Clock or Timing Strobe Required 
Fully TTL Compatible Input and Output 

I ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6789HAP-12 


12ns 


300 mil 24 pin 


HM6789HAP-15 


15ns 


Plastic DIP 


HM6789HAP-20 


20ns 


(DP-24NC) 


HM6789HAJP-12 


12ns 


300 mil 24 pin 


HM6789HAJP-15 


15ns 


Plastic SOJ 


HM6789HAJP-20 


20ns 


(CP-24D) 




— Preliminary 




(DP-24NC) 



(CP-24D) 



PIN ARRANGEMENT 



Ao 


c 




24 


□ 


VCC 


Ai 




2 


23 


□ 


A13 


A 2 


□ 


3 


22 


□ 


A12 


A3 




4 


21 




An 


A4 


c 


5 


20 


□ 


A10 


As 


E 


6 


19 


□ 


A 9 


A 6 


c 




18 


□ 


NC 


A 7 


c 


8 


17 


□ 


l/Oi 


As 


c 


9 


16 


□ 


I/02 


CS 


q 


10 


15 


□ 


I/O3 


OE 


c 


11 


14 


□ 


I/O4 


vss 


c 


12 


13 


□ 


WE 



(Top View) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



149 



ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


. 

Voltage on Any Pin Relative to V ss 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


Pj 


1.0 


W 


Operating Temperature Range 


T opr 


Oto +70 


°c 


Storage Temperature Range (with bias) 


T stf>(bias) 


-10 to + 85 


°c 


Storage Temperature Range 




-55 to + 125 


°c 



RECOMMENDED DC OPERATING CONDITIONS (0°C < T a < 70°C) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


v ss 


0.0 


0.0 


0.0 


, 

V 


Input High Voltage 


V,H 


2.2 




6.0 


V 


Input Low Voltage 


V,L* 


-3.0 





0.8 


V 



•Pulse width s 10ns, DC: -0.5V 
■ TRUTH TABLE 



CS 


OE 


WE 


Mode 


Vcc Current 


I/O Pin 


Ref. Cycle 


H 


HorL 


HorL 


Not Selected 


Isb> 'sbi 


HighZ 




L 


H 


H 


Output Disabled 


Ice Icci 


HighZ 




L 


L 


H 


Read 


Ice Icci 


Data Out 


Read Cycled) (2) (3) 


L 


H 


L 




Ice- Icci 


Data In 


Write Cycle (1) (2) (3) (4) 


L 


L 


L 


Write 


Ice Icci 


Data In 


Write Cycle (5) (6) 



DC AND OPERATING CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, V ss = 0V) 



Item 


Symbol 


Test Condition 


Min. 


Typ. 


Max. 


Unit 


Input Leakage Current 


liul 


V cc = 5.5V,V IN = V ss toV cc 






2 


HA 


Output Leakage Current 


HloI 


CS = V IH or OE = V 1H , WE = V IL 
v i/o = V ss to V cc 






10 




Operating Power Supply Current 


I C c 


CS = V 1L , I I/Q , = 0mA 






100 


mA 


Average Operating Current 


Icci 


Min. Cycle, Duty: 100%, I I/0 = 0mA 






120 


mA 




Isb 


CS = V IH 






30 


mA 


Standby Power Supply Current 


Isbi 


CS > V cc - 0.2V 

V 1N < 0.2V or V IN > V cc - 0.2V 






10 


mA 


Output Low Voltage 


Vol 


IoL = 8mA 






0.4 


V 


Output High Voltage 


V 0H 


Ioh = -4mA 


2.4 

1 






V 



AC TEST CONDITIONS 

1 Input Pulse Levels: V ss to 3.0V 
1 Input and Output Reference Levels: 1.5V 
± 200mV from steady level (Output Load B) 



1 Input Rise and Fall Time: 4ns 
Output Load: See 1 



Dout 



+5 V 
: 4800 



2550 



Dout 



+5V 
4800 



30 pF' 



255(1 



/P7 
Output Load A 



5pF* 



S77 
Output Load B 
(for t CHZ , t CLZ , t OHZ . t 0LZ , t wz & tp W ) 



•Including scope and jig capacitance. 



150 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6789HA Series 



■ TIMING WAVEFORM 
• Read Cycle (1)<D 



Address 



tRC 



X 



tAA 



tOE 



toLZ 



CS 



tACS 



'&.Z 



High I 
Cycle (2) «>.»« 



Address 



• Read Cycle (3) (DO) (4) 



CS 



Data Out 



tRC 



'ACS 



tCLZ 



High I 




X 







JP /////////, 



'oh 



7-7-7 



'OHZ 



'CHZ 



Data Valid 



1Z 



m- 









> 


< > 


< 








« 'oh ^ 




tOH . 




Previous Data Valid XXXX1) 


^ Data Valid ) 


X 



'CHZ 



Data Valid 



NOTES: 1WE = V,h 

2. CS = V, L 

3. OE = Vil 

4. Address valid prior to or coincident with ( 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



151 



HM6789HA Series 



■ CAPACITANCE (T a = 25 °C, f = 1.0MHz) 



Item 


Symbol 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Input Capacitance 




v, N = ov 






6 


pF 


Input/Output Capacitance 


C I/0 


V,/ = ov 






10 


pF 



NOTE: This parameter is sampled and not 100% tested. 



; 



■ AC CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, unless otherwise noted.) 
• Read Cycle 



Item 


Symbol 


HM6789HA-12 


HM6789HA-15 


HM6789HA-20 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


«RC 


12 




15 




20 




ns 




Address Access Time 


l AA 




12 




15 




20 


ns 




Chip Select Access Time 


'ACS 




12 




15 




20 


ns 




Chip Selection to Output in Low Z 


tCLZ 


3 




5 




5 




ns 


1,2 


Output Enable to Output Valid 


<OE 





6 





7 





8 


ns 


1 


Output Enable to Output in Low Z 


k)LZ 


2 




2 




2 




ns 


1,2 


Chip Deselection to Output in High Z 


'CHZ 





6 





6 





8 


ns 


1, 2 


Output Hold from Address Change 


'oh 


4 




4 




4 




ns 




• Write Cycle 


Item 


Symbol 


HM6789HA-12 


HM6789HA-15 


HM6789HA-20 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


'wc 


12 




15 




20 




ns 




Chip Selection to End of Write 


•cw 


8 




10 




15 




ns 




Address Setup Time 


'AS 

















ns 




Address Valid to End of Write 


'aw 


8 




10 




15 




ns 




Write Pulse Width 


'wp 


8 




10 




15 




ns 




Write Recovery Time 


l WR 

















ns 




Write to Output in High Z 


'WHZ 





6 





6 





8 


ns 


1, 2 


Data Valid to End of Write 


'dw 


6 




7 




10 




ns 




Data Hold Time 


'dh 

















ns 




Output Disable to Output in High Z 


tOHZ 


1 


6 


1 


6 


1 


8 


ns 


1. 2 


Output Active from End of Write 


'ow 


3 




3 




3 




ns 


1,2 



NOTES: 1. Transition is measured ±200mV from steady 
2. This parameter is sampled 



with Load B. 



HITACHI 

1 52 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6789HA Series 



• Write Cycle (1) (OE = H, WE Controlled) 



Address 



twc 



>C 



tew 



//////////////A 



tAS 



WE 



tWP(1) 



tpw 



x 



tDH 



xxxxxxxxxxxxxxxy* p-v* *xxxxxxxx> 

High I 



Data Out 



• Write Cycle (2) (OE = H, CS Controlled) 



Address 



CS 



> 


< ) 


< 
















\ / 

tAW 


f 




1 _ t W P(1) 


wwwwwxww 


<//////////////, 




«« tow ^ 






xxxxxxxxxxxxxxxx> 


<^ Data Valid )< 


XXXXXXXX) 



High Impedance 
Data Out 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 53 



HM6789HA Series 



• Write Cycle (3) (OE = Clocked, WE Controlled) 



Address 



twc 



X 



67 '/////////# 



>C 



tgw_ 



cs 



WE 







tAW 



; V/////////////, 



tAS 



IWPd) 



^OHZ^ 



/ 



Data Out 



Data In 



High Impedance 



High Impedance 



tpw 



tWR 



tOLZ(2 



, tDH 



xx> 



High Impedance 



Cycle (4) (OE = Clocked, CS Controlled) 



Address 



twc 



X 



OE '////////////& 

tAS 



CS 



WE 



Data In 



Data Out 



<cw 



< ,AW *■ - 


tWR „ 






■V///////////A 




< *DW > 






XX) 


( Data Valid ) 


XX 



High Impedance 



HITACHI 

1 54 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Write Cycle (5) (OE = L, WE Controlled) 



HM6789HA Series 



Address 



X 



5^ 



///////////////. 



WE 



mi 



tWP (1) 



0-0, »»»»»»»>^ 



twHZ (2) 

High Impedance 



Data In 



High Impedance 



*DW 




>c 



tWR 



V 



tow 



tfJH 



•dh 



Data Valid 



(S)High Impedance 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 55 



HM6789HA Series 



• Write Cycle (6) (OE = L, CS Controlled) 



Address 
CS 

WE 

Data Out 
Data In 



>c 

tAS 



tCLZ 



tew 



Uw 



tyyp P) 



x 



tWHZ 



High Impedance 



High Impedance 



tDW 



' //////////////, 



Data Valid 



NOTES: 1. A write occurs during the overlap (twp) of a low CS and a low WE. 

2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not 
be applied. 

3. D 0U | is the same phase of write data of this write cycle. 

4. If the CS low transition occurs after the WE low transition, output remain in a high impedance state. 

5. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the 
outputs must not be applied to them. 

6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in 
high impedance state. 



HITACHI 

1 56 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6287 



65536-word x 1-bit Hi 




Maintenance Only 



RAM 



■ FEATURES 

• High Speed: Fast Access Time 45/55/70ns (max.) 

• Single 5V Supply and High Density 22 Pin Package 

• Low Power Standby and Low Power Operation 
Standby: 100/iW (typ.)/10//W (typ.) (L-version) 
Operation: 300mW (typ.) 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Equal Access and Cycle Times 

• Directly TTL Compatible: All Inputs and Output 

• Capability of Battery Back Up Operation (L-version) 

■ ORDERING INFORMATION 




Type No. 



HM6287P-45 
HM6287P-55 
HM6287P-70 



HM6287LP-45 
HM6287LP-55 
HM6287LP-70 



Access Time 



45 ns 
55ns 
70ns 



45 ns 
55ns 

70ns 



300 mil 22 pin 
Plastic DIP 



■ BLOCK DIAGRAM 



M«B«r, Arr., 



-Vcc 
-V>1 



■ PIN ARRANGEMENT 

7T]a„ 

ioJa,, 

TTJa,! 
T7|a,i 

Ai(T TT]Ai, 

a.(T TT| a,. 

.(7 77] a. 

d™ [7 T7J At 

W [io TT) d.. 




(Top View) 



5£l 



Column Dtcott, 



mmm 







NOTE: Not for new designs. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



157 



HM6287 Series 

■ TRUTH TABLE 



cs 


WE 


Mode 


1 

Vcc Current 


Dout Pin 


. 

Ref. Cycle 


H 


X 


Not Selected 


^B^SBl 


High Z 




L 


H 


Read 


Ice 


Dout 


Read Cycle 


L 


L 


Write 


>CC 


High Z 


Write Cycle 







■ ABSOLUTE MAXIMUM RATH 



Item 


Symbol 


Rating 


Unit 


Voltage on Any Pin Relative to V$s 


V T 


-0.5* 1 to +7.0 


V 


Power Dissipation 


Pt 


1.0 


W 


Operating Temperature 


Topr 


to +70 


°C 




Storage Temperature 


T Mtg 


-55 to +125 


°C 


Temperature Under Bias 




-10 to +85 


°c 


Note) * 1 . -3 .5V for pulse width g 20ns 

















■ RECOMMENDED DC OPERATING CONDITIONS (T a = to +70°C) 



Item 


Symbol 


min 


typ 


max 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


v S s 











V 


Input Voltage 


v m 


2.2 




6.0 


V 




-0.5* 1 




0.8 


V 



Note) * 1. -3.0V for pulse width £ 20ns 

■ DC AND OPERATING CHARACTERISTICS (V cc = 5V ± 10%, V ss = 0V, Ta = to +70°C) 



Item 


Symbol 


Test Conditions 


min 


typ* 1 


max 


Unit 


Input Leakage Current 




K CC = 5.5V, Kf^Kss to K CC 






2.0 


*iA 


Output Leakage Current 


\Ilo I 


cs = k /h , v out = v ss to v cc 






2.0 


MA 


Operating Power Supply Current 


ice 


CS = V IL , I out = 0mA, min. cycle 




60 


100 


mA 




! SB 


cs = Vm< min - °y c ' e 




10 


30 


mA 


Standby Power Supply Current 




CSg Fcc-0-2V, 

0V g V ln g 0.2V or V C C - 0-2V i V in 




0.02 


2.0 


mA 






2*2 


100 * 2 


mA 


Output Voltage 


Vol 


l0L~ 8mA 






0.4 


V 


Vqh 


I OH - -4.0mA 


2.4 






V 



Notes) *1, Typical limits are at V C C = S <>V, T a = 25°C and specified loading. 
•2. This characteristics is guaranteed only for L-version. 



■ CAPACITANCE (/= 1MHz, r B = 25°C) 



Item 


Symbol 


Test Conditions 


min 


typ 


max 


Unit 


Input Capacitance 




V in = 0V 






5 


pF 


Output Capacitance 


Cout 


Vout = 0V 






7.5 


pF 



Note) This parameter is sampled and not 100% tested. 



HITACHI 

1 58 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwv. • E 



HM6287 Series 



■ AC CHARACTERISTICS (V CC = 5V ±10%, T a = to +70°C, unless otherwise noted) 
• AC TEST CONDITIONS 

Input Pulse Levels: V S s to 3.0V 

Input Rise and Fall Times: 5ns 

Input and Output Timing Reference Levels: 1 .5V 

Output Load: See Figure 



Output Load A 



Output Load B 



sv 



Dout o— 



2550 . 



: 30pF 



$ 4800 

ispF* 



i 



* Including scope & jig capacitance 

• READ CYCLE 



♦ Including scope & )ig capacitance 



Item 


Symbol 


HM6287-45 


HM6287-55 


HM6287-70 


Unit 


Notes 


min 


max 


mm 


max 


min 


max 


Read Cycle Time 


>RC 


45 




55 




70 




ns 


1 


Address Access Time 


'AA 




45 




55 




70 


ns 




Chip Select Access Time 


'ACS 




45 




55 




70 


ns 




Output Hold from Address Change 


'OH 


5 




5 




5 




ns 




Chip Selection to Output in Low Z 


'LZ 


5 




5 




5 




ns 


2, 3,7 


Chip Deselection to Output in High Z 


'HZ 





30 





30 





30 


ns 


2,3,7 


Chip Selection to Power Up Time 


tpu 

















ns 


7 


Chip Deselection to Power Down Time 


tPD 




40 




40 




40 


ns 


7 



• Timing Waveform of Read Cycle No. 1 <4)(5) 



Address 



Dout 



X 



X 



Previous Dan Valid )( X X ) C 

• Timing Waveform of Read Cycle No. 2 (4)(6) 



Data Valid 



3^ 



es 



Dout 







Ice 



High Impedance 

— In 



XXK 



X 



Data Valid 



VcC supply 
current 



t SO",, 



/""High 



Ian 

Notes: 1 . All Read Cycle timings are referenced from last valid address to the first transitioning address. 

2. At any given temperature and voltage condition, tffZ max - is le ss than tiz min. both for a given device 
and from device to device. 

3. Transition is measured t500 mV from steady state voltage with specified loading in Load B. 

4. WE is high for READ Cycle. 

5. Device is continuously selected, while CS = V[i. 

6. Address valid prior to or coincident with CS transition low. 

7. This parameter is sampled and not 1 00% tested. 



Hitachi America. 



HITACHI 



. CA 94005-1819 • (415) 589-8300 



159 



HM6287 Series - 



• WRITE CYCLE 



Item 


Symbol 


HM6287-45 


HM6287-55 


HM6287-70 


Unit 


Notes 


min 


max 


min 


max 


min 


max 


Write Cycle Time 


'WC 


45 


- 


55 


- 


70 


- 


ns 


2 


Chip Selection to End of Write 


'CW 


40 


- 


50 


- 


55 


- 


ns 




Address Valid to End of Write 


'AW 


40 


- 


50 


- 


55 


- 


ns 




Address Setup Time 


'AS 

















ns 




Write Pulse Width 


tWP 


25 




35 




40 




ns 




Write Recovery Time 


'WR 

















ns 




Data Valid to End of Write 


'DW 


25 




25 




30 




ns 




Data Hold Time 


tDH 

















ns 




Write Enabled to Output in High Z 


'wz 





25 





25 





30 


ns 


3,4 


Output Active from End of Write 


<OW 

















ns 


3,4 



• Timing Waveform of Write Cycle No. 1 (WE Controlled) 



C5 
WE 

Din 



ZD 


- lur 




t ) 


( 




li « 










i ; 


/ 






us - 


lAH — 


"-—/UK—*- 








""• ; 


t 

h"-/iJH 






- — low •» 




) 


^Data in Va 


mZ 






High Impedance 




Data Undefined /( 


( 



• Timing Waveform of Write Cycle No. 1 (CS Controlled) 



cs 



WE 



Din 
Dout 



J.- 



JZla 



1- 1« 


High Impedance 


[ Data Undefined ) 





Notes) 1. If CS goes high Simultaneously with WE high, the output remains in a high impedance state. 

2. All Write Cycle timings are referenced from the last valid address to the first transitioning address. 

3. Transition is measured ±S00mV from steady state voltage with specified loading in Load B. 

4. This parameter is sampled and not 100% tested. 



HITACHI 

160 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6287 Series 



■ LOW V cc DATA RETENTION CHARACTERISTICS (T a = to +70°C) 

This characteristics is guaranteed only for L-version. 



Parameter 


Symbol 


Test Condition 


min. 


typ. 


max. 


Unit 


Vcc f° r Data Retention 


V D R 


v% = > r fcc-^'^' 0! 

OV Cfi„ < 0.2V 


2.0 






V 


Data Retention Current 


'CCDR 




1 


50* 2 


fA 


Chip Deselect to Data Retention Time 


'CDR 


See retention wave- 
form 









ns 


Operation Recovery Time 


'R 


tRC ' 






ns 



Note) *1. t RC = Read Cycle Time 



*2. K CC =3.0V 
• LOW V cc DATA RETENTION WAVEFORM 



PatA Retgntion Mode 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 61 



HM6287 Series 



ACCESS TIME vs. SUPPLY VOLTAGE 









Ta=25'C 











































4.75 5.0 5.25 

Supply Voltage V cc (V) 



ACCESS TIME vs. AMBIENT TEMPERATURE 



3 1.0 



J 0.9 









Vcc = 5.0V 











































20 40 60 

Ambient Temperature To CC) 



STANDBY CURRENT vs. 
SUPPLY VOLTAGE 



STANDBY CURRENT vs. 
AMBIENT TEMPERATURE 







































To 

CS 


-25'C 

= V cc -0.2V 










2 3 4 


i 



Supply Voltage V c c (V) 



SUPPLY CURRENT vs. 
FREQUENCY 









y C t=3v 

CS=2.8V 



















20 40 
Ambient 



Ta CO 



STANDBY CURRENT vs. 
INPUT VOLTAGE 




10 15 
Frequency / (MHz) 













n = 

Vcc 
CS = 


=25'C 
=5.0V 
=4.8V 



























































1 2 3 4 5 6 

Input Voltage V,.v(V) 



HITACHI 

1 62 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6287 Series 



INPUT LOW VOLTAGE \ 
SUPPLY VOLTAGE 



INPUT HIGH VOLTAGE vs. 
SUPPLY VOLTAGE 



I 

! 









7o=25"C 











































4.75 5.0 5.25 

Supply Voluwe Vcc (V) 



5.5 



3 

1" 

it 

1 1 









7«=25'C 











































4.75 5.0 5.25 5.5 

Supply Voluuje Vcc (V) 



OUTPUT HIGH CURRENT vs. 
OUTPUT HIGH VOLTAGE 



OUTPUT LC 
OUTPUT LC 



*RENT vs. 
LTAGE 









7o = 25'C 
Vcc = 5V 











































12 3 4 

Output High Voltig. V„„ (V) 



r 

I 1.2 



.3 O.i 



0.4 

































Ta =25"C 

V CC =5V 




A 















0.2 0.4 0.6 0.8 

Output Low Volume V 0L (V) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 63 



HM6287H Series 

65536-Word x 1-Bit High Speed CMOS Static RAM 



The Hitachi HM6287H is a high speed 64K static RAM organized 
as 64-kword x 1 -bit. It realizes high speed access time (25/35 ns) and 
low power consumption, employing CMOS process technology and 
high speed circuit designing technology. It is most advantageous for 
the field where high speed and high density memory is required, 
such as the cache memory for main frame or 32-bit MPU. The 
HM6287H packaged in a 300-mil plastic DIP and SOJ, is available 
for high density mounting. 

Low power version retains the data with battery back up. 



Features 

• Single 5 V supply and high density 22-pin DIP and 24-pin 

• Highspeed: Fast access time 25/35 ns (max) 

• Low power 

Operation: 300 mW (typ) 
Standby: 1 00 u.W (typ) 

• Completely static memory 

No clock or timing strobe required 

• Equal access and cycle times 

• Directly TTL compatible: All inputs and outputs 



Pin Arrangement 

HM6287HP Series 



HM6287HP Series 




(DP-22NB) 



4? 



(CP-24D) 



HM6287HJP Series 




(Top View) 



AOc 1 
A1 c 2 
A2n 3 
A3c 1 
A4c 5 
A5C 6 
NCC 7 
A6C 8 
A7C 9 
Dout c 10 
WEC 11 
Vss C 12 



24 av cc 
23 3A15 
22 DA14 
21 3A13 
20 □ A12 
19 3 NC 
18 3A1 1 
17 3A10 
16 3A9 
15 3A8 
14 3 Din 
13 3 CS 



(Top View) 







Pin Description 


Pin Name 


Function 


A0-A15 


Address 


Din 


Input 


Dout 


Output 


CS 




WE 


Write enable 


Vcc 


Power supply 


Vss Ground 



Ordering Information 



Type No. 



Access Time 



Package 



HM6287HP-25 
HM6287HP-35 



HM6287HLP-25 
HM6287HLP-35 



25 ns 
35 ns 



25 ns 
35 ns 



300-mil 
22-pin 
plastic DIP 
(DP-22NB) 



HM6287HJP-25 
HM6287HJP-35 



HM6287HLJP-25 
HM6287HLJP-35 



25 ns 
35 ns 



25 ns 
35 ns 



300-mil 
24-pin SOJ 
(CP-24D) 



HITACHI 

1 64 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6287H Series 



Block diagram 



AO 

— te 
«— J* 
«— b 

— -te 



Row 
Decoder 



Din 



i" fr- 

WE-j>— I 



Memory Array 
128X512 



Column I/O 



Column Decoder 



{> Dout 



A7 A8 A9 A10 All A12 A13 A14 A15 



Function Table 








CS WE Mode 


Vcc Current 




Dour Pin 


Ket. Cycle 


H X Standby 


Isb, Isbi 




High-Z 




L H Read 


Ice 




Dow 


Read cycle 1, 2 


L L Write 


Ice 




High-Z 


Write cycle 1, 2 


Note: x: H or L 










Absolute Maximum Ratings 










Item 


Symbol 




Value 


Unit 


Voltage on any pin relative to Vss 


Vt 




-0.5/! to +7.0 


V 


Power dissipation 


Pt 




1.0 


W 


Operating temperature 


Topr 




to +70 


°C 


Storage temperature 


Tstg 




-55 to +125 


°c 


Storage temperature under bias 


Tbias 




-10 to +85 


°c 


Note: *1. Vt min= -2.0 V for pulse widths 10 n 




















Recommended DC Operating Conditions (Ta = to + 70°C) 






Item Symbol 


Min 




Typ Man 


Unit 


Vcc 


4.5 




5.0 5.5 


V 


Supply voltage — 

Vss 










V 


Input high (logic 1) voltage Vih 


2.2 




— 6.0 


V 


Input low (logic 0) voltage Vn. 


-0.5- ' 




— 0.8 


V 



Note: *1. Vn. min =-2.0 V for pulse width < 10 ns 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 "1 65 



HM6287H Series 



DC Characteristics ( Ta 


= to +70°C, Vcc 


= 5 V± 10%, Vss 


= V ) 






Item 


Symbol 


Min 


Typ" 


Max 


Unit 


Test Conditions 


Input leakage current 


IIliI 


— 


— 


2.0 


uA 


Vcc = Max 












Vin = Vss to Vcc 


Output leakage current 


IIloI 


— 


— 


2.0 


U.A 


CS = Vdi 














Vto = Vss to Vcc 


Operating Vcc current 


Ice 




60 


120 


mA 


CS = Vn. 














lout = mA, min cycle 


Standby Vcc current 


ISB 




15 


30 


mA 


CS = Vni, min cycle 








0.02 


2.0 


mA 


CS > Vcc - 0.2 V 


Standby Vcc current (1) 


ISB1 










- V < Vin < 0.2V or 








0.02* 2 


o.r 


mA 


Vcc - 0.2 V< Vin 


Output low voltage 


Vol 






0.4 


V 


lot. = 8 mA 


Output high voltage 


Voi i 


2.4 






V 


Ion = -4.0 mA 


Notes: *1. Typical limits are at Vcc = 5.0 V, 


Ta = 25°C and specified loading. 








*2. This characteristics is guaranteed 


>nly for L- 


version. 









Capacitance ( Ta = 25°C, f = 1 .0 MHz )*' 

Item Symbol Min Typ Max Unit Test Conditions 

Input capacitance Cin — — 6 pF Vin = V 

Output capacitance Cout — — 8 pF Voul = V 

Note: *i. This parameter is sampled and not 100% tested. 



AC Characteristics ( Ta = to +70°C, Vcc = 5 V ± 10%, unless otherwise noted. ) 
Test Conditions 

• Input pulse levels: Vss to 3.0V • Input and Output timing reference levels: 1 .5 V 

• Input rise and fall times: 5 ns • Output load: See figures 

Output Load (A) Output Load (B) (for tnz, liy, twz & low) 




Note: Including scope & jig 



166 Hitachi Americ; 



HITACHI 

Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6287H Series 



Read Cycle 



Item 


O Y 1 1 1 lAJ 1 


HM6287H-25 


HM6287H-35 


Unit 


Min 


Max 


Min 


Max 


Read cycle time 


tKC 


25 


— 


35 


— 


ns 


Address access time 


tAA 




25 




35 


ns 


Chip select access time 


tACS 




25 




35 


ns 


Output hold from address change 


tOH 


3 




5 




ns 


Chip selection to output in low-Z 


tuz' 1 


5 




5 




ns 


Chip deselection to output in high-Z 


tHZ 1 





12 





20 


ns 


Chip selection to power up time 


tPU 












ns 


Chip deselection to power down time 


tro 




25 




30 


ns 







Read Timing Waveform (1) * 2 -' 3 •' 5 



X 



Previous 
Dm V.I .d 



A X X~A 



Read Timing Waveform (2)^* 4 



cT 







Hi|h lmp*d»ncf 



KXXXZ 



VtC Supply Curr.ni 



Notes: M. Transition is measured ±200 mV from steady state vollage with Load (B). This parameter is sampled and not 100 % tested. 
*2. WE is high for read cycle. 
*3. Device is continuously selected, CS = Vn.. 
*4. Address valid prior to or coincident with CS transition low. 

*S. AU read cycle timing are referenced from last valid address to the first transitioning address. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 67 



HM6287H Series 



Write Cycle 



Item 


symbol 


HM6287H-25 


HM6287H-35 


unit 


Min 


Max 


Min 


Max 


Write cycle time 




twc 


25 


— 


35 


— 


ns 


Chip selection to end of write 


tew 


20 


— 


30 


— 


ns 


Address valid to end of write 


tAW 


20 


— 


30 


— 


ns 


Address setup time 


US 





— 





— 


ns 


Write pulse width 


twp 


20 




30 




ns 


Write recovery time 


tWR 












ns 


Data valid to end of write 


CDW 


15 




20 




ns 


Data hold time 


tDH 












ns 


Write enabled to output in high-Z 


twz*' 





8 





10 


ns 


Output active from end of write 


tow" 1 


5 




5 




ns 

















Write Timing Waveform (1) (WE controlled) 



Address 



CS 



"WE 



_twc_ 



tAW 



■* <XXXXX XX > XXXX>£ 



t»p- 



Data m 
Valid 



Dout 



<((((((< <7(1 Hieh ^^n^ m^ 



: fexxxxx> 



168 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Write Timing Waveform (2) (CS Controlled) 



HM6287H Series 









— -> 


( > 


( 




t.. 


== •! 










tew 

s 7 




\\\\\\\v 


k / 


<///////// 








XXXXXXXXXXXX) 


( xxxxxxx 



Notes: *1. Transition is measured ±200 mV from steadystate voha ge wi th Load (B). This parameter is sampled and not 100% tested. 
•2. A write occurs during the overlap of a lo w CS and a low WE. (twp) 
*3. Iwr is measured from the earlier of CS or WE going high to the end of write cycle. 

*4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain 

in a high impedance slate. 
*5. Dout is the same phase of write data of this write cycle, if Iwr is long enough. 



Low Vcc Data Retention Characteristics ( Ta = to +70°C ) 
(This specification is guaranteed only for L-version.) 



Item Symbol 




Typ 


Max 


Unit 


Test Condition 


Vcc for data retention Vdr 






_ 


V 


C?>Vcc-0.2V 


Data retention current Iccdr 


— 




50' 2 
35'' 


uA 


Vin>Vcc-0.2 Vor 
V < Vin < 0.2 V 


Chip deselect to data retention time taw 









ns 


See retention waveform 


Operation recovery time » 


tRC'l 






ns 



Notes: *1. ttc = Read cycle time 
*2. Vcc = 3.0 V 
•3. Vcc = 2.0 V 



Low Vcc Data Retention Timing Waveform 



Data Retention Mode 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 69 



HM6287H Series 



Supply Current vs. Supply Voltage 



Supply Current vs. Ambient Temperature 



b 1.0 

i 

I 0.8 
U 
>* 

"5. 0.6 



OA 









Ta — 25°C 











































4.5 4.75 5.0 5.25 5.5 

Supply Voltage Vcc (V) 



1-2 

Z 

u 

£ l.O 

c 

u 

§ 0.8 
U 

1 0.6 
3 

0.4 









V CC = 5.0V 











































20 



40 



60 



80 



Ambient Temperature Ta (°C) 



Access Time vs. Supply Voltage 



Access Time vs. Load Capacitance 



1.3 
.1 1.2 



| 0.9 



1 08 

07 



4 5 









Ta=25t 











































4.75 



5 



5.25 5.5 
Supply Voltage Vcc(V) 



1.8 

K 

=§ 16 
o 

Z 1.4 

u 
< 

- 1.2 
< 

s 

u 

E '° 
F 

o 0.8 
o 
S 
< 

0.6 




















































50 100 150 200 

Load Capacitance Ct. (pF) 



Access Time vs. Ambient Temperature 



a 12 



o 
Z 



i 

| 0.! 
| 0, 









V C c = 5.0V 







































80 



Ambient Temperature Ta (°C) 



Supply Current vs. Frequency 

100 50 33 25 20 T (ns) 




Frequency f (MHz) 



170 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, 



HM6287H Series 



Input Low Voltage vs. 



Input High Voltage vs. Supply Voltage 









Ta = 25t; 











































^ 1.3 



4.5 4.75 5.0 5.25 5.5 

Supply Voltage Vcc(V) 



1.2 



i 



> 

■a 



0.9 



0.7 









Ta = 25'C 











































4.5 4.75 5.0 5.25 5.5 

Supply Voltage Vcc(V) 



Output Current vs. Output Voltage ID 



Output Current vs. Output Voltage (2) 









Ta=25"C 
Vcc=5V 


\ 




































v- 





1 2 3 4 5 

Output High Voltage Voh (V) 



^ 1.6 

1 

g 1.4 

O 

S ,.2 
$ 

I" 
u 
* 
3 

a 0.6 
§■ 

° 0.4 



08 









Ta = 25H 
' V C c=5V 











































0.2 



0.4 



0.6 



0.8 



Output Low Voltage Vol (V) 



Standby Current vs. Ambient Temperature 



Standby Current vs. Supply Voltage 









V CC =3V 
CS=2.8V 



























20 40 60 

Ambient Temperature Ta (°C) 



80 



1.4 

a i.2 



5 0.8 

S 

| 0.6 
<3 0.4 
I 0.2 










h 














. 
























Ta=i 


5t 






CS=V CC -0.2V 



3 4 5 

Supply Voltage Vcc (V) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



171 



Standby Current vs. Input Voltage 




Input Voltage Vin (V) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6787 Series 



Maintenance Only 



65536-word x 1-bit High Speed Hi-BiCMOS Static RAM 



■ FEATURES 

• Super Fast Access Time: 25ns/30ns (max.) 

• Low Power Dissipation (DC): 
Operating 180mW (typ) 

• High Driving Capability: l OL 16mA 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Balanced Read and Write Cycle Time 

• Fully TTL Compatible Input and Output 

• Skinny 22-pin Plastic Dip (300 mil) and 22-pin Chip Carrier 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6787P-25 


25ns 


300 mil 22 pin 


HM6787P-30 


30ns 


Plastic DIP 



HM6787P Series 




(DP-22NB) 







■ BLOCK DIAGRAM 




-t>— ° Dout 



■ABSOLUTE MAXIMUM RATINGS 



■ PIN ARRANGEMENT 

• HM6787P Series 



A.[T V " 


J ~n\ vcc 


Ai[T 


IT] A 15 


A 2 (T 


lo] Au 


a 3 [T 


ITj Al3 


A. [7 


If] An 


AsjjT 


17] An 


A«(T 


16] Am 


A 7 [T 


j|] As 


Dout \T 




WE [lO 


l3]Din 


v ss [TT 


JT) cs 



(Top View) 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage to V ss Pin 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


PT 


1.0 


W 


Operating Temperature Range 


Topr 


to +70 


°C 


Storage Temperature Range 


Tug 


-55 to +125 


°C 



% HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 73 



HM6787 Se>rle>e 







" 


tts 


WE 


lj cc Curren! Mode 


C^uiput PMccCurreni 




W 


Mode 


l^cr: Current 


Output Pin 


M 


X 


Not Selected 


* St* ■ *sat 


High Z 


L 


II 


Rend 




I >o U 1 


L. 


L 


Write 




High Z 



Output Fin 



- RECOMMENDED DC OPERATING CONDITIONS (0 C < To < 70 C) 



Item 


Symbol 


mln 


typ. 




Unit 
V 


Supply Voltage 




4.5 


S «' 


s.s 


v&s 


O 


o 


o 


V 


Input High Voltigc 




2.2 




a 


V 


Input Low Volt blbc 




-OS*"" 




o.a 


V 



Mote) * 1. -3.0V for pulnc- wtdlh 20m 
- DC AND OPERATING CHARACTERISTICS < ^ctr ~ Wl IO%. 7„ 



■ 0"C to +70 C) 



It.-... 


Symbol 


Teat Condition* 


mln. 


typ. 




Unit 


Input Latakage Currant 


1 I L-l 1 


^ < (- - V5V, " f ,w <° ^CC 






2 


MA 


Output 1 rukiiKf t m it-ill 


I //,<-_>! 


CTS- Vmh- •'out- ,r> f<rc 






2 


"A 


Operating Power Supply Current 


'cc 


CS - "^/^ . OmA 






lOO 




Standby Power Supply Current 




«TS- 






40 




'.••••! 


C§«5 fr'c-C- -CIV 

»^r/vS0.2Vor t'wSl'cc-O IV 






20 


m A 


Output Low Voltage 




/oi. - 16mA 






O.S 


V 


Output High Voltage 


* ,>ii 


1 an ~ -4mA 


2.4 






V 



AC TEST CONDITIONS 
Input pulse (avals: \fss to 3.0V 
Input rise and fall timet: 4ns 
Input timing reference levels: 1.5V 

Output reference levels: 1 .BV 

Output load: See Figure 



Out put I I A 

+ SV 



Out put i .... i B 

IN* . It. * , 11V* St 

+- 5V 




- . »P' - 



Including ■ 



<tU> HITACHI 



■ CAPACITANCE (r a = 25°C,/=1.0MHz) 



Item 


Symbol 


max 


Unit 


Conditions 


Input Capacitance 


C /JV 


5.0 


pF 


K W =0V 


Output Capacitance 


CquT 


7.0 


PF 


Koot-OV 



Note) This parameter is sampled and not 100% tested. 



■ AC CHARACTERISTICS (K cc = 5 




• READ CYCLE 



Item 


Symbol 


HM6787-25 


HM6787-30 


Unit 


Notes 


min 


max 


min 


max 


Read Cycle Time 


'RC 


25 




30 




ns 




Address Access Time 


>AA 




25 




30 


ns 




Chip Select Access Time 


'ACS 




25 




30 


ns 




Output Hold from Address Change 


'OH 


5 




5 




ns 




Chip Selection to Output in Low Z 


tLZ 


5 




5 




ns 


1, 2 


Chip Deselection to Output in High Z 


*HZ 





15 





15 


ns 


1,2 


Chip Selection to Power Up Time 


tpu 












ns 


2 


Chip Deselection to Power Down Time 


*PD 




25 




30 


ns 


2 


Input Voltage Rise/Fall Time 


t T 




150 




150 


ns 


3 


Notes) 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

2. This parameter is sampled and not 100% tested. 

3. If tT becomes more than 150ns, there is possibility of function fail. 
Please contact your nearest Hitachi's Sale Dept. regarding specification. 

• WRITE CYCLE 


Item 


Symbol 


HM6787-25 


HM6787-30 


Unit 


Notes 


min. 


max. 


min. 


max. 


Write Cycle Time 


'WC 


25 




30 




ns 


2 


Chip Selection to End of Write 


'CW 


20 




25 




ns 




Address Valid to End of Write 


f AW 




25 




ns 




Address Setup Time 


*AS 












ns 




Write Pulse Width 


tWP 


20 




25 




ns 




Write Recovery Time 


tWR 


5 




5 




ns 




Data Valid to End of Write 


>DW 


20 




25 




ns 




Data Hold Time 


tDH 












ns 




Write Enable to Output in High Z 


'WZ 





15 





15 


ns 


3,4 


Output Active from End of Write 


'OW 












ns 


3,4 



Note: 1 . If CS goes high simultaneously with WE high, the output remains in a high impedance state. 

2. AU Write Cycle timings are referenced from the last valid address to the first transitioning address. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

4. This parameter is sampled and not 100% tested. 



<fj> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 75 



HM6787 Series 



• TIMING WAVEFORM OF READ CYCLE NO. 2 ' 



Address 



)( 



I 



tOH 



Data Out Previous Data Valid 

/ 



X X 



— 



Data Valid 



• TIMING WAVEFORM OF READ CYCLE I 



, 3) 



Data Out 



High Impedance 











Data Valid 



High Impedance 



Vcc Supply 



Ice 
he 



■50% 



50^ 



Note: 1 . WE is high and CS is low for READ cycle. _ 

2. Addresses valid prior to or coincident with CS transition low. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



HITACHI 

176 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



1 



• TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) 



Address 



C5 



WE 



Data In 



Data Out 





Iwc 

( ) 


( 




lew 




v — r 

V 


^ — . — I 


V 

tWR 


/ / / 

//// 




IAS 


IWP 

low — 


tint 4— 






Data In Valid 


)( 






Iwz 


tow 




/ High Impedance 


X 



Note: 1 . Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



• TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED) 



CS 



3c 



" \\\\\\\ 



Data In 



Data Out 



3( 



////// 



Data In Valid 



iwz 



Data Undefined 



High 



Note: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1619 • (415) 589-8300 



HM6787H Series 

65536-word x 1 bit High Speed Hi-BiCMOS Static RAM 



Features 

• Super Fast Access Time: 15ns/20ns (max.) 

• Low Power Dissipation (DC): 
Operating 210mW (typ) 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Balanced Read and Write Cycle Time 

• Fully TTL Compatible Input i 

Ordering Information 



Type No. 


Access Time 


Package 




HM6787HP-15 
HM6787HP-20 


15ns 
20ns 


300 mil 22 pin 
Plastic DIP 




HM6787HJP-15 
HM6787HJP-20 


15ns 
20ns 


300 mil 24 pin 
Plastic SOJ 




Block Diagram 




Memory Matrix 
128X512 



Din o- 
WE °~ 



Column I/O 
Column Decoder 



Vcc 
Vss 



r. Dout 



A„A„A„ 



Pin i 



HM6787HP Series 




a, [7 






*.r± 




1T]a,> 


A, [7 




jo] a,. 


Al[T 




1T]a,i 


A.|T 




7J]a„ 


As[T 




TJJai, 


Ai[T 




JJ] An 


A>(T 




71] A. 


Dou. [T 




77] ai 


we QT 




TT] Din 






TJJcs 




(Top View) 





HM6787HP Series 




(DP-22NB) 



Series 



(CP-24D) 




Note) The specifications of this device 
are subject to change without 
notice. 

Please contact Hitachi's Sales 
Dept. regarding specifications. 



HITACHI 

178 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6787H Series 



Absolute Maximum Ratings 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage to Vss Pin 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


Pf 


1.0 


W 


Operating Temperature Range 


Topr 


to +70 


°c 


Storage Temperature Range 


T stg 


-55 to +125 


s c 


Temperature under Bias 




-10 to +85 


°c 











Function Table 



CS WE Mode V cc Current Output Pin 



H X 


Not Selected 




ISB-ISBI 


High Z 




L H 




Read 




he feci 


Dout 




L L 





Write 




fee 'eel 


HighZ 




Recommended DC Operating Conditions (0°C ^ Ta ^ 70° C) 








Item 


Symbol 


min. 






typ. 




Unit 




v C c 


4.5 






5.0 5.5 




V 


Supply Voltage — 


Yss 














V 


Input High Voltage 


y,H 


2.2 






6.0 




V 


Input Low Voltage 


VlL 


-0.5 


•1 




0.8 




V 


Note) * 1. -3.0V for pulse width ^ 10ns. 












DC and Operating Characteristics (Vcc 


= 5V±10%, T a 


= 0°C to +70°C) 






Item 


Symbol 


min. typ. 


max. 


Unit 


Test Conditions 




Input Leakage Current 


l'u-1 




2 


MA 


K CC = 5.5V, V IN =V sst o 


vcc 




Output Leakage Current 


1'x.oi 




10 


(iA 


cs = v IH , V OUT =V ss to V CC 




Operating Power Supply Current 


Ice 




100 


mA 


CS= V IL , / ot/T =0mA 






Average Operating Current 


feci 




120 


mA 


Min. Cycle, Duty: 100% 


IquT~ m A 




I SB 




30 


mA 


CS=V IH 






Standby Power Supply Current 


f SBl 




10 


mA 


CS£P CC -0.2V 
V lN Z0.2V or Vni^Vcc 


-0.2V 




Output Low Voltage 


Vol 




0.4 


V 


Iol~ 8mA 






Output High Voltage 


VOH 


2.4 - 




V 


J OH = - 4m A 






















































HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6787H Series 



AC Test Conditions 

Input pulse levels: V$s to 3.0V 
Input rise and fall times: 4ns 
Input timing reference levels: 1.5V 
Output reference levels: 1.5V 
Output load: See Figure 



Output Load A 
+ 5V 



480 2 



Output Load B 
(for IHZ, ILZ, tvz & low) 
+ 5V 



■ 480 2 



Dout O- 



255 2 ; 



;30pF* 



Dout O- 



255 2 > ~ 5pF« 



777 



Including scops and jig. 



Capacitance (T„ = 25°C, /= 1 .0MHz) 



Item 


Symbol 


max. 


Unit 


Conditions 




Input Capacitance 


Cm 


6.0 


PF 


v w 


= OV 





Output Capacitance 


CquT 


10.0 


PF 


K o[/T = 0V 




Note) This parameter is sampled and not 100% tested. 












AC Characteristics (V C c = 5V±10%, T a =0°C to 70°C, unless otherwise noted.) 








Read Cycle 














Item 




HM6787H-15 


HM6787H-20 


— Unit 


Notes 




Symbol — 


min. max. 


min. max. 






Read Cycle Time 


>RC 


15 


20 


ns 






Address Access Time 


'AA 


IS 


20 


ns 






Chip Select Access Time 


'ACS 


15 


20 


ns 






Output Hold from Address Change 


'OH 


3 


3 


ns 






Chip Selection to Output in Low Z 


>LZ 


3 


3 


ns 


1,2 




Chip Deselection to Output in High Z 


'HZ 


6 


8 


ns 


1,2 




Note: 1 . This parameter is sampled and 100% tested. 

2. Transition is measured ±200mV from steady state voltage with spec 


ified loading in Loa< 


IB. 






Write Cycle 














Item 


Symbol 


HM6787H-15 


HM6787H-20 


Unit 






min. max. 


min. max. 


Notes 




Write Cycle Time 


'WC 


15 


20 




ns 


2 





Chip Selection to End of Write 


'CW 


10 


15 


ns 






Address Valid to End of Write 


'AW 


10 


15 


ns 






Address Setup Time 


'AS 








ns 






Write Pulse Width 


'WP 


10 


15 


ns 






Write Recovery Time 


'WR 


3 


3 


ns 






Data Valid to End of Write 


'DW 


12 


15 


ns 






Data Hold Time 


'DH 








ns 






Write Enable to Output in High Z 


'WZ 


6 


8 


ns 


3,4 




Output Active from End of Write 


'OW 








ns 


3,4 





Note: 1 . If CS~ goes high simultaneously with WE high, the output remains In a high impedance state. 

2. All Write Cycle timings are referenced from the last valid address to the first transitioning address. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

4. This parameter is sampled and not 100% tested. 



HITACHI 

1 80 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6787H Series 



Timing Waveform of Read Cycle No. I 1 *' 2) 



Address 



zx 



1 



Data Out Previous Data V.Iid 

^ 



X X X xz 



Data Valid 



Timing Waveform of Read Cycle No. 2 1 '* 3> 



CS 



Data Out 



High Impedance 



v( X)\ 



Data Valid 



High Impedance 



Note: 1 . WE ii high and CS is low for READ cycle. _ 

2. Addresses valid prior to or coincident with CS transition tow. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 181 



HM6787H Series 

Timing Waveform of Write Cycle No. 1 (WE Controlled) 



C5 



WE 



Data In 



Data Out 





tew 






A / 

tAW 


V, 

twft 


//// 




IAS 


tWP 

1 ' 

tDW - 


( 

lUH Urn 




X 


Data In Valid 


K 




twz 


tow 




D.t. Undefined / ZTZZ 

/ High Impedance 





Note: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



Timing Waveform of Write Cycle No. 2 (CS Controlled) 



Address 



CS 



Data In 



Data Out 





twe 








i 




MS 

tew 








\ / 


t 

tWR 




tAW 




tW 




WWW 


\ / 


'///// 






tDW 


IDH 










X- 


Data In Valid ^ 


i 


Data Undefined 


twz 

\ 





Note: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



182 



HITACHI 

America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6787HA 

1-Bit High Speed Static RAM 



65536-Word x 
■ FEATURES 



• Super Fast 

Access Time 

• Low Power Dissipation 

(DC) Operating 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Fully TTL Compatible Input and Output 

■ ORDERING INFORMATION 



.12/15/20ns (max.) 
. . . .300mW (typ.) 



Type No. 


Access Time 


Package 


HM6787HAP-12 


12ns 


300 mil 22 pin 


HM6787HAP-15 


15ns 


Plastic DIP 


HM6787HAP-20 


20ns 


(DP-22NB) 


HM6787HAJP-12 


12ns 


300 mil 24 pin 


HM6787HAJP-15 


15ns 


Plastic SOJ 


HM6787HAJP-20 


20ns 


(CP-24D) 



■ BLOCK DIAGRAM 



AgO- 
A 7 C- 
A e O- 
A5O- 
A4O- 
A3O- 



A 2 0- 



-cs: 

-cs: 
^§= 
-cs: 



Row 
Decoder 



Memory Matrix 
256x1024 



Column Decoder 



55 o- 
WEO- 



&3 



A I2 A 11 A 10 *9 A 14 A 15 A 1 *0 A 13 




(CP-24D) 



I 



■ PIN ARRANGEMENT 







An C 

AlC 
A2 C 
A3 C 
A4 □ 
As C 
NC □ 

a 6 r 

A7C 
Dout C 
WE □ 



1 
2 
3 
4 
5 
6 
7 
8 
9 

10 

11 



23 
22 
21 
20 
19 
18 
17 
16 
15 
14 



v *s 13p CS 



24 □ VCC 

□ A15 

□ A14 

□ A13 

□ A12 

□ NC 

□ A11 

□ A10 

□ A 9 

□ A 8 

□ Din 



(Top View) 



HM6787HAJP Series 



An C 
A1 C 

Az-E 
A3 C 
A 4 □ 
As C 

nc rz 

Ae C 

A7C 
Dout C 
WE □ 11 
V S S C 12 



24 □ VCC 
23 □ Ais 
22 □ A14 
21 HA13 
20 □ A12 
19 □ NC 
18 □ A11 
17 □ A10 
16 □ A 9 
15 □ A 8 
14 □ Din 
13 □ CS 



(Top View) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 83 



■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Voltage on Any Pin Relative to V ss 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


P T 


1.0 


w 


Operating Temperature Range 


Topr 


Oto +70 


°c 


Storage Temperature Range 


T slg 


-55 to + 125 


°c 


Temperature Under Bias 


T bias 


-10 to +85 


T 



■ RECOMMENDED DC OPERATING CONDITIONS (0°C < T a < 70°C) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


v ss 


0.0 


0.0 


0.0 


V 


Input High Voltage 


V IH 


2.2 




6.0 


V 


Input Low Voltage 


V,L 


-3.0* 




0.8 


V 



*Pulse width < 10ns, DC: -0.5V 
■ TRUTH TABLE 



CS 


WE 


Mode 


V C c Current 


Output Pin 


H 


X 


Not Selected 


!sb. Isbi 


HighZ 


L 


H 


Read 


!co !cci 


Data Out 


L 


L 


Write 


'cc Icci 


High Z 



DC AND OPERATING CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, V ss = 0V) 



Item 


Symbol 


Test Condition 


Min. 


Typ. 


Max. 


Unit 


Input Leakage Current 


iy 


V cc = 5.5V, V IN = V ss toV cc 






2 




Output Leakage Current 


HloI 


CS = V IH , V 0UT = V ss to V cc 






10 




Operating Power Supply Current 


I C c 


CS = V 1L , I OUT = 0mA 






100 


mA 


Average Operating Current 


Icci 


Min. Cycle Duty: 100%, I OUT = 0mA 






120 


mA 




'SB 


CS = V 1H 






30 


mA 


Standby Power Supply Current 


IsBl 


CS > V cc - 0.2V 

V IN < 0.2V or V, N > V cc - 0.2V 






10 


mA 


Output Low Voltage 


Vol 


I OL = 8mA 






0.4 


V 


Output High Voltage 


V OH 


•oh = -4mA 


2.4 






V 



■ AC TEST CONDITIONS 

• Input Pulse Levels: V ss to 3.0V 

• Input Timing Reference Levels: 1.5V 

• Output Load: See Figure 



• Input Rise and Fall Times: 4ns 

• Output Reference Levels: 1.5V 



+5 V 



Dout 



2550 




Dout 



255fi 




Output Load A 



Output Load B 
(for t HZ , t LZ , t wz & tow) 



"Including scope and jig capacitance. 



184 



Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6787HA Series 



■ CAPACITANCE (T a = 25°C, f = 1.0MHz) 



Item 


Symbol 


Max. 


Unit 


Conditions 


Input Capacitance 




6.0 


pF 


v, N = ov 


Output Capacitance 


C OUT 


10.0 


pF 


VquT = OV 



NOTE: This parameter is sampled and not 100% tested. 

■ AC CHARACTERISTICS (V cc = 5V ± 10%, T a to 0°C to 70°C, unless otherwise noted.) 
• Read Cycle 



Item 


Symbol 


HM6787HA-12 


HM6787HA-15 


HM6787HA-20 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


l RC 


12 




15 




20 




ns 




Address Access Time 


tAA 




12 




15 




20 


ns 




Chip Select Access Time 


'ACS 




12 




15 




20 


ns 




Output Hold from Address Change 


tOH 


4 




4 




4 




ns 




Chip Selection to Output in Low Z 


tLZ 


3 




5 




5 




ns 


1, 2 


Chip Deselection to Output in High Z 


l HZ 





6 





6 





8 


ns 


1,2 


NOTES: 1 . This parameter is sampled and not 100% tested. 

2. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

• Write Cycle 


Item 




Symbol 


HM6787HA-12 


HM6787HA-15 


HM6787HA-20 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


<wc 


12 




15 




20 




ns 


2 


Chip Selection to End of Write 


tew 


8 




10 




15 




ns 




Address Valid to End of Write 


l AW 


8 




10 




15 




ns 




Address Setup Time 


'AS 

















ns 




Write Pulse Width 


'wp 


8 




10 




15 




ns 




Write Recovery Time 


l WR 

















ns 




Data Valid to End of Write 


'dw 


7 




8 




10 




ns 




Data Hold Time 


'dh 

















ns 




Write Enable to Output in High Z 


l WZ 





6 





6 





8 


ns 


3,4 


Output Active from End of Write 


l ow 


3 




3 




3 




ns 


3,4 



NOTES: 1. If CS goes high simultaneously with WE high, the output remains in a high impedance state. 

2. All write cycle timings are referenced from the last valid address to the first transitioning address. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

4. This parameter is sampled and not 100% tested. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 85 



HM6787HA Series 



TIMING WAVEFORM 
I Cycle (1)0) (2) 



Address 



tRC 



x — 



tAA 



tOH 



Data Out Previous Data Valid ) (XXXX) C Data Valid ~^ ^ 







Read Cycle (2) 0)0) 



CS 



Data Out 



tRC 



tACS 



tLZ 



mm 



tHZ 



Data Valid 



High Impedence 



NOTES: 1 . WE is high and CS is low for READ cycle. 

2. Addresses valid prior to or coincident with CS transition low. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



"> 



High 



HITACHI 

1 86 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 



HM6787HA Series 



• Write Cycle (1 ) (WE Controlled) 



Address 

CS 

WE 

Data In 
Data Out 





iWC 




> 


< > 


< 




« tew ^ 












'/////////A 










< AS » 


t wp 


tWR 




?s / 


t 








> 


( Data In Valid } 


< 



Data Undefined 



tow 



High Impedance 



NOTE: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 87 



HM6787HA Series 



Write Cycle (2) (CS Controlled) 



Address 



CS 



Data In 
Data Out 



> 


( 'J 














/ 




< 








v/////////////, 




tDW 

f- — »~ 








Data In Valid ^ 


( 



twz 



Data Undefined 



5h 



High Impedance 



NOTE: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



— 



32768-word x 8-bit High Speed CMOS Static RAM 



FEATURES 

High Speed: Fast Access Time 85/1 00/1 20/1 50ns (max.) 
Low Power Standby and Low Power Operation; 
Standby: 200/liW (typ)/10/uW (typ) (L-version), 

Operation: 40mW (typ.) (f= 1MHz) 
Single 5V Supply 

Completely Static RAM: No clock or Timing Strobe Re- 
quired 

Equal Access and Cycle Time 

Common Data Input and Output, Three-state Output 
Directly TTL Compatible: All Input and Output 
Capability of Battery Back Up Operation (L-/L-SL version) 

ORDERING INFORMATION 



Type No. 


Access Time 


HM62256P-8 


85ns 


HM62256P-10 


100ns 


HM62256P-12 


120ns 


HM62256P-15 


150ns 


HM62256LP-8 


85ns 


HM62256LP-10 


100ns 


HM622S6LP-12 


120ns 


HM62256LP-15 


150ns 


HM62256LP-10SL 


100ns 


HM62256LP-12SL 


120ns 


HM62256LP-15SL 


150ns 


HM62256FP-8T 


85ns 


HM62256FP-10T 


100 ns 


HM62256FP-12T 


120ns 


HM62256FP-15T 


150ns 


HM62256LFP-8T 


85 ns 


HM62256LFP-10T 


100ns 


HM622S6LFP-12T 


120ns 


HM62256LFP-15T 


150ns 


HM62256LFP-10SLT 


100ns 


HM62256LFP-1 2SLT 


120ns 


HM62256LFP-15SLT 


150ns 



Package 



600 mil 28 pin 



HM62256P Series 




(DP-28) 



HM62256FP Series 




(FP-28DA) 



i PIN ARRANGEMENT 



28 pin 
Plastic SOP 



ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Voltage on any pin with relative to Vss 


V T 


-0.5 M to +7.0 


V 


Power Dissipation 


P T 


1.0 


w 


Operating Temperature 


Topr 


to +70 


°c 


Storage Temperature 


Tsll 


-55 to +125 


°c 


Temperature Under Bias 




-10 to +85 


°C 



Note) *1. -3.0V for pulse width g 50ns 



An(T ^ 


28] Vcc 


Al^jT 


27] WE 


At (T 


26Ja,j 


iifi 


25] A. 


As (T 


iTjA, 


A, (T 


23]An 


A3 (T 


22] OE 


A2 (T 


TTJaio 


Ai |T 


20] cs 


Ao [To 


TjTJi Ov 






I O, (jj 


TTji/os 


i 02 [n 


TJ]i/o. 




TJ]i/03 



(Top View) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



189 



■ BLOCK DIAGRAM 



X 

Address 
Buffer 



Row 
Decode i 



Memory Array 



512x512 



I/O0- 



1/07- 



1/0 
Bulfer 



WE- 

ot- 













Mm 


n Decoder 












Y Addret« Bailer 



AO A I A2 A10A3A4 



■ TRUTH TABLE 



cs~ 


OE 


WeT 


Mode 


V CC Current 


I/O Pin 


Reference Cycle 


H 


X 


X 


Not Selected 


1SB-ISB1 


HighZ 




L 


L 


H 


Read 


Ice 


Oout 


Read Cycle No. 1-3 


L 


H 


L 


Write 


Ice 


Din 


Write Cycle No. 1 


L 


L 


L 


Write 


lec 


Din 


Write Cycle No. 2 



X means H or L 

■ RECOMMENDED DC OPERATING CONDITIONS (T a = to +70°C) 



Item 


Symbol 


min. 


typ. 


max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


v S s 











V 


Input Voltage 


Kjh 


2.2 




6.0 


V 




-0.5*' 




0.8 


V 



Note) *1. -3.0V for pulse width g 50ns 

■ DC AND OPERATING CHARACTERISTICS (V CC = 5V ± 10%, V ss = 0V, T„ = to +70°C) 



Item 


Symbol 


Test Condition 


min 


typ*' 


max 


Unit 


Input Leakage Current 




VlN = YSS 'o VCC 






2 


MA 


Output Leakage Current 




CS= V/H or OE= V m oi WE=V IL> K/ /0 = V S S to V C C 






2 


ma 


Operating Power Supply Current 


ice 


CS = K /t ,// /o =0mA 




8 


15 


mA 


Average 

Operating 

Power 

Supply 

Current 


HM62256-8 


icci 


Min. Cycle, duty=100%, CS=V. L , // /o =0mA 




50 


70 


mA 


HM62256-10 




40 


70 


HM62256-I2 




35 


70 


HM62256-15 




33 


70 




r CC2 


CS = K /t , V IH =Vcc, K /t =0V,/ //o =0mA/=lMHZ 




8 


15 


mA 


Standby Power Supply Current 


>SB 






0.5 


3 


mA 


ISBl 


CS ^ K CC -0.2V, OV g V, N 




0.04 


2 


mA 




2*2 


100*2 


"A 




2*3 


50*3 


Output Voltage 


Vol 


/ oi = 2.1mA 






0.4 


V 


VOH 


I OH- -1.0mA 


2.4 




— 


V 



Notes) *1. Typical values are at Vqq- 5.0V, T a = 25°C and specified loading. 
*2. This characteristics is guaranteed only for L-version. 
*3. This characteristics is guaranteed only for L-SL version. 

HITACHI 

1 90 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



■ CAPACITANCE (r fl = 25°C,/=lMHz) 



Item 


Symbol 


Test Condition 


typ. 


max. 


Unit 


Input Capacitance 


c,„ 


K in = 0V 




6 


PF 


Input/Output Capacitance 


Q/o 


V I/o = 0\ 




8 


PF 



Note) This parameter is sampled and not 100% tested. 

■ AC CHARACTERISTICS (^ CC =5V± 10%, T a =0 to +70°C unless otherwise noted) 
• AC Test Conditions 



o Input pulse levels: 0.8V to 2.4V 
o Input rise and fall times: 5ns 



o Input and Output timing reference levels: 1.5V 
o Output load: 1TTL Gate and C L OOOpF) 
(Including scope and jig) 



• Read Cycle 



Item 


Symbol 


HM62256-8 


HM62256-10 


HM62256-12 


HM62256-15 


Unit 


min. 


max. 


min. 


max. 


min. 


max. 


min. 


max. 


Read Cycle Time 


'RC 


85 




100 




120 




150 




ns 


Address Access Time 


<AA 




85 




100 




120 




150 


ns 


Chip Select Access Time 


'ACS 




85 




100 




120 




150 


ns 


Output Enable to Output Valid 


'OE 




45 




50 




60 




70 


ns 


Output Hold from Address Change 


'OH 


5 




10 




10 




10 




ns 


Chip Selection to Output in Low Z 


'CLZ 


10 




10 




10 




10 




ns 


Output Enable to Output in Low Z 


'OLZ 


5 




5 




5 




5 




ns 


Chip Deselection to Output in High Z 


'CHZ 





30 





35 





40 





50 


ns 


Output Disable to Output in High Z 


IOHZ 





30 





35 





40 





50 


ns 



• Timing Waveform of Read Cycle No. I 11 ' 



ress 



}< 



tRC 



tAA 



OE 



CS 



Dout 



tOE 



tpLZ 



tACS - 

-tCLZ 



//////// 



tOH 



-toHZ- 
-tCHZ— 



Data Valid 



• Timing Waveform of Read Cycle No. 2 U) (2) [4 ' 



Address 



Dout 





tRC 

( ) 


( 




tAA 




tOH 




tOH 






) 


cxxxxxx 1 


{ Data Valid ^ 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Timing Waveform of Read Cycle No. 3 [1) 131141 

CS 



Dout 



tCLZ 



-tACS- 



tCHZ 



Data Valid 




> 



Notes) 1 . WI is High tor Read Cycle. 

2. Device is continuously selected, CS = V^. 

3. Address Valid prior to or coincident with CS transition Low. 

4. 0E = V IL . 







• Write Cycle 



Item 


Symbol 


HM62256-8 


HM62256-10 


HM62256-12 


HM62256-15 


Unit 


min. 


max. 


min. 


max. 


min. 


max. 


min. 


max. 


Write Cycle Time 


'WC 


85 




100 




120 




150 




ns 


Chip Selection to End of Write 


tew 


75 




80 




85 




100 




ns 


Address Valid to End of Write 


'AW 


75 




80 




85 




100 




ns 


Address Set Up Time 


'AS 






















ns 


Write Pulse Width 


'WP 


60 




60 




70 




90 




ns 


Write Recovery Time 


'WR 


10 



















ns 


Write to Output in High Z 


'WHZ 





30 





35 





40 





50 


ns 


Data to Write Time Overlap 


WW 


40 




40 




50 




60 




ns 


Data Hold from Write Time 


'DH 






















ns 


Output Disable to Output in High Z 


'OHZ 





30 





35 





40 





50 


ns 


Output Active from End of Write 


tnw 


5 




5 




5 




5 




ns 



• Timing Waveform of Write Cycle No. 1 (OE Clock) 



Address ~\{ 

OE 

CS 

WE 



twe 



tew 



-tAS- 



tOHzW 



tAW 



X 



— 



///// // 



twp CO 



/ 



Dout 



Din 







tDW 



tDH 



HITACHI 

1 92 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM62256 Series 



• Timing Waveform of Write Cycle No. 2 [5) (OE Low Fixed) 



Address 



C5 



WE 



Dout 



twc 







tew 



fll/'U) 



1 



tWHZ 



[.-{] 



))))))>)))))> ! 







[2) 

t\VK 



7 



(6) 



(7] 



Notes: 1 A write occurs during the overlap (Iwp) of a low C5 and a low WE. 

2. t WR is measured from the earlier of CS or WE going high to the end of write cycle. 

3 During this period. I/O pins are in the output state. Thejnput signals out of phase must not be applied 

4 If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, 
outputs remain in a high impedance state. 

5. OE is continuously low. (OT = Vii) 

6. Dout is in the same phase of written data of this write cycle. 

7. Dout is the read data of next address. 

8. If CS is low during this period, I/O pins are in the output state. The input signals out of phase must not be 
applied to I/O Pins. 

■ LOW V C c DATA RETENTION CHARACTERISTICS (T a = to +70°C) 
(This characteristics is guaranteed only for L-and L-SL version) 



Item 


Symbol 


Test Conditions 


min. 


typ. 


max. 


Unit 


Vcc for Date Retention 


Vdr 


CS S Vqq -0.2V 


2.0 






V 


Data Retention Current 


! CCDR 


Vcc " 3-OV, CS ^ 2.8V 






50* 1 




ov g V ln 






10* 3 


MA 


Chip Deselect to Data Retention Time 


>CDR 


See Retention Waveform 









ns 


Operation Recovery Time 


tR 


tRC*> 






ns 



Note) *1. fyjc = Read Cycle Time 
•2. This characteristic is f 
•3. This characteristic is f 



• Low V cc Data Retention Waveform 

Vcc 



i for L-version, 20mA max. at T„ = to 40°C. 
' for L-SL version, 3mA max. at T a = to 40°C. 



DATA RETENTION MODE 




0V-- 



Note) In Data Retention Mode, CS controls the Address, WE, OE, and Din Buffers. Vin for these inputs can be in 
high impedance state in data retention mode. 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 93 



HM62256 Series 



SUPPLY CURRENT vs. SUPPLY VOLTAGE (1) SUPPLY CURRENT vs. AMBIENT TEMPERATURE (1) 



I * 



_ 1.0 

i 

■a °- ; 



0.4 









To=25"C 











































4.75 5.00 5.25 

Supply Voll«e Vcc (V) 



,50 









y cc = 5.ov 











































20 40 60 

Ambient Tempenture To CO 



SUPPLY CURRENT vs. SUPPLY VOLTAGE (2) SUPPLY CURRENT vs. AMBIENT TEMPERATURE (2) 









r« = 25T 

















































V CC = 5.0V 











































Supply Volume V c c (V) 



To CO 



SUPPLY CURRENT vs. SUPPLY VOLTAGE (3) SUPPLY CURRENT vs. AMBIENT TEMPERATURE (3) 



I 1 

Jf 1.0 

1 









To = 25T 











































I 

(J 

>■ 0.9 



5.50 









Vcc" 5.0V 











































Supply Voltage V„ (V) 



Ambient Temperature To I'CI 



HITACHI 

1 94 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM62256 Series 




4.50 4.75 5.00 5.25 5.50 20 40 60 80 



Supply Vcjuwe V cc IV 1 AmbienlT.mper.lure Ta ("Cf 

STANDBY CURRENT vs. SUPPLY VOLTAGE STANDBY CURRENT vs. AMBIENT TEMPERATURE 




Frequency / I MHz i Frequency / I MHz I 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 95 



HM62256 Series 



INPUT LOW VOLTAGE vt. SUPPLY VOLTAGE 



INPUT HIGH VOLTAGE vs. 
SUPPLY VOLTAGE 





L2 


1 




o 

35 


1.1 






1 






10 






1 






0.9 


* 








5 






8 









7<i 25'C 











































1 

* 0.8 



4.75 5.00 5.25 5.50 

Suppl, Vollw V cr iV 









T« 25'C 











































4.50 4.75 5.00 5.25 5.50 

Supply VollaBP fe V 



OUTPUT CURRENT w. 
OUTPUT VOLTAGE 



OUTPUT CURRENT w. 
OUTPUT VOLTAGE 





1 6 




1.4 






1 

o 






1.2 












10 


u 










5 








0.6 











\ 






















T.=SC 
Vcc 5.0V 






















1 


s 




Output HtRh 



0.2 0.4 
Output Low Volune Vm 'V. 



ACCESS TIME™. LOAD CAPACITANCE 



J 

1 1.4 



200 




jar 



Load Capacitance C L 'pFi 



HITACHI 

1 96 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM62832/HM62832H 

8-Bit CMOS Static RAM 

32768-WORD x 8-BIT HIGH SPEED CMOS STATIC RAM 
■ FEATURES 

• High speed: Fast Access time 25/35/45 ns (max.) 

HM62832— Low power 

Standby: 10 /.W (typical) (L-version) 
Active: 300 mW (typical) 



Standby: 300 mW (typical) 
Active: 30 /iW (typical) (L-version) 

• Single 5V supply 

• Completely static memory 

No clock or timing strobe required 

• Equal access and cycle times 

• Common data input and output— Three stage output 

• Directly TTL compatible— All inputs and outputs 

■ ORDERING INFORMATION 



(DP-28NA) 



(CP-28DN) 



Part No. 


Access 


Package 


HM62832P-35 


35 


ns 




HM62832P-45 


45 


ns 


300 mil 28-pin 


HM62832LP-35 


35 


ns 


Plastic DIP 


HM62832LP-15 


45 


ns 




HM62832JP-35 


35 


ns 




HM62832JP^5 


45 


ns 


300 mil 28-pin 


HM62832UP-35 


35 


ns 


Plastic SOJ 


HM62832UP-45 


45 


ns 




HM62832HP-25 


25 


ns 


300 mil 28-pin 


HM62832HP-35 


35 


ns 


Plastic DIP 


HM62832HP^»5 


45 


ns 


(DP-28NA) 


HM62832HJP-25 


25 


ns 


300 mil 28-pin 


HM62832HJP-35 


35 


ns 


Plastic SOJ 


HM62832HJP-45 


45 


ns 


(CP-28DN) 



PIN ARRANGEMENT 



Top View 



A14 □ 




28 


□ v cc 


A12 C 


2 


27 


□ WE 


A7C 


3 


26 


□ A13 


A6 C 


4 


25 


□ Ae 


AsC 


5 


24 


□ A 9 


A4 C 


6 


23 


□ An 


A3 [I 




22 


□ 01 


AaC 


8 


21 


□ A,o 


Alt 


9 


20 


□ CS 


AoC 


10 


19 


□ 1/07 


i/oo C 


11 


18 


□ i/Oe 


i/o, C 


12 


17 


□ i/o 5 


l/0 2 □ 


13 


16 


□ i/o 4 


vss tl 


14 


15 


□ 1/O3 



PIN DESCRIPTION 



Pin Name 


Function 


An- A 14 


Address 


I/O0-I/O7 


Input/Output 


CS 


Chip Select 


WE 


Write Enable 


51 


Output Enable 


Vcc 


Power Supply 


Vss 


Ground 



<§► HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 97 



HM62832/HM62832H - 



■ BLOCK DIAGRAM 



A12 — 
A14 - 
AS 

A13 I 
A9 I 
An | 
AS . 

8 -I 















X 


1 


Row 


l 


Address 


1 


Decoder 


I 


Buffer 


1 
1 




I 











Memory Array 



l/OO 
1/07 



WE 

OE 

CS 



I/O 
Buffer 



Column Decoder 



Y Address Buffer 



TT 



A0A1 A2A3A10A3A4 



■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Value 


Unit 


Voltage on any Pin Relative to V ss 


v T 


-0.5* 1 to + 7.0 


V 


Power Dissipation 


Pt 


1.0 


W 




Operating Temperature 


T 

■opr 


to +70 


°c 





Storage Temperature 


Tslg 


-55 to + 125 


°c 


Storage Temperature Under Bias 


T bias 


-10 to +85 


°c 



NOTE: I -2.5 V for pulse widlh : 

■ FUNCTION TABLE 



CS 


OE 


WE 


Mode 


V cc Current 


I/O Pin 


Ref. Cycle 


H 


X 


X 


• Not Selected 


'sb- 'sbi 


HighZ 




L 


L 


H 


Read 


Ice 


Do,,, 


Read Cycle" >«" 3 > 


L 


H 


L 


Write 


I cc 


D,n 


Write Cycle 1 " 


L 


L 


L 


Ice 


D in 


Write Cycle' 2 ' 



I . X : H or L 



<^ HITACHI 

198 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM62832/HM62832H 



■ DC CHARACTERISTICS for HM62832 (T A = Oto +70°C, V cc = 5V ± 10%, = 0V) 



Parameter 


Symbol 


Min. 


Typ" 


Max. 


Unit 


Test Conditions 


Note 


Input Leakage Current 


w 






10 


fiA 


V in = V ss to V cc 




Output Leakage Current 


UloI 






10 


MA 


CS = V, H or OE = V IH 
or WE = Vn,, 
Vi/o = Vss to Vcc 




/WCIagC vspCRIllIlg njwci 

Supply Current 

1 


Ice 


— 


60 


120 


mA 


Min. cycle, duty = 100%, 
CS - V IL , 
I l/0 = mA 





Standby V cc Current 






15 


30 


mA 


CS = V IH 




tm 




2 


100 


*A 


CS 2 V cc - °- 2V , 

V s V„, s 0.2 V, 
orV,,, a V re -0.2V 


L-version 


Output Voltage 


Vol 






0.4 


V 


Iol = 8 mA 




V 0H 


2.4 






V 






NOTE: 1 . Typical values are at Vcc = 5.0 V, Ta = +25°C and specified loading. 

■ DC CHARACTERISTICS for HM62832H (T A = to +70°C, V cc = 


5V ± 10%,V SS = 0V) 


Parameter 


Symbol 


Min. 


Typ." 


Max. 


Unit 


Test Conditions 


Note 


Input Leakage Current 


iU 






2 




V in - Vss to V cc 




Output Leakage Current 


UloI 






2 


*A 


CS = V 1H or OE = V IH 
orWE = Vu., 
v i/o = v ss to V cc 




Operating Power Supply Current 




Ice 




60 


120 


mA 


Min. cycle, duty = 100%, 
CS = V, L , 
I I/0 = mA 




Standby Power Supply Current 


l SB 




15 


30 


mA 


CS = V, H 






■SBI 




0.02 


2 


mA 


CS 2 Vcc - 0.2V, 
V s V in £ 0.2 V, 
orV in , 2 Vc,. -0.2 V 








0.006 


0.1 


mA 


L-version 


Output Voltage 


Vol 






0.4 


V 


I OL = 8 mA 




Voh 


2.4 






V 


•oh = -*mA 





NOTE: I . Typical values are at V C C = 5.0 V. T A = +25"C and specified loading. 



■ CAPACITANCE (T a = 25°C, f = 1MHz) 



Parameter 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test Conditions 


Input Capacitance 








6 


pF 


V m = V 


Input/Output Capacitance 


c i/o 


— 




10 


pF 


V„ o =0V 



NOTE: I . This parameter is sampled and not 100% tested. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 1 99 



HM62832/HM62832H - 



■ AC CHARACTERISTICS (T a = to +70°C, V cc = 5 V ± 10%, unless otherwise noted.) 
Test Conditions 



• Input pulse levels: 0.0 V to 3.0 V 

• Input rise and fall times: 5 ns 



Input and output timing reference 
• Output load: See Figures 



1.5 V 



Output Load (A) 



Dout 
255 




Output Load (B) 
(for Xcu. to L7 . tc Hz . toHZ- 'whz & tow* 

+5V 



30 pF* 






NOTE: 'Including scope & jig. 


















■ Read Cycle 


















Parameter 


Symbol 


HM62832H-25 


HM62832-35 
HM62832H-35 


HM62832^t5 
HM62832H^»5 


Unit 






Min. 


Max. 


Min. 


Max. 


Min. 


Max. 




Read Cycle Time 


tRC 


25 




35 




45 




ns 


Address Access Time 


tAA 




25 




35 




45 


ns 


Chip Select Access Time 


tACS 




25 




35 




45 


ns 


Output Enable to Output Valid 


tOE 




12 




15 




20 


ns 


Output Hold From Address Change 


■oh 


5 




5 




5 




ns 


Chip Selection to Output in Low-Z 


>CLZ 


5 




5 




5 




ns 


Output Enable to Output in Low-Z 


tOLZ 

















ns 


Chip Deselection to Output in High-Z 


tcHZ 





12 





15 





15 


ns 


Output Disable to Output in High-Z 


k)HZ 





12 





15 





15 


ns 



Read Cycle Timing (2) "% "2. ** 



Read Cycle Timing (1) "1 



) 


t 


i! 


\\\ 








A V 


S k 








/// 






:x) 


^ Daia Val«J 





> 




< 












c 


) 


(XXXXXX) 





Cycle Timing (3) *1. '3, *4 



MM 



NOTES: • 1 . WE is high for read cycle. 

*2. Device is continuously selecied, CS = Vjl 

•3. Address should be valid prior io or coincident with CS transition It 

•4 OE - V| L . 



HITACHI 

200 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM62832/HM62832H 



Write Cycle 



Item 


Symbol 


HM62832H-25 


HM62832-35 
HM62832H-35 


HM62832^t5 
HM62832H-45 


Unit 






Min 


Max 


Min 


Max 


Min 


Max 




Write Cycle Time 


'wc 


25 




35 




45 




ns 


Chip Selection to End of Write 


•cw 


20 




30 




40 




ns 


Address Valid to End of Write 


<AW 


20 




30 




40 




ns 


Address Setup Time 


'as 




















ns 


Write Pulse Width 


'wp 


15 




20 




25 




ns 


Write Recovery Time 


'WR 

















IIS 


Write to Output in High-Z 


•WHZ 





15 





15 





20 


ns 


Data to Write Time Overlap 


<DW 


12 




15 




20 




ns 


Data Hold from Write Time 


'dh 

















ns 


Output Disable to Output in High-Z 


'OHZ 





12 





15 





20 


ns 


Output Active From End of Write 




5 




5 




5 




ns 



Write Cycle Timing (1) (OE Clock) 



7ZX 



WE 



5 Si 



' /77T777, 



ZEE 



XXX 



Write Cycle Timing (2) (OE Low Fixed) 



cs 

WE 













> 

Si 


2 




" * =n 


V, 


V/////, 






t 


. "» . 


f / / / / / / / / f f f ^ 
< 





*l . A wriic occurs during the overlap (twp) of a low CS and a low WE. 

•2. Iwr is measured from the earlier of CS or WE going high to (he end of write cycle. 

*3. During this period. I/O pins are in the output state. The input signals out of phase must not be applied. 

*4. If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain in a high impedance si 

*5. OE is continuously low. (OE = V iL ). 

*6. Do„i is in the same phase of written data of this write cycle. 

•7. D«fl is the read data of next address. 

*8. If CS is low during this period. I/O pins arc in the output state. The input signals out of phase must not be applied to I/O pins. 
*9. WE must be high during all address transitions except when device is deselected with CS. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



201 



HM62832/HM62832H 



■ Low Vcc Data Retention Characteristics (T A = to +70°C) 
This characteristics is guaranteed only for L-version 



Parameter 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test Conditions 


V cc for Data Retention 


V DR 


2.0 






V 




Data Retention Current 


■CCDR 




1 


50' 2 


pA 


CS 2 V cc - 0.2 V, 
V in > V cc -0.2 V or 
V < V in s 0.2 V 


Chip Deselect to Data Retention Time 


■CDR 









ns 


Operation Recovery Time 


l RC 


tRC*' 






ns 





NOTES: * I . IRC = read cycle lime. 
•2. V C C - 3.0 V. 




HITACHI 

202 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 




4-Bit CMOS 



Series 
RAM 



65536-Word x 4-Bit High Speed CMOS Static RAM 

The Hitachi HM6208 and HM6208H are high speed 256k static 
RAMS organized as 64k-word x 4 bit. They realize high speed 
access time (25/35/45 ns) and low power consumption, employing 
CMOS process technology and high speed circuit designing 
technology. It is most advantageous wherever high speed and high 
density memory is required, such as the cache memory for main 
frame or 32-bit MPU. 

The HM6208 and HM6208H are packaged in the industry 
standard 300-mil, 24 pin, plastic DIP. The HM6208H is also 
available in a 300-mil, 24 pin, plastic SOJ package for high density 
mounting. The low power versions are ideal for battery backed 
systems. 

Features 

• Single 5 V supply and high density 24-pin package 

• High speed: Access time 25/35/45 ns (max.) 




Low power 
Active: 
Standby: 



300 mW (typ.) 
100 (typ.) 
30 jiW (typ.) (L-version) 

• Completely static operation requires 

No clock or timing strobe 

• Access and cycle times are equivalent 

• All inputs and outputs TTL compatible 

• Capability of battery back up operation (L-version) 

Ordering Information 




(CP-24D) 



Pin Arrangement 



Type No. 



Access Time 



Package 



HM6208P-35 
HM6208P-45 




35 ns 
45 ns 




HM6208LP-35 
HM6208LP-45 




35 ns 
45 ns 


300-mil 
24-pin 


HM6208HP-25 
HM6208HP-35 




25 ns 
35 ns 


plastic DIP 
(DP-24NC) 


HM6208HLP-25 
HM6208HLP-35 




25 ns 
35 ns 




HM6208HJP-25 
HM6208HJP-35 




25 ns 
35 ns 


300-mil 
24-pin 


HM6208HLJP-25 
HM6208HLJP-35 




25 ns 
35 ns 


plastic SOJ 
(CP-24D) 


Pin Description 






Pin Name 


Function 






AO- A15 


Address 






I/Ol -I/04 


Inpu [/Output 






CS 


Chip select 






WE 


Write enable 








Power supply 




Vss 


Ground 







AO [T ^- 


"»*} v„ 


AI 


~u\ A15 


A2[T 


IT] A14 


A3 |jT 


"zT] A13 


A" Li 


lo] A12 


A5 [V 


"jT"} All 


A6 


IT] A10 


A7 [V 


"iT| i/oi 


AS [jT 


"l6~| l/OZ 


A9 


t/03 


cs QT 


"i<"| 1/04 


Le 




(Top View) 



0HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



203 



HM6208/HM6208H Series - 

Block Diagram 



















Function Table 












Mode 


Vcc Current 


I/O Pin 


Rcf. Cycle 


H x 


Not selected 


Isb, Isri 


High-Z 




L H 


Read 


Ice 


Dout 


Read cycle 


L L 


Wrile 


Ice 


Din 


Write cycle 



Note: x means don't care. 

Absolute Maximum Ratings 



hem 


Symbol 


Value 


Unit 


Voltage on any pin relative to Vss 


Vin 


-0.5 -1 to +7.0 


V 


Power dissipation 


Pt 


1.0 


w 


Operating temperature range 


Topr 


to +70 


°c 


Storage temperature range 


Tstg 


-55 to +125 


°c 


Storage temperature range under bias 


Tbias 


-10 to +85 




°c 


Note: *1. Vin min= -2.5 V for pulse widths 10 ns. 









HITACHI 

204 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6208/HM6208H Series 



Recommended DC Operating Conditions (Ta = to +70°C) 



Item S 


ymbol 


Min 


Typ 


Max 


Unit 




Vcc 


4.5 


5.0 


5.5 


V 


Supply voltage 


Vss 


n 
u 









y 


Input high (logic 1) voltage 


Vm 


2.2 






6.0 


V 


Input low (logic 0) voltage 


Vu. 


-0.5 M 






0.8 


V 


Note: •!. Vu.min = -2.0 V for pulse widths 10ns. 












■ DC Characteristics (T a = o to +70°C. v C c 


= 5 V ± 10 


*. V SS = V) 






Item 


Symbol 


Min. 


Typ.' 1 


Max. 


Unit 


Test Conditions 


Input Leakage Current 


lu 


— 




2.0 


(■A 


fee = Max. 


Output Leakage Current 


Ilo 






10 


~fh 


CS = V 1H 

V m = V ss to Vcc 


Operating Power Supply Current 


lec 


- 


60 


100 


111 A 


CS = V„ . l m = mA. 
Min. Cycle. Duty = 1005f 


Standby Power Supply Current 


I SB 




15 


30 


mA 


CS = V, H . Min. Cycle 


Standby Power Supply Current "H" Version 


I SB 




20 


40 


mA 


Standby Power Supply Current 


'SBI 




20 


2000 


dA 


CS ■* Vcc " 2 V 
V < V„, s 0.2 Vor 
V in 2 V„.-0.2V 


Standby Power Supply Current L- Version 


'SBI 




6 


100 


/•A 


Output Low Voltage 


Vol 






0.4 


V 


— 8 mA 


Output High Voltage 


Voh 


2.4 






V 


'oh = -4 mA 


Note: •!. Typical limits arc at V cc = 5.0 V. T, = +25°C and specified loading. 








Capacitance (Ta = 25°C, f = 1MHz)' 1 










hem Symbol Min 


Max 


Unit 


Test Conditions 


Input capacitance Cin 






6 


pF 




Vin = V 


Input/output capacitance Ci/o 






10 


PF 




Vi/o = 0V 


Note: *1. This parameter is sampled and not 100% tested. 










AC Characteristics (Ta = to +70°C, Vcc 


= 5 V ± 10%, unless otherwise noted.) 




Test Conditions 














• Input pulse levels: Vss to 3.0 V 




Input and output timing reference levels : 1 .5 V 


• Input rise and fall times: 5 ns 




• Output load: See Figures 




Output Load (A) 






Output Load (B) 












for BIZ, tLZ, 


twz & low) 


»sv 














> 110 2 








Smob 


















DwlO t • 








»<o £ 






™H 








' 

















Note: * Including scope & jig. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 05 



HM6208/HM6208H Series 



Read Cycle 



Item 


Symbol 


HM6208H-25 


HM6208-35 
HM6208H-35 


HM6208-45 


Unit 






Min. 


Max. 


Min. 


Max. 


Min. 


Max. 




Read Cycle Time 


I.RC 


25 





35 





45 





ns 


Address Access Time 






25 




35 




45 


ns 


Chip Select Access Time 


*ACS 




25 




35 




45 


ns 


Output Hold From Address Change 


'OH 


S 




5 




5 




ns 


Chip Selection to Output in Low-Z 


iLZ* 1 


5 




5 




5 




ns 


Chip Deselection to Output in High-Z 


1HZ' 1 





12 





20 





20 


ns 


Chip Selection to Power Up Time 


'PU 

















ns 


Chip Deselection to Power Down Time 


<PD 




15 




25 




30 


ns 



Note: •! Transition is measured ±200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 



Read Timing Waveform (1) 



X 



X 



X 



3IC 



— 



Read Timing Waveform (2) ''• -3 




Notes: M. WE is high for read cycle. 

♦2. Device is continuously selected, CS = Vn,. 

*3. Address valid prior to or coincident with CS transition low. 



HITACHI 

206 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Write Cycle 



Item 




Symbol 


HM6208H-25 


HM6208-35 
HM6208H-35 


HM6208-45 


Unit 








Min. 


Max. 


Min. 


Max. 


Min. 


Max. 




Write Cycle Time 


*wc 


25 


_ 


35 


_ 


45 


_ 


ns 


Chip Selection to End of Write 


tew 


20 


_ 


30 


_ 


40 


_ 


ns 


Address Valid to End of Write 


*AW 


20 


_ 


30 


_ 


40 


— 


ns 


Address Setup Time 


'AS 





— 





— 





— 


ns 


Write Pulse Width 




iwp 


20 




30 




35 




ns 


"H" Version 




25 






Write Recovery Time 


t\VR 


3 




3 




3 




ns 


Data Valid to End of Write 


•dw 


15 




20 




20 




ns 


Data Hold Time 


•dh 

















ns 


Write Enabled to Output in High-Z 


<wz*' 





8 





10 





15 


ns 


Output Active From End of Write 


'ow*' 

















ns 



Note: *l Transition is measured ±200 mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested. 



Write Timing Waveform (1) (WE Controlled) 



) 


< > 


< 










\\\ 


\\ > 


'///a 


'///// 




[,» 

^ - . . i„ •! 








\\v 


\ / 


la* I 






Data Valid 




1 R • 3 

/ / \ u._t r a 


>(X> 








ITACHI 



Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 207 



HM6208/HM6208H Series - 



Write Timing Waveform (2) (CS Controlled) 



) 


!J= 

< > 


( 










•- 


It. 






I 


wwww 


^ ? 


'/?/////// 




Im 


X — XXXXXXX 



H«h Im^d.ncc »4 



HITACHI 

208 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



- HMR?r>R/HMR?nRH Rnrifif; 



Low Vcc Data Retention Characteristics (T a = to +70°C) 
These characteristics are guaranteed only for L-version. 



Item 



Symbol Min Typ Max Unit 



Test Conditions 



Vcc for data retention 



Vox 



2.0 



— — V 



Data retention current 


Iccdr 




1 50 ' 2 uA 




Chip deselect to data retention time 


tCDR 





— — ns 




Operation recovery time 


tR 


Kc" 


— — ns 





CS > Vcc - 0.2 V. 
Vin>Vcc-0.2 V( 
0V< Vin<0.2V 



Notes: *1. ttc = read cycle time. 
•2. Vcc = 3.0 V. 

Low Vcc Data Retention Timing Waveform 



Data retention mode 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



209 




# HITACHI 

21 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 



HM6708 Series 



65536-word x 4-bit High Speed Hi-BiCMOS Static RAM 



Features 

• Super Fast Access Time : 20725ns (max.) 

• Low Power Dissipation 
Operating: 350mW (typ.) (f = 50MHz) 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Balanced Read and Write Cycle Time 

• Fully TTL Compatible Input and Output 



Ordering Information 






Type No. 


Access Time 


Package 


HM6708P-20 
HM6708P-25 


20ns 
25ns 


300mil 24 pin 
Plastic DIP 


HM6708JP-20 
HM6708JP-25 


20ns 
25ns 


300 mil 
24 pin SOJ 


Block Diagram 



A o- 
Ai o- 
A 2 o- 
A 3 o- 
A 4 o- 
A50- 
A90- 
Aio^- 



2= 



Row 
Decoder 



Memory Matrix 
256X1024 





v cc 



Vss 



I/Oio- 
I/0 2 °- 
I/O30- 
I/O40. 



_£3o- 



7&- 

Input 
. Data 
_|s > _ Control 



Column I/O 



Column Decoder 



A 6 A 7 A 8 An A 12 Ai3A 14 Ai5 



EE 



— 



HM6708P 




(DP-24NC) 



HM6708JP 




(CP-24D) 



Pin 



A C 


1 


24 




Alt 


2 


23 


□ A,5 


A 2 C 


3 


22 


□ A 14 


A 3 C 


4 


21 


□ A 13 


A 4 C 


5 


20 


□ A 12 


A5C 


6 


19 


□ A U 


A 6 C 


7 


18 


□ A I0 


A 7 C 


8 


17 


□ I/O, 


A 8 C 


9 


16 


□ I/0 2 


A 9 C 


10 


15 


3I/O3 


CSC 


11 


»4 


□ I/O4 




12 


13 


□ WE 



(Top View) 



Note) The specifications of this device are subject to change without notice. 
Please contact Hitachi's Sales Dept. regarding specifications. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 21 1 



Absolute Maximum Ratings 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage to V ss Pin 


v T 


-0.5 to +7.0 


V 


Power Dissipation 


p T 


1.0 


w 


Operating Temperature Range 


Topr 


to +70 


°c 


Storage Temperature Range (with bias) 


^s^(bias) 


-10 to +85 


°c 


Storage Temperature Range 


T,tg 


-55 to +125 


°c 



Recommended DC Operating Conditions (T a = to +70°C) 



Item 


Symbol 


min. 


typ- 


max. 


Unit 


Supply Voltage 


v C c 


4.5 


5.0 


c c 

J J 


V 


v S s 











V 


Input Voltage 


Vm 


2.2 




6.0 


V 


Vii 


-0.5" 




0.8 


V 


Note) .1. -3.0 V for pulse width 20ns. 










Function Table 












cs we 


Mode 






I/O Pin 


Ref. Cycle 


Vcc Current 




H X 


Not selected 






HighZ 




L H 


Read 


I co ha 




Data Out 


Read Cycle 


L L 


Write 


ice- feci 




Data In 


Write Cycle 


DC and Operating Characteriiti 


« (V C C * 5 V±10% 


, T a = to +70°C) 






Item 


Symbol min. typ. max. 


Unit 


Test Conditions 


Input Leakage Current 




2 


MA 


V CC ' 5.5V, V IN -V SS to V CC 


Output Leakage Current 


I/to' 


10 


ma 


CS'V m ,Vi /0 


« v ss to Vcc 


Operating Power Supply Current 


Ice 


100 


mA 


CS-Vu.,I I/0 ' 


mA 


Average Operating Current 


feci 


120 


mA 


Min. Cycle, Duty: 100%, ///o* 0mA 


Standby Power Supply Current 


fsB 


30 


mA 


CS-V m ,V IN =V IH oiV IL 


ISBI 


10 


mA 


CS £ Vcc-0-2 V 

V JN g 0.2 V or V IN Z Vcc-0.1V 


Output Low Voltage 


Vol 


0.4 


V 


Iql = 8 mA 




Output High Voltage 






V 















HITACHI 

21 2 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



-HM6708 Series 



Capacitance {j a = 25°C,/ = 1 MHz) 



Item 


Symbol 


max. 


Unit 


Test Conditions 


Input Capacitance 


C IN 


6.0 


PF 


V IN = 0V 


Input/Output Capacitance 


c i/o 


10.0 




V I/O = 0V 



Note) This parameter is sampled and not 100% tested. 



AC Characteristics (y cc = 5 v ±10%, T a = to +70°C, unless otherwise noted) 
AC Test Conditions 

• Input pulse levels : K55 to 3.0 V 

• Input timing reference levels : 1 .5 V 

• Output Load : See Figure 

• Input rise and fall times : 4 ns 

• Output reference levels :1.5V 



Output 
O 



2550.1 



+ 5V 



4802 



Output 
O 



30pF" 



2552 



Output Loid A 



+ 5V 



480Q 



5pF- 



7T7 
Output Lo<d B 

(for t HZ , t LZ , t wz , & t ow ) 



Read Cycle 



Item 




Symbol 


HM6708-20 


HM6708-25 




Notes 




min. 


max. 


min. 


max. 


- Unit 


Read Cycle Time 





'rc 


20 




25 




ns 




Address Access Time 




'aa 




20 


_ 


25 


ns 




Chip Select Access Time 




'ACS 




20 




25 


ns 




Output Hold from Address Change 


'oh 


5 




5 




ns 




Chip Selection to Output in Low Z 


*LZ 












ns 


1,2 


Chip Deselection to Output 
in High Z 









8 





10 


ns 


1,2 



Note) 1. This parameter is sampled and not 100% tested. 

2. Transition is measured ±200 mV from steady state voltage with specified loading in Load B. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 21 3 



HM6708 Solas 

Read Cycle-I* 1 "' 2 



Address 



Data Out 



tRC 



3C 



tAA 



tOH ■ 




m 



■4- tQH 



Data Valid 



Read Cycle-2* 



i,.s 



CS 



Data Out 



tRC 



5 W 



tACS 



4 t L Z 



High Impedance 



Em 



Data Valid 



/High 
Impedance 



Notes) . 1 . WE is High for Read cycle. 

•2. Device is continuously selected, C5 ■ Vjr 
•3. Address valid prior to or coincident withCS 



low. 



Writ. Cycle 



Item 




HM6708-20 


HM6708-25 




Notes 




Symbol — 


min. max. 


min. 


max. 




Write Cycle Time 


>WC 


20 


25 




ns 


2 


Chip Selection to End of Write 


*CW 


15 


20 




ns 




Address Valid to End of Write 


( AW 


15 


20 






ns 





Address Setup Time 


Us 










ns 




Write Pulse Width 


*WP 


15 


20 




ns 


- 


Write Recovery Time 


( WR 


3 


3 




ns 





Data Valid to End of Write 


( DW 


12 


15 




ns 




Data Hold Time 


*DH 










ns 




Write Enable to Output in High Z 


f WZ 


8 





10 


ns 


3,4 


Output Active from End of Write 


'ow 










ns 


3,4 



Note) 1 . If CS goes high simultaneously with WE high, the output remains in a high impedance state. 

2. All Write Cycle timings are referenced from the last valid address to the first transitioning address. 

3. Transition is measured ±200 mV from steady state voltage with specified loading in Load B. 

4. This parameter is sampled and not 100% tested. 



HITACHI 

21 4 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 



HM6708 Series 



Write Cycle- 1 (WE Controlled) 



Address 



CS 



WE 



Data In 



Data Out 



7 


■* t wc ► 

( ) 


( 




H t cw ► 






w 


xi 


//// 


///// 

////// 




■4 L 

4- t A s\> 


- 'aw ► 

t w p*l ► 


1- t W R* 2 H» 








S 7 


i 






■*— *DW — ► 

^)^Data Valid 


I®" 






1 ) \ Hicrh Imneria. 


4 tow*^l 







HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 21 5 



HM6708 Series - 



Write Cycle-2 (CS Controlled) 



Note) 



Address 



CS 



WE 



Data I 



Data Out 



di. 



twc 



"SXXXXXXXXXM 



+ 

* tAS ► 


- 'aw ► 






< tew ► 

S 7 


L 


^ t WP *i ► 

t 7 


AWWVW 




-* — tow — ► 





Data Valid 



MXXXEX 



High Impedance * 4 



*1. A write occurs during the overlap of a low CS and a low WE. (t^p) 
*2. fvyjj is measured from the earlier of CS or WE going high to the end of write cycle. 

*3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs 
must not be applied. 

»4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the 

output buffers remain in a high impedance state. 
«5. If Cl> is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase 

to the outputs must not be applied to them. 
•6. Output is the same phase of write data of this write cycle. 



216 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, 



4005-1819 .(415)1 



j708A Series — Product Preview 

3-Word x 4-Bit High Speed Static RAM 
-EATURES 

Super Fast 

Access Time 15/20/25ns (max.) 

» Low Power Dissipation 400mW (typ.) 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Fully TTL Compatible Input and Output 

■ ORDERING INFORMATION 







Type No. 


Access Time 


Package 


HM6708AP-15 


15ns 


300 mil 24 pin 


HM6708AP-20 


20ns 


Plastic DIP 


HM6708AP-25 


25ns 


(DP-24NC) 


HM6708AJP-15 


15ns 


300 mil 24 pin 


HM6708AJP-20 


20ns 


Plastic SOJ 


HM6708AJP-25 


25ns 


(CP-24D) 



■ BLOCK DIAGRAM 



A 2 o- 
A 3 o- 
A 4 o- 
A7 o- 
As o- 
Ag o- 
A5 o- 
A6 o- 



Row 
Decoder 



I/O, o- 
I/O20- 
I/O3O- 

I/04 0- 



CS o- 



Input 
Data 
' iQ~ Control 



Memory Matrix 
256 X 1024 



Column I/O 



Column Decoder 



>V C0 
>V SS 



AioAnA, 2 A, 3 A, 4 A, 5 A A 

1 — 



^3 — 1 




(DP-24NC) 







(CP-24D) 



PIN ARRANGEMENT 



An 


c 




24 


□ 


v C c 


A1 


c 


2 


23 




A15 


A 2 


Lt 


3 


22 


□ 


A14 


A3 


C 


4 


21 


□ 


A13 


A 4 


C 


5 


20 


□ 


A12 


As 


Lt 


6 


19 


□ 


A11 


A 6 


r 


7 


18 


□ 


A10 


A 7 


r 


8 


17 


□ 


I/O1 


A 8 


c 


9 


16 


□ 


I/O2 


A9 


C 


10 


15 




I/O3 


CS 


c 


11 


14 


□ 


I/O4 


Vss 


c 


12 


13 




WE 



(Top View) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 21 7 



HM6708A Series 







■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage to V ss Pin 


V X 


-0.5 to +7.0 


V 


Power Dissipation 


P T 


1.0 


W 


Operating Temperature Range 


T 

A opr 


to +70 


°c 


Storage Temperature Range (with bias) 


Tstg(bias) 


-10 to +85 


°c 


Storage Temperature Range 


T stg 


-55 to + 125 


°c 



RECOMMENDED DC OPERATING CONDITIONS (0°C < T a < 70°C) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


V SS 


0.0 


0.0 


0.0 


V 


Input High (Logic 1) Voltage 


VlH 


2.2 




V CC + 0.5 


V 


Input Low (Logic 0) Voltage 


v 1L 


-3.0* 




0.8 


V 



*Pulse width < 15ns, DC: -0.5V 
■ TRUTH TABLE 



cs 


WE 


Mode 


Vqc Current 


I/O Pin 


Ref. Cycle 


H 


X 


Not Selected 


Isb> Isbi 


High Z 




L 


H 


Read 


Ico Icci 


Data Out 


Read Cycle (1) (2) 


L 


L 


Write 


Ice Icci 


Data In 


Write Cycle (1) (2) 



DC AND OPERATING CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, V s 



0V) 



Item 


Symbol 


Test Condition 


Min. 


Typ- 


Max. 


Unit 


Input Leakage Current 


Hul 


V cc = 5.5V, V IN = V ss to V cc 






2 


fiA 


Output Leakage Current 


HloI 


CS = V IH , V, /0 = V ss to V cc 






10 


liA 


Operating Power Supply Current 


Ice 


CS = V IL , I I/0 = 0mA 






100 


mA 


Average Operating Current 


Icci 


Min. Cycle, Duty: 100%, I I/0 = 0mA 






120 


mA 




Isb 


CS = V IH , V IN = V IH orV IL 






30 


mA 


Standby Power Supply Current 


ISB! 


CS > V cc - 0.2V 

V IN < 0.2V or V, N > V cc " 0.2V 






10 


mA 


Output Low Voltage 


Vol 


Iol = 8mA 






0.4 


V 


Output High Voltage 


V 0H 


Ioh = -4mA 


2.4 






V 



AC TEST CONDITIONS 

' Input Pulse Levels: V ss to 3.0V 

' Input Timing Reference Levels: 1.5V 

' Output Reference Levels: 1.5V 



Input Rise and Fall Times: 
Output Load: See Figure 



+5 V 
4800 



2550 



Dout 

o- 



30 pF* 



2550 




Output Load A 



Output Load B 
(for t HZ , t LZ , t wz & t OW) 



including scope and jig capacitance. 



HITACHI 

21 8 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6708A Series 



■ CAPACITANCE (T a = 25°C, f = 1.0MHz) 



Item 


Symbol 




Max. 


Unit 


Input Capacitance 




Vin = ov 


6.0 


pF 


Output Capacitance 


c i/o 


Vi/o = OV 


10.0 


pF 



NOTE: This parameter is sampled and not 100% tested. 

■ AC CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, unless otherwise noted.) 
• Read Cycle 



Item 


Symbol 


HM6708A-15 


HM6708A-20 


HM6708A-25 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


'rc 


15 




20 




25 




ns 




Address Access Time 


<AA 




15 




20 




25 


ns 




Chip Select Access Time 


'ACS 




15 




20 




25 


ns 




Output Hold from Address Change 


'oh 


3 




3 




3 




ns 




Chip Selection to Output in Low Z 




3 




3 




3 




ns 


1. 2 


Chip Deselection to Output in High Z 


«HZ 





6 





8 





10 


ns 


1. 2 



NOTES: 1 . This parameter is sampled and not 100% tested. 

2. Transition is measured ± 200mV from steady state voltage with specified loading in Load B. 



• Write Cycle 



Item 


Symbol 


HM6708A-15 


HM6708A-20 


HM6708A-25 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


[ wc 


15 




20 




25 




ns 


1 


Chip Selection to End of Write 


'cw 


10 




15 




20 




ns 




Address Valid to End of Write 


l AW 


10 




15 




20 




ns 




Address Setup Time 


t AS 

















ns 




Write Pulse Width 


( WP 


10 




15 




20 




ns 




Write Recovery Time 


l WR 

















ns 




Data Valid to End of Write 


•dw 


9 




12 




15 




ns 




Data Hold Time 


<[>H 

















ns 




Write Enable to Output in High Z 


<wz 





6 





8 





10 


ns 


2, 3 


Output Active from End of Write 


tow 

















ns 


2,3 



NOTES: 1 . All write cycle timings are referenced from the last valid address to the first transitioning address. 

2. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

3. This parameter is sampled and not 100% tested. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



219 



HM6708A Series 



■ TIMING WAVEFORM 
• Read Cycle (1) 0) (2) 



Address 



• Read Cycle 



CS 



'rc 



tACS 



Slz 



Data Out 



(XXx 

High Impedance 





tRC 




> 


< > 







tAA 




< tQH > 




tOH 

•* — *- 






Previous Data Valid y 




^ Data Valid ^> 


kxx 





—y 



tHZ 



Data Valid 



S Mi 



High 
Impedance 



NOTES: 1 . WE is High for READ cycle. 

2. Device is continuously selected, CS = Vn.. 

3. Address valid prior to or coincident with CS transition low. 



HITACHI 

220 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Write Cycle (1) (WE Controlled) 




twc 



— 



HM6708A Series 



X 



tew 



2 



X 



V/////////////, 



tAS 



WE 



Din 



t WZ (3) 



low 



tWR(2) 



t tDH(5^ 



Data Valid 



«.<.<«.<«.<«««a 



tpW (5) 



High Impedance 



tOH(6) 



• Write Cycle (2) (CS Controlled) 



Address 

CS 
WE 

Data In 
Dout 

NOTES: 





twc 




> 


< ) 


< 




< AW * 

< l AS t CW „ 


< tWR-2 ^ 






\ / 

I _ twp*1 






^^^^ 


V///////////// 

/////////// ///, 


« tow p 






XXXXXXXXXXXXXXXXX Data valid >< 


:xxxxxxxx> 



High Impedance (2) 



1 . A write occurs during the overlap of a low CS and a low WE (twp). 

2. twR is measured from the earlier of CS or WE going high to the end of write cycle. 

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not 
be applied. 

4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output 
buffers remain in a high impedance state. 

5. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the 
outputs must not be applied to them. 

6. Output data is the same phase of write data of this write cycle. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 221 



HM6709 Series — Preliminary 

65536-Word x 4-Bit High Speed Static RAM (with OE) 

■ FEATURES 

• Super Fast 

Access Time 20725ns (max.) 

• Fast OE 

Access Time 10ns (max.) 

• Low Power Dissipation 350mW (typ.) 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Balanced Read and Write Cycle Time 

• Fully TTL Compatible Input and Output 

• 300 mil 28 pin SOJ 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6709JP-20 
HM6709JP-25 


20ns 
25ns 


300 mil 28 pin 
Plastic SOJ 
(CP-28DN) 


■ BLOCK DIAGRAM 







A 8 o 
Ai o 
A 2 o 
A 3 o 



A 9 o 
A100- 

l/O, o 




I/O2& 
I/O3& 
I/O4O 







(CP-28DN) 





■ PIN ARRANGEMENT 



nc r~ 

An C 
A1 C 
A 2 C 
A3 □ 
A 4 C 
AsC 
A 6 C 
A7 C 
A 8 □ 10 
A9 C 11 
CS □ 12 
OE □ 13 
Vss C 14 



26 
25 
24 
23 
22 
21 
20 
19 
18 
17 



28 □ VcC 
27 □ A15 

□ Au 

□ A13 

□ A12 

□ A11 

□ A10 

□ NC 

□ NC 

□ I/O1 

□ I/O2 

□ I/O3 
16 □ I/O4 
15 □ WE 



(Top View) 



HITACHI 

222 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6709 Series 



ABSOLUTE MAXIMUM RATINGS 



Item 


jy 1IILMJ1 




Unit 


Terminal Voltage to V^ Pin 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


P T 


1.0 


W 


Operating Temperature Range 


T 


Oto +70 


°c 


Storage Temperature Range (with bias) 


T s i s (bias) 


-10 to + 85 


'C 


Storage Temperature Range 


T S [ K 


-55 to + 125 


°c 



1 

Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


v ss 


0.0 


0.0 


0.0 


V 


Input High Voltage 


V,H 


2.2 




6.0 


V 


Input Low Voltage 


ViL* 


-3.0 




0.8 


V 



*Pulse width: 20ns, DC: -0.5V 
■ TRUTH TABLE 



CS 


OE 


WE 


Mode 


V cc Current 


I/O Pin 


Ref. Cycle 


H 


HorL 


HorL 


Not Selected 


Isb> Isbi 


High Z 




L 


H 


H 


Output Disabled 


Ice Icci 


HighZ 




L 


L 


H 


Read 


Ice- Icci 


Data Out 


Read Cycle (1) (2) (3) 


L 


H 


L 


Write 


Ice- Icci 


Data In 


Write Cycle (1) (2) (3) (4) 


L 


L 


L 


Ice- Icci 


Data In 


Write Cycle (5) (6) 



DC AND OPERATING CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C) 



Item 


Symbol 


Test Condition 


Min. 


Typ. 


Max. 


Unit 


Input Leakage Current 


UliI 


V cc = 5.5V,V IN = V ss toV cc 






2 


HA 


Output Leakage Current 


UloI 


CS = V IH or OE = V IH , WE = V, L 
v i/o = v ss to V cc 






10 


pA 


Operating Power Supply Current 


Ice 


CS = V IL , I I/0 = 0mA 






100 


mA 


Average Operating Current 


Icci 


Min. Cycle, Duty: 100%, I, /0 = 0mA 






120 


mA 




Isb 


CS = V IH , V IN = V 1H or V IL 






30 


mA 


Standby Power Supply Current 


Isbi 


CS > V cc - 0.2V 

V IN < 0.2V or V IN > V cc - 0.2V 






10 


mA 


Output Low Voltage 


Vol 


I 0L = 8mA 






0.4 


V 


Output High Voltage 


VqH 


Ioh = "4mA 


2.4 






V 


■ AC TEST CONDITIONS 

• Input Pulse Levels: V ss to 3.0V 

• Input and Output Reference Levels: 1.5V 


• Input Rise and Fall Time: 4ns 

• Output Load: See Figure 









Dout 



+5V 
48012 



255 Q 



30 pF' 



/77 
Output Load A 




5pF" 



Output Load B 
(for t HZ , t LZ , Xp m - k>Lz- 'wz & tow) 



scope and jig capacitance. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



223 



HM6709 Series 

■ CAPACITANCE (T a = 25°C, f = 1.0MHz) 



Item 


Symbol 


Test Conditio 


ns 


Min. 


Typ. 


Max. 


Unit 


Input Capacitance 




v, N = ov 








6 


pF 


Input/Output Capacitance 


Ci/o 


v„ = ov 








10 


pF 


NOTE: This parameter is sampled and not 100% tested. 

■ AC CHARACTERISTICS (V cc = 5V ± 10%, T a = 0° 
• Read Cycle 


C to 70°C, unless otherwise noted.) 


Item 




HM6709JP-20 


HM6709JP-25 


Unit 


Notes 


Symbol 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


<RC 


20 




25 




ns 




Address Access Time 


l AA 




20 




25 


ns 




Chip Select Access Time 


'ACS 




20 




25 


ns 




Chip Selection to Output in Low Z 


tLZ 












ns 


1,2 


Output Enable to Output Valid 


l OE 





10 





10 


ns 




Output Enable to Output in Low Z 


l OLZ 












ns 


1, 2 


Chip Deselection to Output in High Z 


l HZ 





8 





10 


ns 


1, 2 


Output Hold from Address Change 


l OH 


5 




5 




ns 




NOTES: 1. This parameter is sampled and not 100% tested. 

2. Transition is measured ±200mV from steady state v< 

• Write Cycle 


)ltage with specified loading is Load B. 


Item 




HM6709JP-20 


HM6709JP-25 


Unit 


Notes 


Symbol 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


'wc 


20 




25 




ns 


1 


Chip Selection to End of Write 


tew 


15 




20 




ns 




Address Setup Time 


(as 












ns 




Address Valid to End of Write 


'aw 


15 




20 




ns 




Write Pulse Width 


'wp 


15 




20 




ns 


_ 


Write Recovery Time 


'WR 


3 




3 




ns 




Write to Output in High Z 


'wz 





8 





10 


ns 


2, 3 


Data Valid to End of Write 


'dw 


12 




15 




ns 




Data Hold Time 


'dh 












ns 




Output Disable to Output in High Z 


<OHZ 





8 





10 


ns 


2, 3 


Output Active from End of Write 


tow 












ns 


2, 3 



NOTES: 1 . All write cycle timings are referenced from the last valid address to the first transitioning address 

2. This parameter is sampled and not 100% tested. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 



■ TIMING WAVEFORM 
• Read Cycle (1)0) 



Address 



OE 



tRC 



X 



x\\\\\\\\\\\\\^ 



t0E 



toLZ 



cs 



Ucs 



Data Out 



High Impedance 
Read Cycle (2) 0)(2)(3) 



X 



#/////////, 



tOH 



/ &//////////, 



tOHZ 



tcHZ 



Data Valid 



Address 





U ^ >i 




> 


< > 


< 




tAA 




tOH 




tOH > 






Previous Data Valid ) 


(XXX> 


^ Data Valid ) 


X 



• Read Cycle (3) 0)0) (4) 



CS 



Data Out 



X 



'rc 



tACS 



tCLZ 



High Impedance 



tCHZ 



NOTES: l.WE = V IH 

2. CS = V IL 

3. OE = V, L 

4. Address valid prior to or coincident with CS transition low. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 25 



• Write Cycle (1) (OE = H, WE Controlled) 



Address 



CS 



WE 



Data In 



> 


< ) 


< 






< lew > 








w 


s /, 




///////// 






tAW w 

I . twp(1) 










> 






XXXXXXXXXXXXXXXX) 


<^ Data Valid ^< 


wxxxxxx 



Data Out 



High Impedance 







• Write Cycle (2) (OE = H, CS Controlled) 



Address 



CS 



WE 



Data In 



Data Out 



> 


< ) 


< 






« tew ^ 










\ / 






1 _ t W P(1) 




</////////////. 










XXXXXXXXXXXXXXXX> 


<^ Data Valid 


:xxxxxxx> 



High Impedance 



<§> HITACHI 

226 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6709 Series 



• Write Cycle (3) (OE = Clocked, WE Controlled) 



Address 




5s WWWWWW^ 



WE 



Data Out 



Data In 



tew 



'aw 







; V////////////. 



twp(i) 



c tQHZ(2^ 



High Impedance 



High Impedance 



tow 



tWR > 



s 



tOLZ(2 



tDH 



High Impedance 



• Write Cycle (4) (OE = Clocked, CS Controlled) 



Address 



twe 



3^ 



X 



cs 



tAS 



tew 



*AW 



Si \\\\\\\\\\\\\\\\^ 



'WP(D 



<WR 







Data In 



Data Out 



High Impedance 




tpw 



, '////////////, 



tDH. 



Data Valid 



<0 HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 227 



HM6709 Series 



• Write Cycle (5) (OE = L, WE Controlled) 



Address 



CS 



'wc 



X 



tAS 



tew 



//////////////, 



WE 



twp (D 



-o- »»»»»»»»?» 



tWHZ (2) 

High Impedance 



Data In 



X 



tWR 



Y 



Data Valid 



tow 



tOH 



tDH 



3f 



(5) High Impedance 



• Write Cycle (6) (OE = L, CS Controlled) 



Address 
CS 



X 



iwc_ 



tAS 
-« — *■ 



x 



X 



tCLZ 



tew 



V 



tAW 



Data Out 



Data In 



'wp m 



tWHZ 



(GDI 



High Impedance 



High Impe 




tpw 



tWR 



//////////////. 



tDH 



Data Valid 



xxxxxxxxx) 



NOTES: 1. A write occurs during the overlap (twp) of a low CS and a low WE. 

2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not 
be applied. 

3. Output data is the same phase of write data of this write cycle. 



4. If the CS is low transition occurs after the WE low transition, output remain in a high impedance s 

5. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to t 
outputs must not be applied to them. 



6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in 
high impedance state. 



HITACHI 

228 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6709A Seri CS — Product Preview 

65536-Word x 4-Bit High Speed Static RAM (with OE) 
■ FEATURES 

• Super Fast 

Access Time 15/20/25ns (max.) 

• Fast OE 

Access Time 8/10710ns (max.) 

• Low Power Dissipation 400mW (typ.) 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Fully TTL Compatible Input and Output 



■ ORDERING INFORMATION 


Type No. 


Access Time 


Package 



HM6709AP-20 
HM6709AP-25 


15ns 
20ns 
25ns 


300 mil 28 pin 
Plastic DIP 
(DP-28N) 


HM6709AJP-15 
HM6709AJP-20 
HM6709AJP-25 


15ns 
20ns 
25ns 


300 mil 28 pin 
Plastic SOJ 
(CP-28DN) 


■ BLOCK DIAGRAM 







I/O, o 



I/02O 
I/03O 

1/04 



-oV cc 
-°v ss 





(DP-28N) 




(CP-28DN) 



PIN ARRANGEMENT 











NC □ 




28 


□ v C c 


Ao □ 


2 


27 


3 A15 


A1 C 


3 


26 


□ A14 


A 2 □ 


4 


25 


□ A13 


A3 □ 


5 


24 


□ A12 


A4 □ 


6 


23 


□ An 


AsC 


7 


22 


□ A10 


A 6 C 


8 


21 


□ NC 


AtC 


9 


20 


□ NC 


As C 


10 


19 


□ I/O1 


A 9 □ 


11 


18 


□ I/O2 


cs □ 


12 


17 


□ I/O3 




13 


16 


□ I/O4 


vss C 


14 


15 


□ WE 




(Top View) 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 229 



HM6709A Series 



ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 




Terminal Voltage to V ss Pin 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


Pt 


1 n 


w 
w 


Operating Temperature Range 


T 


Oto +70 


°c 


Storage Temperature Range (with bias) 


T stg (bias) 


-10 to +85 


°c 


Storage Temperature Range 




-55 to + 125 


°c 

1 


■ RECOMMENDED DC OPERATING CONDITIONS (0°C < T a < 


70°C) 





Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


V S s 


0.0 


0.0 


0.0 


V 


Input High Voltage 


V,H 


2.2 




6.0 


V 


Input Low Voltage 


VlL* 


-3.0 




0.8 


y 





*Pulse width: 15ns, DC: -0.5V 
■ TRUTH TABLE 



CS 


OE 


WE 


Mode 


V cc Current 


I/O Pin 


Ref. Cycle 


H 


HorL 


HorL 


Not Selected 


Isb. Isbi 


High Z 




L 


H 


H 


Output Disabled 


Ico Icci 


High Z 




L 


L 


H 


Read 


Ice- Icci 


Data Out 


Read Cycle ( 1 ) (2) (3) 


L 


H 


L 


Write 


Ice Icci 


Data In 


Write Cycle (1) (2) (3) (4) 


L 


L 


L 


Ice- Icci 


Data In 


Write Cycle (5) (6) 



DC AND OPERATING CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C) 



Item 


Symbol 


Test Condition 


Min. 


Typ. 


Max. 


Unit 


Input Leakage Current 


M 


V cc = 5.5V, V, N = V ss to V cc 






2 


M 


Output Leakage Current 


HloI 


CS = V, H or OE = V, H or WE = V, L 
v i/o = v ss <° v cc 






10 


jiA 


Operating Power Supply Current 


Ice 


CS = V IL . I I/Q = 0mA 






100 


mA 


Average Operating Current 


Icci 


Min. Cycle, Duty: 100%, I I/0 = 0mA 






120 


mA 




Isb 


CS = V 1H , V IN = V IH or V IL 






30 


mA 


Standby Power Supply Current 


Isbi 


CS > V cc - 0.2V 

V IN < 0.2V or V IN > V cc - 0.2V 






10 


mA 


Output Low Voltage 


Vol 


I OL = 8mA 






0.4 


V 


Output High Voltage 


V OH 


I OH = -4mA 


2.4 






V 



■ AC TEST CONDITIONS 

• Input Pulse Levels: V ss to 3.0V 

• Input and Output Reference Levels: 1.5V 



1 Input Rise and Fall Time: 4ns 
Output Load: See Figure 



Dout 



255!! 




Dout 



+5 V 
I 480S! 



30 pF* 



255!! 



5pF* 



Output Load A 



/77 
Output Load B 
(f° r <HZ. 'lz. toHz. toLz. l wz & km 



♦Including scope and jig capacitance. 



HITACHI 

230 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6709A Series 

■ CAPACITANCE (T a = 25°C, f = 1.0MHz) 



Item 


Symbol 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Input Capacitance 


C IN 


Vin = ov 






6 


pF 


Input/Output Capacitance 


c i/o 


V,/o = ov 






10 


P F 



NOTE: This parameter is sampled and not 100% tested. 



■ AC CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, unless otherwise noted.) 
• Read Cycle 



Item 


Symbol 


HM6709A-15 


HM6709A-20 


HM6709A-25 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


tRC 


15 




20 




25 




ns 




Address Access Time 


( AA 




15 




20 




25 


ns 




Chip Select Access Time 


'ACS 




15 




20 




25 


ns 




Chip Selection to Output in Low Z 


tLZ 


3 




3 




3 




ns 


1, 2 


Output Enable to Output Valid 




l OE 





8 





10 





10 


ns 




Output Enable to Output in Low Z 


k)LZ 


3 




3 




3 




ns 


1. 2 


Chip Deselection to Output in High Z 


<HZ 





6 





8 





10 


ns 


1, 2 


Output Hold from Address Change 


«OH 


3 




3 




3 




ns 




NOTES: 1 . This parameter is sampled and not 100% tested. 

2. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

• Write Cycle 


Item 


Symbol 


HM6709A-15 


HM6709A-20 


HM6709A-25 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


'wc 


15 




20 




25 




ns 


1 


Chip Selection to End of Write 


tew 


10 




15 




20 




ns 




Address Setup Time 


t A s 

















ns 




Address Valid to End of Write 


l AW 


10 




15 




20 




ns 




Write Pulse Width 


l WP 


10 




15 




20 




ns 




Write Recovery Time 


( WR 

















ns 




Write to Output in High Z 


'wz 





6 





8 





10 


ns 


2, 3 


Data Valid to End of Write 


l DW 


9 




12 




15 




ns 




Data Hold Time 


<DH 

















ns 




Output Disable to Output in High Z 


l OHZ 





6 





8 





10 


ns 


2, 3 


Output Active from End of Write 


tow 










_ 







ns 


2, 3 



NOTES: 1 . All write cycle timings are referenced from the last valid address to the first transitioning address. 
2. This parameter is sampled and not 100% tested. 



3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 231 



HM6709A Series 



■ TIMING WAVEFORM 
• Read Cycle (1)< 1 > 



Address 



OE 



tRC 



X 



tAA 



cs 



Data Out 



tOE 



tOLZ 



tACS 



tdZ 



High Impedance 
Read Cycle (2) (D(2)(3) 



Address 



Read Cycle (3) (DO) (4) 



CS 



Data Out 



Ucs 



tLZ 



High 



X 



& /////////, 



tOH 



tQHZ 



<CHZ 



Data Valid feO ~ 





M tRC 


> 


< 




tAA 




* tOH ^ 




Previous Data Valid ^ 


booo 


^ Data Valid 



x 



tQH 



XX 



y 



tHZ 



Data Valid 



NOTES: 1 WE = Vm 

2. CS = V, L . 

3. OE = V IL . 

4. Address valid prior lo or coincident with CS transition low. 



HITACHI 

232 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6709A Series 



• Write Cycle (1) (OE = H, WE Controlled) 



Address 



CS 



two 



X 



tew 



///////////////. 



tAS 



WE 



tpw 



X 



y 



. tDH . 



°-* xxxxxxxmxxxxm: ■>-««. ~x«xxxxxx: 

High Impedance 



Data Out 



• Write Cycle (2) (OE = H, CS Controlled) 



Address 



CS 



WE 



Data In 



Data Out 



> 


< ) 


< 












\ / 






I - tWP(1) 




'/////////////, 


|« to - 






XXXXXXXXXXXXXXXXX X 


XXXXXXXX) 



High lm| 



pedance 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 33 



• Write Cycle (3) (OE = Clocked, WE Controlled) 



Address 




cs 



WE 



tew 



/ V/////////////. 



tAS. 



_| r. twP(1) _| 



tOH2(2) 



Data Out 



Data In 



High Impedance 



High Impedance 



tpw 



• Write Cycle (4) (OE = Clocked, CS Controlled) 



tOLZ(2 



High Impedanct 



Address 



twe 



si v///////////x » 



cs 



tAS 



tew 



K 



x 



X 



Data In 



Data Out 



^ twP(1) 


'///, 


V////////. 




« ,dw » 


tDH 




XX) 


( Data Valid ) 





High Impedance 



HITACHI 

234 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6709A Series 



• Write Cycle (5) (OE = L, WE Controlled) 



Address 



l wc 



X 



5? xWWWW^ 



tAS 



'cw 



//////////////, 



Jaw 



> 



WE 



tWHZj (2) 



t 

High Impedance 



twp (D 



High Impedance 



Data In 



<I 



X 



tWR 



Y 



tow 



tOH 



tDH 



Data Valid 



(5) High Impedance 



• Write Cycle (6) (OE = L, CS Controlled) 



CS 



Data Out 



Data In 





« 'wc „ 




> 


< > 


< 




tAS 


* t C W > 








s 


\ / 


/ 

< twR 




** 




'AW 

„ t W P (1) fc 




St 


^ i 


V/////////////, 


liz 




twz 

' \ H '9 n Impedance 
, ' 4 » )\ — 





High Impedance 



Data Valid 



NOTES: 1 . A write occurs during the overlap (twp) of a low CS and a low WE. 

2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not 
be applied. 

3. Output data is the same phase of write data of this write cycle. 

4. If the CS is low transition occurs after the WE low transition, output remain in a high impedance state. 

5. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the 
outputs must not be applied to them. 

6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in 
high impedance state. 



Hitachi America, Ltd. • Hitachi Plaza • 200o'sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 235 



HM6207 Series 



262144-word x 1-bit High Speed CMOS Static RAM 



The Hitachi HM6207 is a high speed 256k static RAM or- 
ganized as 256-kword x 1-bit. It realizes high speed access time 
(35/45 ns) and low power consumption, employing CMOS 
process technology and high speed circuit designing technology. 
It is most advantageous for the field where high speed and high 
density memory is required, such as the cache memory for main 
frame or 32-bit MPU. The HM6207, packaged in a 300 mil 
plastic DIP, is available for high density mounting. 

Low power version retains the data with battery back up. 

Features 

• High Speed: Fast Access Time 35/45 ns (max.) 

• Low Power 

Standby: 100 mW (typ.)/30 m w (typ ) (L-version) 
Operation: 300 mW (typ.) 

• Single 5V Supply and High Density 24 Pin Package 

• Completely Static Memory: 

No Clock or Timing Strobe Required 

• Equal Access and Cycle Time 

• Directly TTL Compatible: All Inputs and Outputs 

• Capability of Battery Back Up Operation (L-version) 



Ordering Information 



Type No. 



Access Time 



HM6207P-35 
HM6207P-45 



35 ns 
45 ns 



HM6207LP-35 
HM6207LP-45 



35 i 
45 ns 



300-mil 24-pin Plastic DIP 



Absolute Maximum Ratings 



Item 


Symbol 


Rating 


Unit 


Voltage on Any Pin Relative to Vgg 


V T 


-0.5 *' to +7.0 


V 


Power Dissipation 


P T 


1.0 


W 


Operating Temperature 


Topr 


to +70 


°C 


Storage Temperature 


Tstg 


-55 to +125 


°c 


Storage Temperature under bias 


Tbias 


-10 to +85 


°c 


Note) *1. -2. 5 V for pulse width g 10ns. 








(DP-24NC) 



Pin Arrangement 


Ai7f~r 




17]Vec 


Ao|T~ 




23~|a16 


Al |~3~ 




22]a15 


A2[T 




2l"|AH 


A3|T 




lo] A13 


A4[T 




19]a12 


A5|~7~ 




18~| All 


A6 LL 




if] A10 


A7 [F 




le] A9 


Dout [~10~ 




"l5~j A8 


we |7T 




77] Din 






"l3~| CS 




(Top View) 




Pin Description 


Pin Name Function 


A0-A17 Address 


Din 


Data Input 


Dout 


Data Output 


CS 


Chip Select 


WE 


Write Enable 


V CC 


Power Supply 


V ss Ground 





















HITACHI 

236 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Block Diagram 




Memory Amy 

256X1,024 



- Vcc 
-V„ 



I/O 



to 



A14A13 A12A11 A8 A7 A6 A5 A10 A9 



Function Table 



cs 


WE 


Mode 


V cc Current 


Dout Pin 


Ref. Cycle 


H 


X 


NOT SELECTED 


'SB. 'SBl 


HIGH-Z 




L 


H 


READ 


■cc 


Dout 


READ CYCLE 


L 


L 


WRITE 


>cc 


HIGH-Z 


WRITE CYCLE 



Note) X means don't care. 



DC Operating Conditions (Ta = to +70° C) 



Parameter 


Symbol 


min 


typ 


max 


Unit 








v C c 


4.5 


5.0 


5.5 


V 






Supply Voltage — 


v ss 











V 






Input High (logic 1) Voltage 


Vm 


2.2 




6.0 


V 






Input Low (logic 0) Voltage 


VlL 


-0.5 *> 




0.8 


V 






Note) *1 . -2.0V for pulse width ^ 1 ns 














DC and Operating Characteristics (Ta = to +70°C, V 


CC 


= 5V± 10%, V ss = 


0V) 




Parameter 


Symbol 


min 




typ' 1 


max 


Unit 


Test Condition 


Input Leakage Current 


I'liI 








2.0 


MA 


V cc = MAX. 
Vin = V ss to V CC 


Output Leakage Current 


HloI 








10.0 


mA 


CS = V IH 

Vout = V ss to V cc 


Operating Power Supply Current 


•cc 






60 


100 


mA 


CS = V IL 

lout » 0mA, min. cycle 


Standby Power Supply Current 


'SB 






15 


30 


mA 


CS = Vm, min. cycle 


Standby Power Supply Current (1) 


•SBl 






0.02 


2.0 


mA 


CS > V CC -0.2V, 
0V=i V, N g 0.2V or 
VlN^V cc -0.2V 






0.006 "2 


0.1 n 


Output Low Voltage 


Vol 








0.4 


V 


IOL = 8mA 


Output High Voltage 


Vqh 


2.4 








V 


IoH = -4-0mA 



Note) «1 . Typical limits are at V C c = 5.0V, T a = 25°C and specified loading. 
•2. This characteristics is guaranteed only for L-version. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 37 



HM6207 Series 



Capacitance (7a = 25°C,/= 1 .OMHz) 



. Parameter 


Symbol 


Min 


Typ 


Max 


Unit 


Conditions 


Input Capacitance 


Cin 






6.0 


pF 


Vin = 


OV 


Output Capacitance 


Cout 






10 


P F 


Vout = 


OV 



AC Characteristics (Ta= to +70°C, V C c= 5V ± 10%, unless otherwise noted.) 
AC Test Conditions 

• Input pulse levels: V ss to 3.0V • Input and Output timing reference levels: 1 .5V 

• Input rise and fall times: 5ns • Output load: See Figures. 



Output Load ! A ) 
+ 5V 
O 



480 S 



Output Load (B) 
(for l„ z , ttz, twz & law) 
+ 5V 



• 480 



Dout O 




Dout O- 



255 Q. 



777 



♦ Including scope & jig. 



Read Cycle 



Parameter 


Symbol 


HM6207-35 


HM6207-45 


Unit 


Notes 


min 


max 


min 


max 


Read Cycle Time 


>RC 


35 




45 




ns 




*1 


Address Access Time 


<AA 




35 




45 


ns 




Chip Select Access Time 


'ACS 




35 




45 


ns 





Output Hold from Address Change 


tOH 


5 




5 






ns 




Chip Selection to Output in Low Z 


*LZ 


5 




5 




ns 


*2, *3,*7 


Chip Deselection to Output in High Z 


tHZ 





30 





30 


ns 


*2, *3, *7 


Chip Selection to Power Up Time 


tpu 












ns 


*7 


Chip Deselection to Power Down Time 


tPD 




30 




40 


ns 


*7 


Timing Waveform of Read Cycle No. 1 

i 


*4, *5 















Address 



)<X 



HITACHI 

238 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



impedance 



Timing Waveform of Read Cycle No. 2 



•4,«6 



Notes) *1. All Read Cycle timings are referenced from last valid address to the first transitioning address. 

•2. At any given temperature and voltage condition, t[jZ max. is less than tj^z min. both for a given device and i 
device to device. 

♦3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

•4. WE is high for READ Cycle. 

•S. Device is continuously selected, while CS -J^JL- 

*6. Addresses valid prior to or coincident with CS transition low. 

*7. This parameter is sampled and not 100% tested. 



Write Cycle 



Parameter 


Symbol 


HM6207-35 


HM6207-45 


Unit 


Notes 


min 


max 


min 


max 


Write Cycle Time 


'WC 


35 




45 




ns 


*2 


Chip Selection to End of Write 


tew 


30 




40 




ns 




Address Valid to End of Write 


*AW 


30 




40 




ns 




Address Setup Time 


'AS 












ns 




Write Pulse Width 


'WP 


25 




25 




ns 




Write Recovery Time 


'WR 


3 




3 




ns 




Data Valid to End of Write 


*DW 


20 




20 




ns 




Data Hold Time 


'OH 










_ 


ns 





Write Enable to Output in High Z 


'WZ 





20 





25 


ns 


*3, *4 


Output Active from End of Write 


tow 












ns 


•3, *4 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 39 



HM6207 Series 



Timing Waveform of Write Cycle No. 1 (WE Controlled) 



V 



X 



_ iA ± _ 



X 



D.u in Valid 




s 



— 



7/ / / / / 
////// 



A 



High Impedance 



Timing Waveform of Write Cycle No. 2 (CS Controlled) 



X 



cs 



X 



/ 



\\\\\\\\\\\\\\\\ 



X 



////////////, 



X 



D.M Undefined ^ ■ 



High Impedance 



Notes) *1 . If CS goes high simultaneously with WE high, the output remains in a high impedance states. 

•2. All Write Cycle timings are referenced from the last valid address to the first transitioning address. 

•3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

•4. This parameter is sampled and not 100% tested. 



240 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6207 Series 



Low V cc Data Retention Characteristics (Ta = to +70° C) 
(This characteristics is guaranteed only for L-version) 



Parameter 


Symbol 


min 


typ. 


max. 


Unit 


Test Condition 


v CCf°r Data Retention 


V D R 


2.0 






V 


CS ^ VCC -0.2V, 
- V ir ^ V rc - 0.2V or 


Data Retention Current 


'CCDR 




2 


50* 2 


«A 


0?SVfaI 0.2V 


Chip Deselect to Data Retention Time 


'CDR 









ns 


See retention 


Operation Recovery Time 


«R 


♦ *i 

'rc 1 






ns 


waveform 


Note) »1. t RC = Read Cycle Time *2. 


V cc = 3.0V 












Low V cc Data Retention Waveform 















Data Retention Mode 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 241 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6207/HM6207H Series 
1-Bit CMOS Static RAM 

262144-Word x 1-Bit High Speed CMOS Static RAM 

The Hitachi HM6207 and HM6207H are high speed 256k 
static RAMs organized as 256-kword x 1 -bit. They realize high 
speed access time (25/35/45ns) and low power consumption, 
employing CMOS process technology and high speed circuit 
design technology. It is most advantageous wherever high 
speed and high density memory is required. 

The HM6207 and HM6207H are packaged in the industry 
standard 300-mil, 24-pin plastic DIP. The HM6207H is also 
available in a 300-mil, 25-pin plastic SOJ package for high 
density mounting. The low power versions are ideal for battery 
backed systems. 

Features 

• Single 5 V supply and high density 24-pin package 

• High speed 



Access time: 25/35/45 ns (max.) 



Low power 
Active: 
Standby: 



300 mW (typ.) 
100 M W (typ.) 



30 j<W (typ.) (L-version) 

• Completely static memory requires 

No clock or timing strobe requires 

• Equal access and cycle time 

• All inputs and outputs TTL compatible 

• Capability of battery back up operation (L-version) 

Ordering Information 



Type No. Access Time 


Package 


HM6207P-35 


35 ns 




HM6207P-45 


45 ns 


_ 300-mil 


HM6207HP-25 


25 ns 


24-pin 


HM6207HP-35 


35 ns 


plastic DIP 


HM6207HLP-25 


25 ns 


(DP-24NC) 


HM6207HLP-35 


35 ns 




HM6207HJP-25 


25 ns 


300-mil 


HM6207HJP-35 


35 ns 


24-pin 


HM6207HLJP-25 


25 ns 


plastic SOJ 


HM6207HLJP-35 


35 ns 


(CP-24D) 


Pin Description 






Pin Name Function 






A0-A17 Address 






Din Data input 






Dout Data output 






CS Chip select 






WE Write enable 






Vcc Power supply 






Vss Ground 








Pin Arrangement 



»i?jT 




17| v„ 


aoQT 




"23"] Ate 


Al [T 




~2z]a|5 


A2[T 




jTJah 


A3 E 




lo] A13 


A< [T 




"til A12 


A5[T 




lSj All 


A6[T 




77] A10 


A7 [7£ 




7o"| A9 


Dout QF 




77J A8 


we [77 
v* [77 




77Jd,» 
77| cs 







HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



243 



HM6207/HM6207H Series - 

Block Diagram 




- v„ 



I/O 



Column Decoder 



fflfflfffl 

4A13 A12AU A8 A7 A6 A5 A10 A9 



Function Table 












TS 'WE 


Mode 


Vcc Current 


I/O Pin 


Rcf. Cycle 




H x 


Nol selected 


Isb, Isbi 


High-Z 






L H 


Read 


Ice 


Dout 


Read cycle 




L L 


Write 


Ice 


High-Z 


Write cycle 





Note: x means don't care. 



Absolute Maximum Ratings 



Item 


Symbol 


Value 


Unit 


Voltage on any pin relative to Vss 


Vin 


-0.5' 1 to +7.0 


V 


Power dissipation 


Pr 


1.0 


w 


Operating temperature range 


Topr 


to +70 


°c 


Storage temperature range 


Tstg 


-55 to +125 


°c 


Storage temperature range under bias 


Tbias 


-10 to +85 


°c 



Note: *1. Vin min = -2.5 V for pulse width < 10 ns. 



244 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6207/HM6207H Series 



Recommended DC Operating Conditions (Ta = to +70°C) 



Item 


Symbol 


Min 


Typ 


Max 


Unit 


Supply voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 











V 


Input high (logic 1 ) voltage 


VlH 


2.2 




6.0 


V 


Input low (logic 0) voltage 


Vtt. 


-0.5"' 




0.8 


V 



Note: * 1 . Vtt. min = -2.0 V for pulse width S 1 ns. 



■ DC Characteristics (T, = to +70-C. v cc = 5 V ± 10%. v ss = V) 





Item 


Symbol 


Min. 


Typ." 1 


Max. 


Unil 


Test Conditions 


Input Leakage Current 


M 






2.0 


/iA 


V cc = Max. 
V,„ = V ss to V„. 


Output Leakage Current 


HloI 






10.0 


U A 


CS = V IH 

V TO = VssloVcc 


Operating Power Supply Current 


Ice 




60 


100 


mA 


CS = V, L . 1,,,, = mA. 
Min. Cycle. Duty = 1009i 


Standby Power Supply Current 


'sB 




IS 


30 


mA 


CS = V, H . Min. Cycle 


Standby Power Supply Current 


"H" Version 


'.SB 




20 


40 


mA 


Standby Power Supply Current ( 1 ) 


'sBI 




20 


2000 


«A 


CS > V cr - 0.2 V 
V < V ln < 0.2 V or 
V,„ 2 V CC -0.2V 


Standby Power Supply Current (1) 


L- Vers ion 


IsBI 




6 


100 


*A 


Output Low Voltage 


Vol 






04 


V 


Io! = 8 mA 


Output High Voltage 


VqH 


2.4 






V 


I OH = -*.0 mA 



Note: «l. Typical limits arc al V cc = 5.0 V. T, = +25°Cand specified loading. 



Capacitance (Ta = 25°C, f = 1MHz) -1 

Item Symbol Min Max Unit Test Conditions 

Input capacitance Cin — 6 pF Vin = V 

O utput ca pa citance Com 10 pF V<,„t = V 

Note: * 1 . This parameter is sampled and not 1 00% tested. 



AC Characteristics (Ta = to +70°C, Vcc = 5 V ± 10%, unless otherwise noted.) 
Test Conditions 

• Input pulse levels: Vss to 3.0 V • Input and output timing reference levels : 1 .5 V 

• Input rise and fall times: 5 ns • Output load: See Figures 

Output Load (A) Output Load (B) 

(for tttz, tti twz & tow) 




Note: • Including scope & jig. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 45 



HM6207/HM6207H Series 



Read Cycle 





Item 


Symbol 


HM6207H-25 


HM6207-35 
HM6207H-35 


HM6207-45 


Unit 






Min. 


Max. 


Min. 


Max. 


Min. 


Max. 




Read Cycle Time 


•rc 


25 




35 




45 




ns 


Address Access Time 


>AA 




25 




35 




45 


ns 


t_nip oeiect Access lime 


<ACS 




25 




35 




45 


ns 


Outpui Hold From Address Change 


l 0H 


5 




5 




5 




ns 


Chip Selection to Output in Low-Z 


<LZ*' 


5 




5 




5 




ns 


Chip Deselection to Output in High-Z 


t H z*' 





12 





20 





30 


ns 


Chip Selection to Power Up Time 


ipu 

















ns 


Chip Deselection to Power Down Time 


'PD 




15 




25 




40 


ns 



Note: *l Transition is measured ±200 mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 

Read Timing Waveform (1) 





Ik 




> 


< > 


< 




1 


M 






<x 






) 


^ Data Invalid ^ 


^ Diu Valid ) 



Timing Waveform (2) * 3 



High Imped.nc,. 



^ Data Invalid 



j 



Notes: *1. WE is high for read cycle. 

*2. Device is continuously selected, CS = Vil. 

*3. Address valid prior to or coincident with CS transition low. 



HITACHI 

246 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



■ Write Cycle 



Item 




Symbol 


HM6207H-25 


HM6207-35 
HM6207H-35 


HM6207-45 


Unit 








Min. 


Max. 


Min. 


Max. 


Min. 


Max. 




Write Cycle Time 


'wc 


25 


— 


35 


— 


45 


— 


ns 


Chip Selection to End of Write 


l cw 


20 


— 


30 




40 


— 


ns 


Address Valid to End of Write 


'aw 


20 




30 




40 




ns 


Address Setup Time 


'as 

















ns 


Write Pulse Width 




l wp 


20 




30 




35 




ns 


*'H" Version 




25 






Write Recovery Time 


l WR 


3 




3 




3 




ns 


Data Valid to End of Write 


l DW 


15 




20 










Data Hold Time 


•dh 

















ns 


Write Enabled to Output in High-Z 


'wz 





8 





10 





15 


ns 


Output Active From End of Write 


k>w 1 

















ns 



Note: *l Transition is measured ±200 raV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested. 



Write Timing Waveform (1) (WE Controlled) 



Addrr.s 



WE 



Oh 



DM 









) 


< ) 


( 










x\\\ v 


- - — : 


'///A 


'////, 




















\ / 


V 




to* 


tarn 




r 








Data Valid 


X 




-. 




to. 








> 


High Impedance 


< 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



247 



07H Series - 



Write Timing Waveform (2) (CS Controlled) 



> 


( 


> 


< 




If, 










\ 


/ 


/ 

In 




m - 


far 


\\\\\\\\\\\\\\\ s 




</////?/////, 






lam 




) 


V 


Data Valid ^ ^ 







H.nh 



Notes: *1. A write occurs during the overlap of a lo w CS and a low WE. 

*2. IWH is measured from the earlier of CS or WE going high to the end of write cycle. 

*3. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output huffers remain 

in a high impedance state. 
•4. Dout is the same phase of write data of this write cycle, if lw« is long enough. 



HITACHI 

248 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 







Low Vcc Data Retention Characteristics (T a = to +70°C) 



These characteristics are guaranteed only for L-version. 


Item 


Symbol 


Min 


Typ 


Max 


Unit 


Test Conditions 


Vcc for data retention 


Vdr 


2.0 






V 


CS > Vcc - 0.2 V, 
Vin > Vcc - 0.2 V or 
V< Vin<0.2 V 


Data retention current 


ICCDR 




1 


50- 2 


uA 


Chip deselect to data retention tir 


ne tcoR 









ns 


Operation recovery lime 




tRC - l 






ns 



Notes: •!. t»c = read cycle lime. 



Vcc = 3.0 V. 



Low Vcc Data Retention Timing Waveform 




Data retention mode 



CS£V„-0.2V 




PACKAGE DIMENSIONS Unit: mm (inch) 



HM6207P/HM(.207HP Series 
(DP-24NC) 



30*8™. (I 200ma. ) 

innnnnnnnnnn 



iUUUUUUULIU ITU U 

-rV- -fl- « 

«(Q.M5) I 3<00$i> 



Jl ,. S 3 EE 

48 • i 7 S4 • o?s S SIS 

019 t 0004) (0 100 - 010) ~ s 




HM6207HJP Series 
(CP-24D) 




f^lo lOiO owl 

4J + 10 

0i 't0 004 




<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 249 



HM6707 



262144-word x 1-bit High Speed Hi-BiCMOS Static RAM 



Features 

• Super Fast Access Time : 20/25ns (max.) 

• Low Power Dissipation 
Operating: 350mW (typ.) (f = 50MHz) 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Balanced Read and Write Cycle Time 

• Fully TTL Compatible Input and Output 



Ordering Information 

Type No. 



Access Time 



HM6707P-20 


20ns 


300mil 24 pin 


HM6707P-25 


25 ns 


Plastic DIP 


HM6707JP-20 


20ns 


300 mil 


HM6707JP-25 


25 ns 


24 pin SOJ 


Block Diagram 



A °- 
Ai o- 
A 2 °- 
A 3 o- 
A40- 
A50- 
A90- 
A10 °— 



Row 
Decoder 



256X1024 



Dino- 



WE°- 



5 — ^~ 


Column I/O 






Column Decoder 






> t^-«rvJ 


Ag A7 Ag An ~ A17 



Vcc 



Dout 



HM6707P 




(DP-24NC) 



HM6707JP 




(CP-24D) 



Pin Arrangement 




(Top View) 



Note) The specifications of this device are subject to change without notice. 
Please contact Hitachi's Sales Dept. regarding specifications. 



HITACHI 



, CA 94005-1819 • (t 



Ahtcnliitp Mavimum RatinfK 
nujuiuic itioai ■ ■ iui 11 naiiiiys 














Item 


Symbol 


Rating 


Unit 








Terminal Voltage to V ss Pin 


V T 


-0.5 to +7.0 


V 








Power Dissipation 


P T 


1.0 


W 








Operating Temperature Range 


T 

' opr 


to +70 


°c 








Storage Temperature Range (with bias)r s ff (bias) 


-10 to +85 




°c 






Storage Temperature Range 


T stg 


-55 to +125 


"C 






















Recommended DC Operating Conditions (Ta = to +70°C) 










Item 


Symbol 


min. 


typ. 


max. 


Unit 




Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 




Vss 











V 




Input Voltage 


v m 


2.2 




6.0 


V 




V IL 


-0.5" 


- 


0.8 


V 




Note) *1 : -3.0 V for pulse width 20ns. 












Function Table 

CS WE 


Mode 




V cc Current 




Output Pin 




H X 


Not selected 








High Z 




L H 


Read 




hc< ! CCl 




Dout 




L L 


Write 








High Z 





DC and Operating Characteristics {V cc 


= 5v±io%,r fl = 


Oto +70°C) 






Item 


Symbol 


min. 


typ. 


max. 


Unit 




Input Leakage Current 


i hi i 






2 


uA 


^ CC = 5.5V, V IN *V ss to V cc 


Output Leakage Current 








10 


MA 


cs = v IH , V OUT =V ss to V cc 


Operating Power Supply Current 


fee 






100 


mA 


CS= V IL ,I OUT = 0mA 


Average Operating Current 


! CC1 






120 


mA 


Min. Cycle, Duty : 100%,/ or jr = 0n 




>SB 






30 


mA 


CS= V IH _ V IN =V IH orV IL 


Standby Power Supply Current 


'SBI 






10 


mA 


CS> C cc -0.2 V 

V m g 0.2 V or V lN g V cc -0.2V 


Output Low Voltage 


Vol 






0.4 


V 


Iql ~ 8 mA 


Output High Voltage 


Vqh 


2.4 






V 


Iqh ■ -4 mA 

















HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 251 



HM6707 Series 



Capacitance (T a = 25°C,/= 1 MHz) 





Item 


Symbol 


max. 


Unit 


Test Conditions 




Input Capacitance 




6.0 


pF 


V IN = 0V 




Output Capacitance 


C OUT 


10.0 


pF 


V OUT = 0\ 



Note) This parameter is sampled and not 100% tested. 



AC Characteristics ( V cc = 5 V±10%, T a = to +70°C, unless otherwise noted) 

AC Test Conditions 

• Input pulse levels: Vss to 3.0 V 

• Input timing reference levels : 1.5 V 

• Output Load : See Figure 

• Input rise and fall times : 4 ns 

• Output reference levels ; 1.5 V 



1 




Output Load A Output Load B 

(for t H z. tLZ. t\VZ & f Ow) 



Read Cycle 



Item 




HM6707-2O 


HM6 707-25 


— Unit 


Notes 


Symbol - 


min. 


max. 


min. 


max. 




Read Cycle Time 


'rc 


20 




25 




ns 




Address Access Time 


'aa 




20 




25 


ns 




Chip Select Access Time 


'ACS 




20 




25 


ns 




Output Hold from Address Change 


'oh 


5 




5 




ns 




Chip Selection to Output in Low Z 


'lz 


5 




5 




ns 


1,2 


Chip Deselection to Output 
in High Z 


'hz 





15 





15 


ns 


1,2 



Note) 1 . This parameter is sampled and not 100% tested. 

2. Transition is measured ±200 mV from steady state voltage with specified loading in Load B. 



HITACHI 

252 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6707 Series 



Read Cycle- V 



Address 



Data Out 



tRC 



tAA 



tOH 



Previous Data Valid 



Data Valid 



Read Cycle-2* 2 







C5 



tACS ► 



Data Out High Impedance 




/ 



Data Valid 




High Impedance 



Notes) • 1 . WE is high and T!5~is low for Read cycle. 

•2. Addresses valid prior to or coincident with CS transition low. 

*3. Transition is measured ±200 mV from steady state voltage with specified loading in Load B. 
Write Cycle 



Item 


Symbol - 


min. max. 


min. 


max. 


- Unit 


Notes 


Write Cycle Time 


'wc 


20 


25 




ns 


2 


Chip Selection to End of Write 


<cw 


IS 


20 




ns 




Address Valid to End of Write 


'aw 


15 


20 




ns 




Address Setup Time 


'AS 










ns 




Write Pulse Width 


'wp 


15 


20 




ns 






Write Recovery Time 


'WR 


3 


3 




ns 




Data Valid to End of Write 


'dw 


15 


20 




ns 




Data Hold Time 


'dh 










ns 




Write Enable to Output in High Z 


'wz 


15 





15 


ns 


3,4 


Output Active from End of Write 


'ow 










ns 


3,4 



Note) 1 . If CS goes high simultaneously with WE high, the output remains in a high impedance state. 

2. All Write Cycle timings are referenced from the last valid address to the first transitioning address. 

3. Transition is measured ±200 mV from steady state voltage with specified loading in Load B. 

4. This parameter is sampled and not 100% tested. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 253 



HM6707 Series 

Write Cycle-1 (WE Controlled) 



Address 



CS 



WE 



Data In 



Data Out 



3 


4 twc ► 




( i 


< 


4 k; W ► 








^ ? 


<■/, 


'/// 




4 t/ 

4\ t AS ■ ► 


lW ■ ► 


<- twR -> 




4 


4 t W p ► 

s ? 

tDW ► 




)i 


Data In Valid 


)( 




*i 

<- t W z -*- 


*1 

•4- t 0W - 





Data Undefined 



) ( 

/I High Impedance (\ 



Note) *1 . Transition is measured ±200 mV from steady state voltage with specified loading in Load B. 



Write Cycle-2 (CS Controlled) 







Address 



CS 



Data In 



Data Out 





■4 twc ► 




■ \ 


/ s 


/ 




* *A8 *L tc, w * 








\ 7 


t 




4 


- tAW ► 


«- twR H 


wwwv 


4 twp ► 

K 1 


'-//I// 




trjw ► 




X 


Data In Valid ^ 




* twz'*- 



Data Undefined 



/[ High Impedance 



Note) *1 . Transition is measured ±200 mV from steady state voltage with specified loading in Load B. 

*2. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output 
buffer remains in a high impedance state. 



HITACHI 

254 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6707A Series — Product Preview 



262144-Word x 1-Bit High Speed Static RAM 

■ FEATURES 

• Super Fast 

Access Time 15/20/25ns (max.) 

• Low Power Dissipation 400mW (typ.) 

• +5V Single Supply 

• Completely Static Memory 

No Clock or Timing Strobe Required 

• Fully TTL Compatible Input and Output 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM6707AP-15 


15ns 


300 mil 24 pin 


HM6707AP-20 


20ns 


Plastic DIP 


HM6707AP-25 


25ns 


(DP-24NC) 


HM6707AJP-15 


15ns 


300 mil 24 pin 


HM6707AJP-20 


20ns 


Plastic SOJ 


HM6707AJP-25 


25ns 


(CP-24D) 




(DP-24NC) 



(CP-24D) 



■ BLOCK DIAGRAM 



A 2 O- 
A 3 O- 
A 4 O- 
A 7 O- 
A 8 O- 
A 9 C- 
A 5 o- 
A 6 O- 



Din o- 



-cs: 
-cs: 

Decodei 

— 1> 







Memory Matrix 
256x1024 



"S3 



WEO- 



Column Decoder 



A 12 A 13 A 14 A 10 A 1 1 A 15 A 16 A 17 A A 1 



PIN ARRANGEMENT 















Ao □ 




24 


□ Vcc 


A1 C 


2 


23 


□ A17 


A 2 C 


3 


22 


□ A16 


A 3 C 


4 21 


□ Ais 


A 4 C 


5 


20 


□ A14 




6 


19 


□ A13 


A 6 C 


7 


18 


□ A12 


AtC 


8 


17 


□ An 


a 8 n 


9 


16 


□ A10 


Dout C 


10 


15 


□ A 9 


WE □ 


11 


14 


□ Din 


vss C 


12 


13 


□ CS 




(Top View) 






HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 55 



HM6707A Series 



ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage to V ss Pin 


V T 


-0.5 to +7.0 


V 


Power Dissipation 


P T 


1.0 


W 


Operating Temperature Range 


T opr 


to +70 


°c 


Storage Temperature Range (with bias) 


TstE(bias) 


-10 to +85 


°c 


Storage Temperature Range 


T st« 


-55 to + 125 


°C 


■ RECOMMENDED DC OPERATING CONDITIONS (0°C < T. < 


70°C) 







Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 


0.0 


0.0 


0.0 


v 


Input High Voltage 


V,H 


2.2 




V cc + 0.5 


v 


Input Low Voltage 


VlL 


-3.0* 




0.8 


1 

V 



*Pulse width: 15ns, DC: -0.5V 
■ TRUTH TABLE 



CS 


WE 


Mode 


V C c Current 


Output Pin 


H 


X 


Not Selected 


Isb. Isbi 


HighZ 


L 


H 


Read 


Ice Icci 


Data Out 


L 


L 


Write 


Ice Icci 


HighZ 



DC AND OPERATING CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, V ss = 0V) 



Item 


Symbol 


Test Condition 


Min. 


Typ. 


Max. 


Unit 


Input Leakage Current 


Uul 


V cc = 5.5V, V IN = V ss to V cc 






2 


fiA 


Output Leakage Current 


HloI 


CS = V IH , V 0UT = V ss to V cc 






10 


liA 


Operating Power Supply Current 


Ice 


cs = v i L , I 0UT = 0mA 






100 


mA 


Average Operating Current 


Icci 


Min. Cycle, Duty: 100%, I ut = 0mA 






120 


mA 




Isb 


CS = V IH , V IN = V IH orV IL 






30 


mA 


Standby Power Supply Current 


Isbi 


CS > V cc - 0.2V 

V IN < 0.2V or V IN > V cc - 0.2V 






10 


mA 


Output Low Voltage 


Vol 


Iol = 8mA 






0.4 


V 


Output High Voltage 


Vqh 


Iqh = -4mA 


2.4 






V 



■ AC TEST CONDITIONS 

• Input Pulse Levels: V ss to 3.0V 

• Input Timing Reference Levels: 1.5V 

• Output Reference Levels: 1.5V 



• Input Rise and Fall Times: 4ns 

• Output Load: See Figure 



Dout 



255 



+5V 
I 4800 



\ : : 30 pF* 



Dout 

o— 



+5 V 
4800 



2550 



? 4= 



/77 

Output Load A 



S77 



5pF* 



Output Load B 
(for t HZ , t LZ , t wz & tow) 



♦Including scope and jig capacitance. 



HITACHI 

256 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM6707A Series 



■ CAPACITANCE (T a = 25°C, f = 1.0MHz) 



Item 


Symbol 


Test Conditions 


Max. 


Unit 


Input Capacitance 




v, N = ov 


6.0 


pF 


Output Capacitance 


C OUT 


VOUT = OV 


10.0 


pF 



NOTE: This parameter is sampled and not 100% tested. 

■ AC CHARACTERISTICS (V cc = 5V ± 10%, T a = 0°C to 70°C, unless otherwise noted.) 
• Read Cycle 



Item 


Symbol 


HM6707A-15 | HM6707A-20 


HM6707A-25 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


l RC 


15 




20 




25 




ns 




Address Access Time 


l AA 




15 




20 




25 


ns 




Chip Select Access Time 


'ACS 




15 




20 




25 


ns 




Output Hold from Address Change 


•oh 


3 




3 




3 




ns 




Chip Selection to Output in Low Z 


tLZ 


3 




3 




3 




ns 


1,2 


Chip Deselection to Output in High Z 


'HZ 





6 





8 





10 


ns 


1,2 


NOTES: I. This parameter is sampled and not 100% tested. 

2. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

• Write Cycle 


Item 


Symbol 


HM6707A-15 


HM6707A-20 


HM6707A-25 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


<wc 


15 




20 




25 




ns 


1 


Chip Selection to End of Write 


'cw 


10 




15 




20 




ns 




Address Valid to End of Write 


l AW 


10 




15 




20 




ns 




Address Setup Time 


'as 

















ns 




Write Pulse Width 


'wp 


10 




15 




20 




ns 




Write Recovery Time 


'WR 

















ns 




Data Valid to End of Write 


•dw 


9 




12 




15 




ns 




Data Hold Time 


'dh 

















ns 




Write Enable to Output in High Z 


'wz 





6 





8 





10 


ns 


2, 3 


Output Active from End of Write 


'ow 

















ns 


2, 3 



NOTES: 1 . All write cycle timings are referenced from the last valid address to the first transitioning address. 

2. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

3. This parameter is sampled and not 100% tested. 



# HITACHI 

a, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 257 



HM6707A Series 



I TIMING WAVEFORM 
Read Cycle (1)0) 



Address 



X 



tOH 



tRC 



tAA 



Data Out Previous Data Valid ^QQOOOC Data Valid 



X 



• Read Cycle (2) ( 



Data Out 



tRC 



'ACS 



tLZ O) 



Impedence 







tHZ P) 



Data Valid 



High 

Impedence 



NOTES: 1 . WE is high and CS is low for READ cycle. 

2. Addresses valid prior to or coincident with CS transition low. 

3. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



HITACHI 



258 



HM6707A Series 



Write Cycle (1) (WE Controlled) 



Address 



twc 



C8 



Jcw_ 



tAW 



, ///////////////, 



tAS 



WE 

Data In 
Data Out 



twp 



tDW 



X 







tDH 



Data In Valid 



twz 



Data Undefined 







tow 



JUJSL 



High Impedance 



K. 



NOTES: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 

2. If CS goes high simultaneously with WE high, the output remains in a high impedance state. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 259 



HM6707A Series 



Write Cycle (2) (CS Controlled) 



Address 



CS 



Data In 
Data Out 



V 

_/ 


< > 
















sj 


S 7 


/ 




tAW 




t W P 




:< > 


V/////////////. 




i tDW > 


l DH 






Data In Valid ^ 


< 



twz 



Data Undefined ) > 



High Impedance 



NOTES: 1. Transition is measured ±200mV from steady state voltage with specified loading in Load B. 



HITACHI 

260 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • 



HM628128 Series 



131072-Word x 8-Bit High Speed CMOS Static RAM 



The Hitachi HM628128 is a CMOS static RAM organized 128- 
kword x 8-bit. It realizes higher density, higher performance and low 
power consumption by employing 0.8 u.m Hi-CMOS process 
technology. 

It offers low power standby power dissipation; therefore, it is 
suitable for battery back-up systems. The device, packaged in a 525 
mil SOP (460-mil body SOP) or a 600-mil plastic DIP, is available for 
high density mounting. 



Features 

• High speed: Fast access time 70/85/100/120 ns (max.) 

• Low power 

Standby: 10 uW (typ) (L-version) 
Operation: 75 mW (typ) 

• Single 5 V supply 

• Completely static memory 

No clock or timing strobe required 

• Equal access and cycle times 

• Common data input and output: Three state output 

• Directly TTL compatible: All inputs and outputs 

• Capability of battery back up operation (L-version) 

2 chip selection for battery back up 



HM628128P Series 




(DP-32) 



HM628128FP Series 




(FP-32D) 



Ordering Information 



Type No. 



HM628128P-7 
HM628128P-8 
HM628128P-10 
HM628128P-12 



HM628128LP-7 
HM628128LP-8 
HM628128LP-10 
HM628128LP-12 



HM628128FP-7 
HM628128FP-8 
HM628128FP-10 
HM628128FP-12 



HM628128LFP-7 
HM628128LFP-8 
HM628128LFP-10 
HM628128LFP-12 



Access Time 



Package 



70 ns 
85 ns 
100 ns 
120 ns 



70 ns 
85 ns 
100 ns 
120 ns 



600 mil 32-pin 
plastic DIP 
(DP-32) 



70 ns 
85 ns 
100 ns 
120 ns 



70 ns 
85 ns 
100 ns 
120 ns 



525 mil 32-pin 
plastic SOP 



Note: The specifications of this device are suhject to change without notice. 

Please contact your nearest Hitachi's Sales Dept. regarding 
specifications. 



Pin Arrangement 




Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 261 



Pin Description 



Pin Name 


Function 


A0-A16 


Address 


I/O0-I/O7 


Input/output 


csl 


Chip select 1 


CS2 


Chip select 2 


WE 


Write enable 


OE 


Output enable 


NC 


No connection 


Vcc 


Power supply 


Vss 


Ground 



Block Diagram 



A13°- 
A15°- 



A6 o- 
A5 o- 
A4 o- 



l/OO o- 







Row 

Decoder 



Memory Matrix 
512X2,048 



Input 
Data 
Control 



Column I/O 



Column Decoder 



3 5 5 5 5~~ 

>9 An A10 AO A1 A2 A3 



Timing Pulse Gen. 
Read/Write Control 



| V ss 




Function Table 



WE 


CS1 


CS2 


OE 


Mode 


Vcc Current 


Dout Pin 


Ref. Cycle 


X 


H 


X 


X 


Not selected 


Isb, Isbi 


High-Z 




X 


X 


L 


X 


ISB, ISBI 


High-Z 




H 


L 


H 


H 


Output disable 


Ice 


High-Z 




H 


L 


H 


L 


Read 


Ice 


Dout 


Read cycle 


I. 


L 


H 


H 


Write 


Ice 


Din 


Write cycle ( 1 ) 


L 


L 


H 


L 


Ice 


Din 


Write cycle (2) 



Note: x : H or L 



HITACHI 

262 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • E 



HM628128 Series 



Absolute Maximum Ratings 



Item 




Symbol 




Value 


Unit 


Voltage on any pin relative to Vss 




Vt 




-0.5*' to +7.0 V 


Power dissipation 




Pt 




1.0 


W 


Operating temperature 




Topr 




to +7C 


°C 


Storage temperature 




Tstg 




-55 to +125 °C 


Storage temperature under bias 




Tbias 




-10 to +85 °C 


Note: * 1 . -3.0 V for pulse half -width < 30 ns 










Recommended DC Operating Conditions ( Ta = to +70°C ) 




Item Symbol 


Min 


Typ 


Max 


Unit Note 


Supply voltage 


Vcc 


4.5 


5.0 


5.5 


V 




Vss 











V 


Input high (logic 1 ) voltage 


VlH 


2.2 




6.0 


V 


Input low (logic 0) voltage 


Va. 


-0.3' 1 




0.8 


V 


Note: * 1 . -3.0 V for pulse half -width < 30 ns 










DC Characteristics ( Ta = to +70°C, Vcc 


= 5V+10%,Vss = 


V) 




Item 


Symbol 


Min Typ* 1 


Max 


Unit 


Test Conditions 


Input leakage current 


Bul 




2 


HA 


Vin = Vss to Vcc 


Output leakage current 


ILol 




2 


uA 


CSl = Vm or CS2 = Va. or 
OE = Vm orWE = Vu., 
Vi/o= Vss to Vcc 


Operating power supply current: DC 


Ice 


— 15 


30 


mA 


CS1= VtL, CS2 = Vm, 
others = Vih/V n. 
Ii/o= mA 


Operating power supply current 


lea 


— 45 


70 


mA 


Min cycle, duty = 100%, 
CS1 = Vil, CS2 = Vm, 
others = Vui/Vil 
Ii/o = mA 


ICC2 


- 15 


30 


mA 


Cycle time = 1 \is, 

duty = 100%, Ii/o = mA 

CSl < 0.2 V, CS2 > Vcc - 0.2 V 

Vm> Vcc -0.2V, Vu.<0.2V 


Standby power supply current: DC 


ISB 


— 1 


3 


mA 


CSl = Vm, CS2 = Vm 
or CS2 = Vil 


Standby power supply current (1): DC 




— 0.02 


2 


mA 


Vin>0V 

CSl > Vcc -0.2 V, 


Ism 


— 2' 2 


100* 2 


uA 


CS2> Vcc- 0.2 Vor 
V < CS2 < 0.2 V 


Output low voltage 


Vol 




0.4 


V 


Iol = 2.1 mA 


Output high voltage 


VOH 


2.4 — 




V 


Ion = -1.0 mA 



Notes: *1. Typical values arc al Vcc = 5.0 V, Ta = +25°C and specified loading. 
*2. This characteristics is guaranteed only for I.-version. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



263 



HM6281 28 Series 



Capacitance ( Ta = 25°C, f = 1 .0 MHz ) 



Ilem 


Symbol 


Min 


Typ 


Max 


Unit 


Test Conditions 


Input capacitance 


Cin 






8 


pF 


Vin = V 


Input/output capacitance 


Cvo 






10 


pF 


Vi/o = V 



Note: This parameter is sampled and not 100% tested. 



AC Characteristics ( Ta = to +70°C, Vcc = 5 V + 10%, unless otherwise noted ) 
Test Conditions 

• Input pulse levels: 0.8 V to 2.4 V • Input and output timing reference levels: 1 .5 V 

• Input rise and fall times :5 ns • Output load: 1 TTL Gate and CL (1 OOpF) 

(Including scope & jig) 



Read Cycle 



Item 


Symbol 


HM628128-7 


HM628128-8 


HM628128-10 


HM628128-12 


Unit 


Note 


Min 


Max 


Min 


Max 


Min 


Max 


Min 


Max 


Read cycle time 


tRC 


70 




85 




100 




120 




ns 




Address access time 


tAA 




70 




85 




100 




120 


ns 




Chip selection (CS1) 


tcoi 




70 




85 




100 




120 


ns 





to output valid 
























Chip selection (CS2) 


tC02 


_ 


70 




85 




100 




120 


ns 




to output valid 
























Output enable (OE) 


tOE 




35 




45 




50 




60 


ns 




to output valid 
























Chip selection (CS1) 


tLZl 


10 




10 




10 




10 




ns 


•1,-2. »3 


to output in low-Z 
























Chip selection (CS2) 


tLZ2 


10 




10 




10 




10 




ns 


•l."2.*3 


to output in low-Z 
























Output enable (OE) 


tOI.Z 


5 




5 




5 




5 




ns 


•1,'2.'3 


to output in low-Z 
























Chip deselection (CS 1 ) 


ntzi 





25 





30 





35 





45 


ns 


•1.-2. *3 


to output in high-Z 
























Chip deselection (CS2) 


UIZ2 


o 







30 





35 





45 


ns 


•1. -2. -3 


to output in high-Z 
























Output disable (OE) 


totiz 





25 





30 





35 





45 


ns 


•1,-2. »3 


to output in high-Z 
























Output hold from 
address change 


ton 


10 




10 




10 




10 




ns 





HITACHI 

264 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 



HM6281 28 Series 



Read Timing Waveform' 



3( 



Ue 



w W\\\W! 



CS2 



*co2 



- wwwwwv - 



toe 



2 2 



Data Valid 



77777 



tnZl 



T ZZZZZ 



;<x>- 



Notes: *1. foot and Iohz are defined as ihc lime at which the outputs achieve the open circuit condiiions and are not referenced to output 
voltage levels. 

*2. At any given temperature and voltage condition, ttrz max is less than Ilz min both for a given device and from device to device. 
*3. This parameter is sampled and not 100% tested. 
*4. WE is high for read cycle. 



Write Cycle 



Item 


Symbol - 


HM628128-7 








8128-10 


HM628128-12 


Unit Note 




Min 


Max 


Min 


Max 


Min 


Max 


Min 


Max 




Write cycle time 


twe 


70 




85 




100 




120 




ns 


Chip selection to 


tew 






75 




90 




100 




ns 


end of write 






















Address setup time 


Us 






















ns 


Address valid to 


Uw 


60 




75 




90 




100 




ns 


end of write 






















Write pulse width 


twp 


55 




65 




75 




85 




ns 


Write recovery time 


tWR 


5 




5 




5 




10 




ns 






10 




10 




10 




15 




ns *11 


Write to output 


twiiz 





25 





30 





35 





40 


ns *10 


in high-Z 






















Data to write time 


tDW 


30 




35 




40 




45 




ns 


overlap 






















Write hold from 


tt>H 







— 












ns 


write time 






















Output active from 


tow 


5 


- 


5 




5 




5 




ns *10 


end of write 























HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 65 



HM628128 Series 



Write Timing Waveform (1) (OE Clock) 



Address 



OE 7 



77777 ZZZI 



CSl 



CS2 



WE 



Din 



t»c 



/////7777 T, 7 



WWW 
7ZZZZZZ2 



wwwwv 

////////// 



Ik 



Write Timing Waveform (2) (OE Low Fix) 



3( 



CS2 7 



zz 



WF 







//// / 



ziZZ 







3 r 



7///// 



hud® 



Notes: *1. A write occurs during the overl ap of a low CST, a high CS2 and a low WE. A write begins at the latest transition among CSl 
goi ng lo w, CS2 going high and WE going low. A write ends at the earliest transition among CSl going high, CS2 going low 
and WE going high, twp is measu red f rom the beginning of write to the end of write. 

*2. tew is measured from the later of CSl going low or CS2 going high to the end of write. 

*3. tAS is measured from the address val id to th e beg inning of write. 

*4. tWR is measured from the earliest of CSl or WE going high or CS2 going low to the end of write cycle. 
*5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not 
be applied. 



266 



<P HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM628128 Series 

*6. If CS1 goes low simultaneously with WE going low or after WE going low, the outputs remain in high impedance state. 

*7. Dout is the same phase of the latest written data in this write cycle. 

*8. Pout is the read data of next address. 

•9. If CS1 is low and CS2 is high during this period, I/O pins are in the output state. Therefore, the input signals of the opposite 
phase to the outputs must not be applied to them. 

*10. This parameter is sampled and not 100% tested. 

* 1 1 . This value is measured from CS2 going low to the end of write cycle. 



Low Vcc Data Retention Characteristics ( Ta = to +70°C ) 
(This characteristics is guaranteed only for L-version.) 



Item 


Symbol 


Min 


Typ 


Max 


Unit 


Test Conditions" 2 














CS1 > Vcc- 0.2 V, 


Vcc for data retention 


Vdr 


2.0 






V 


CS2> Vcc -0.2 V 
or V < CS2 < 0.2 V 
Vin>0 V 














Vcc = 3.0 V, Vin>0 V 


Data retention current 


ICCDR 




1 


50* 1 


uA 


CS1> Vcc -0.2 V, 
CS2>Vcc-0.2 Vor 
OV<CS2<0.2V 


Chip deselect to data retention time 


tCDR 









ns 


See Retention Waveform 


Operation recovery time 


tR 


5 






ms 

















<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 267 



HM6281 28 Series 



Low Vcc Data Retention Timing Waveform (1) (CS1 Controlled) 



- Data Retention Mode 




Low Vcc Data Retention Timing Waveform (2) (CS2 Controlled) 



Data Retention Mode- 




Noles : • 1 . 20 uA max al Ta=0 to 40°C. 

*2. CS2 controls addres s buffer, WE buffer, CS1 buffer and OE buffer and Din b uffer. If CS2 controls data retention mode, Vin 
levels (address, WE, OE, CS1, I/O) can be in the high impedance slate. If CS1 controls data retention mode, CS2 must be CS2 
> Vcc- 0.2 V or V < CS2 < 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 



HITACHI 

268 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM624256 Series 
4-Bit CMOS 



HM624256 SERIES 

262144-WORD x 4-BIT HIGH SPEED CMOS STATIC 

The Hitachi HM624256 is a high speed 1M static RAM 
organized as 256-kword x 4-bit. it realizes high speed access 
time (35/45 ns) and low power consumption, employing CMOS 
process technology and high speed circuit designing technology. 
It is most advantageous for the field where high speed and high 
density memory is required, such as the cache memory for main 
frame or 32-bit MPU. 

The HM624256, packaged in a 400-mil plastic SOJ is 
available for high density mounting. 

■ FEATURES 

• Single 5 V supply and high density 28-pin 
package (DIP and SOJ) 

• High speed: Fast access time 35/45 ns (max.) 

• Low power 

Operation: 350 mW (typ.) 
Standby: 100 /iW (typ.) 

• Completely static memory: 

No clock or timing strobe required 

• Equal access and cycle time 

• Directly TTL compatible: All inputs and outputs 

■ ORDERING INFORMATION 



RAM 




(DP-28C) 



(CP-28D) 



PIN ARRANGEMENT 



Type No. 


Access Time 




HM624256P-35 


35 


ns 


400 mil 


HM624256P-45 


45 


ns 


28-pin 


HM624256LP-35 


35 


ns 


Plastic DIP 


HM624256LP-45 


45 


ns 


(DP28C) 


HM624256JP-35 


35 


ns 


400 mil 


HM624256JP-45 


45 


ns 


28-pin 


HM624256UP-35 


35 


ns 


Plastic SOJ 


HM624256UP-45 


45 


ns 


(CP-28D) 



■ PIN DESCRIPTION 



Pin Name 


Function 


A 0" A I7 


Address 


i/o,-i/o 4 


Input/Output 


CS 


Chip Select 


OE 


Output Enable 


WE 


Write Enable 


Vcc 


Power Supply 


v ss 


Ground 



(DIP and SOJ) 

Top View 




Note: The specifications of this device are subject to change without notice. 
Please contact your nearest Hitachi's Sales Dept. regarding spi 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM624256 Series - 



BLOCK DIAGRAM 



_ 




Memory Array 
■ 256X1,024 



-V cc 



Column I/O 



Column Decoder 



A9 A10AI1AI2AI3AUAI5A16A17 



FUNCTION TABLE 







cs 


OE 


WE 


Mode 


Vcc Current 


I/O Pin 


Ref. Cycle 


H 


X 


X 


Not Selected 


[ SB. 'sbi 


High-Z 




— ^ 


L 


H 


Read 


I cc 


D„m 


Read Cycle* 'H3) 




H 


L 


Write 


'cc 


Din 


Write Cycle'" 




L 


L 


W te 


'cc 


Din 


Write Cycle* 2 ' 



NOTE: X : H or L 

■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Value 


Unit 




Voltage on any Pin Relative to V ss 


v T 


-0.5* 1 to +7.0 


V 




Power Dissipation 


Pt 


1.0 


W 





Operating Temperature Range 


T 


Oto +70 






Storage Temperature Range 


T stg 


-55 to + 125 


°C~~ 





Storage Temperature Range Under Bias 


T bias 


-10 to +85 


°C 



. V T min. = -2.0 V for pulse width < 10 ns. 



270 



HITACHI 



) • (415) 589-8300 



HM624256 Series 



RECOMMENDED DC OPERATING CONDITIONS (T a = to +70°C) 



hem 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 











v 


Input High (Logic 1) Voltage 


VlH 


2.2 




6.0 


V 


Input Low (Logic 0) Voltage 


ViL 


-0.5*' 




0.8 


V 



NOTE: * 1 . V IL min. « -2.0 V for pulse width s KP ns. 

■ DC CHARACTERISTICS (T a = to +70°C, V cc = 5 V ± 10%, = V) 



Item 


Symbol 


Min. 


Typ.* 1 


Max. 


Unit 


Test Conditions 


Input Leakage Current 


Hul 






2.0 


nA 


Vcc = max. 

Vi„ = V ss toV cc 


Output Leakage Current 


HloI 






2.0 


fA 


cs = v IH 

v„„, = v ss to v cc 


Operating Power Supply Current 


•cc 




70 


120 


mA 


CS = V IL , I oul = mA. 
min. cycle 


Standby Power Supply Current 


he 




30 


60 


mA 


CS = V JH , min. cycle 


Standby Power Supply Current (I) 


ISB,* 2 




0.02 


2.0 
0.2 


mA 
mA 


CS a V cc - 2 V 
V < V m < 0.2 V or 
V ln a V cc - 0.2V 


Output Low Voltage 


Vol 






0.4 


V 


I l = 8 mA 


Output High Voltage 


V oh 


2.4 






V 


'oh = -*-0 mA 



NOTES: * I . Typical limits are at V cc = 5.0 V. T, = 25°C amd specified loading. 
•2. JP-version 
*3. UP-version 

■ CAPACITANCE (T a = 25°C, f = 1MHz) 



Item 


Symbol 


Min. 


Max. 


Unit 


Test Conditions 


Input Capacitance 


c,„ 




6 


PF 


Vi„ = 0V 


Input/Output Capacitance 


C ! O 




11 


pF 


V„o = 0V 



NOTE: I. This 

■ AC CHARACTERISTICS (T a = to +70°C, V cc = 5 V ± 10%, unless otherwise noted.) 
Test Conditions 

. • Input pulse levels: V ss to 3.0 V 
• Input rise and fall times: 5 ns 



• Input and output timing reference 

• Output load: See Figures 



: 1.5 V 



Output Load (A) 

+5V 



Output Load (B) 
(for t,; HZ , leu, t WHZ & tow) 

+5V 



Dout O- 



480Q 



I 30pF' 



Dout O- 



5pF* 



777- 



777 



NOTE: 'Including scope & jig. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 271 



■ Read Cycle 



Item 
.em 


Symbol 


HM624256-35 


HM624256-45 


Unit 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


•rc 


35 




45 


- 


ns 


Address Access Time 


'aa 




35 




45 


ns 


Chip Select Access Time 


'ACS 




35 




45 


ns 


Chip Selection io Output in Low-Z 


'CLZ ' 


10 




10 


- 


ns 


Output Enable to Output Valid 


lOE 




18 




23 


ns 


Output Enable to Output in Low-Z 


Iolz' 1 - 




ns 


Chip Deselection to Output in High-Z 


<CHZ'' 





20 





20 


ns 


Chip Disable to Output in High-Z 


'OHZ*' 





10 





15 


ns 


Output Hold From Address Change 


■oh 


5 




5 




ns 


Chip Selection to Power Up Time 


tpu 












ns 


Chip Deselection to Power Down Time 


'PD 




30 




30 


ns 



Read Timing Waveform (1) "i, "2 



OF 



cs 



3C 



Y 



Read Timing Waveform (2) *i. *3. *s 



t«. 



tot 



ten 



X 



I 



I'jL 



Oout 



XXXSX 



w- 



X 



XX 



HITACHI 

272 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM624256 Series 



Read Timing Waveform (3) "•■ '*. "« 

IS 



Ooul 



I 



ten 



> 



•l. Transition is measured ±200 mv from steady state voltage with Load <B). This parameter is sampled and not 100% tested. 

"2 WE is high for read cycle 

•3. Device is continuously selected, CS = Vil. 

*4. Address valid prior to or coincident with CS transition low. 

*5. OE = V| L . 



I Write Cycle 



Item 


Symbol 


HM624256-35 


HM624256-45 


Unit 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


t\vc 


35 




45 




ns 


Chip Selection to End of Write 


•cw 


30 




40 




ns 


Address Valid to End of Write 


l AW 


30 




40 




ns 


Address Setup Time 


'AS 












ns 


Write Pulse Width 


l WP 


30 




35 




ns 


Write Recovery Time 


>WR 


3 




3 




ns 


Output Disable to Output in High-Z* 1 


*OHZ 





10 





15 


ns 


Write to Output in High-Z* 1 


tWHZ 





10 





15 


ns 


Data to Write Time Overlap 


tDW 


20 




25 




ns 


Data Hold From Write Time 


<dh 












ns 


Output Active From End of Write" 1 


tow 












ns 



NOTE: 1 . Transition is measured ± 200 mV from 
This parameter is sampled and not 100% 

Write Timing Waveform (1) 



steady state voltage with Load (B). 



X 



OE 



CS 



t«c 



'-/zzzzzl 




K 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



273 



HM624256 Series - 



Write Timing Waveform (2) "« 



cs 



WE 



Din 



3 


two 

( \ 


l 

\__ 


V 




\ / 


'/> 


'//////// 












A\\\Y 
















))}))}}}))? 

r~ 


Wffl 

- — 



NOTES: *1 . Transition is measured ±200 inV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested. 
-2. A write occurs during the overlap (twp) of a low CS and a low WE. 
*3. iwr is measured from the earlier of CS or WE going high to the end of write cycle. 
•4. During this period. I/O pins are in the output stale so (hat the input signals of the opposite phase to the outputs must not be applied 
•5. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance slate. 
•6. 51 is continuously low. <OE = V| L ) 
*7. DouT is the same phase of write data of this write cycle. 
*8. DouT is the read data of rent address. 

■9. If CS is low during this period. I/O pins are the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 




274 



Hitachi America, Ltd. 



HITACHI 

• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM624257 Series 
4-Bit CMOS Static RAM 

HM624257 SERIES 
262144-WORD x 4-BIT HIGH 



STATIC RAM 



The Hitachi HM624257 is a high speed 1M static RAM 
organized as 256-kword x 4-bit. It realizes high speed access 
time (35/45 ns) and low power consumption, employing the 
advanced CMOS process technology and high speed circuit 
designing technology. It is most advantageous for the field where 
high speed and high density memory is required, such as the 
cache memory for main frame or 32-bit MPU. 

The HM624257, packaged in a 400-mil plastic SOJ is available 
for high density mounting. 

■ FEATURES 

• Single 5 V supply and high density 32-pin package (SOJ) 

• High speed: Access time 35/45 ns (max.) 

• Low power dissipation 

Active mode: 350 mW (typ.) 
Standby: 100 (typ.) 

• Completely static memory: 

No clock or timing strobe required 

• Equal access and cycle time 

• Directly TTL compatible: All inputs and outputs 



■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM624257JP-35 


35 ns 


400 mil 


HM624257JP^5 


45 ns 


32-pin 


HM624257UP-35 


35 ns 


Plastic SOJ 


HM624257UP-45 


45 ns 


(CP-32D) 



■ PIN DESCRIPTION 



Pin Name 


Function 


Ao- A I7 


Address 


I,-I 4 


Data Input 




Data Output 


CS 


Chip Select 


WE 


Write Enable 


V cc 


Power Supply 


Vss 


Ground 



Under Development 






PIN ARRANGEMENT 








R>p View 






NC □ 




32 


□ Vcc 




AO C 


2 


31 


□ A,7 




AllZ 


3 


30 


□ A 16 




A2C 


4 


29 


□ A15 




A3 □ 


5 


28 


□ A M 




A4C 


6 


27 


□ A13 




A5C 




26 


□ A,2 




A«C 


8 


25 


□ a„ 




A7C 


9 


24 


□ NC 




AeC 


10 


23 


□ n 




A9C 


11 


22 


□ "2 




Aio C 


12 


21 


□ o, 




uC 


13 


20 


□ « 






14 


19 


□ 03 




cs □ 


15 


18 


□ 04 




VSS C 


16 


17 


□ we 













HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 275 



HM624257 Series - 
■ BLOCK DIAGRAM 





A9 A10 All A12 A13 AH A15 A16 A17 




■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Value 


Unit 




Voltage on any Pin Relative to V ss 


v,„ 


-0.5' 1 to +7.0 


V 


Power Dissipation 


Pt 


1.0 


W 


Operating Temperature Range 


T 

*opr 


to +70 


°c 


Storage Temperature Range 


T sig 


-55 to + 125 


"C 


Storage Temperature Range Under Bias 


T bias 


-10 to +85 


' 

°c 



NOTE: • I , V, min. - -2.0 V for pulse widlh s 10 ns. 



■ FUNCTION TABLE 



cs 


WE 


Mode 


V cc Current 


D ou , Pin 


Ref. Cycle 


H 


X 


Not Selected 


Hb- 'sbi 


High-Z 


— 


L 


H 


Read 


Ice 


D»i 


Read Cycle 111 -' 2 ) 


L 


L 


Write 


Ice 


High-/ 


Write Cycle' " < 2 > 



NOTE: X : H or L 



HITACHI 

276 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM624257 Series 



■ RECOMMENDED DC OPERATING CONDITIONS (T, = to +70°C) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


V cc 


4.5 


5.0 


5.5 


V 


Vss 











V 


Input High (Logic 1) Voltage 


V,H 


2.2 




6.0 


V 


Input Low (Logic 0) Voltage 


V,L 


-0.5*' 




0.8 


V 



NOTE: • I . V, L min. = -2.0 V for pulse width s 10 ns. 



■ DC CHARACTERISTICS (T a = to +70°C, V cc = 5 V ± 10%, V ss = V) 



Item 


Symbol 


Min. 


Typ.'' 


Max. 


Unit 


Test Condilions 


Input Leakage Current 


(Jul 






2.0 


ctf 


V cc = max. 

Vi„ = V ss toV cc 


Output Leakage Current 


HloI 






10.0 


/•A 


cs = V IH 

V„o = v ss to V cc 


Operating Power Supply Current 


I C C 




70 


120 


mA 






min. cycle 


Standby Power Supply Current 


IsB 




30 


60 


mA 


CS = V| H , min. cycle 


Standby Power Supply Current (1) 


'SRI 




0.02 


2.0 


mA 


CS > V C c - 0.2 V 
0V<V|,< 0.2 V or 
V m > V cc -0.2V 


Output Low Voltage 


Vol 






0.4 


V 


Iql — 8 mA 


Output High Voltage 


V OH 


2.4 






V 


•oh = - 4 mA 


NOTE: 1 . Typical limits are al V„ = 5.0 V, T. = 


t-25"C and specif 


ed loading. 











■ CAPACITANCE (T, = 25°C, f = 1MHz) 



Item 


Symbol 


Min. 


Max. 


Unit 


Test Conditions 


Input Capacitance 






6 


pF 


V in = V 


Output Capacitance 


Com 




11 


PF 


Vou, = V 



NOTE: I . This patameler is sampled and noi 100% lested. 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 277 



HM624257 Series 



■ AC CHARACTERISTICS (T a = to +70°C, V cc = 5 V ± 10%, unless otherwise noted.) 
Test Conditions 



Input pulse levels: Vss to 3.0 V 
Input rise and fall times: 5 ns 



• Input and output timing reference levels: 1.5 V 

• Output load: See Figures 



Output Load (A) 
5V 



Output Load (B) 
(for t CHZ . t CLZ , t WH7 & tow) 
5V 



777" 



77T 



NOTE: 'Including scope & jig. 

■ Read Cycle 



Item 


Symbol 


HM624257-35 


HM624257-45 


Unit 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 




35 




45 




ns 


Address Access Time 


•aa 




35 




45 


ns 


Chip Select Access Time 


l ACS 




35 




45 


ns 


Output Hold From Address Change 


l OH 


5 




5 




ns 


Chip Selection to Output in Low-Z 


<LZ*' 


5 




5 




ns 


Chip Deselection to Output in High-Z 


l HZ 





20 





20 


ns 


Chip Selection to Power Up Time 


'pu 












ns 


Chip Deselection to Power Down Time 


>PD 








30 


ns 



NOTE: t. Transition is measured ±200 mV from steady voltage with Load (B). 
This parameter is sampled and not 100% tested. 



HITACHI 

278 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Read Timing Waveform (1) *i, ** 



HM624257 Scries 



x 



x 



D™i 



)<EEEEX>C 



Timing Wavefori 

cs 



1(2)- 



\ 


/ 


lm 


bca 




— - — 1000000 


^ D.u VJid 


y- 




High Impedance 




High Impedance 



lm 

NOTES: * I . WE is high for read cycle. 

*2. Device is continuously selected, CS = V|j,. 
*3 Address valid prior to or coincident with CS U 

■ Write Cycle 



Item 


Symbol 


HM624257-35 


HM624257-45 


Unit 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


twe 


35 




45 




ns 


Chip Selection to End of Write 


■cw 


30 




40 




ns 


Address Valid to End of Write 


'aw 


30 




40 




ns 


Address Setup Time 


Us 












ns 


Write Pulse Width 


>wp 


30 




35 




ns 


Write Recovery Time 


'WR 


3 




3 




ns 


Data Valid to End of Write 


tDW 


20 








ns 


Data Hold Time 


>DH 


3 




3 




ns 


Write Enabled to Output in High-Z 


twz' 1 





15 





20 


ns 


Output Active From End of Write 


tow" 


5 




5 




ns 



NOTE: I . Transition is measured ±200 mV from 
This parameter is sampled and not 100% 



(B) 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



279 



HM624257 Series 



Write Timing Waveform (1) (WE Controlled) 



X 



r 



WE 



KXXXXXXXX XX^XX 



r 



- ((((((((((( v 

Write Timing Waveform (2) (CS Controlled) 

Address ^ ^ 



Hi«h 



rx> :xxxxx) 



CS 



wi; 



r 



XXXXXXXXXXXX X 



Dout 



Hinh 



77777 



XEX XXXX 



NOTES: * I . A write occurs during ihe overlap of a to* CS and a low WE. 

•2. iwr is measured from rhc earlier of CS or WE going high to the end of write cycle. 

*.V If ihe CS low transition occurs simultaneously with the WE low transitions or after the WE ti 

•4. DouT is the same phase of write data of this write cycle. 



HITACHI 

280 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM624257 Series 



■ Low V C c Data Retention Characteristics (T a = to +70°C) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Test Conditions 


V cc for Data Retention 


V DR 


2 






V 




Data Retention Current 


•cCDR 




2 


100*' 


/•A 


CS £ V cc - 0.2 V, 
V in ^ V cc - 0.2 V or 
0V<V in < 0.2 V 


Chip Deselect to Data Retention Time 


tCDR 









ns 


Operation Recovery Time 


tR 


5 






ms 



NOTE: 'I . V C C -3.0 V. 

Low V cc Data Retention Timing 




D.U RrlmUcn Mode, 



CS2V«-0.ZV 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 281 



HM624257 Series 




HITACHI 

282 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM66204 Series 



Maintenance Only 



131072-word x 8-bit High Density CMOS Static RAM Module 



The HM66204 is a high density 1 M-bit static RAM module 
consisted of 4 pieces of HM62256FP/LFP products (SOP type 
256k static RAM) and a HD74HC138FP equivalent product (SOP 
type CMOS decoder logic). 

An outline of the HM66204 is the standard 600 mil width 32 
pin dual-in-line package. Its pin arrangement is completely com- 
patible with 1 M-bit monolithic static RAM. 

The HM66204 offers the features of low power and high speed 
by using high speed CMOS devices. And, the HM66204 makes 
high density mounting possible with no surface mount technolo- 
gy. 

These features make the HM66204 ideally suited for high 
density compacted memory systems. 

Features 

• High density 32 pin DIP 

- Mounting 4 pes. of 256k static RAM (SOP; HM62256FP/ 
LFP) and CMOS decoder logic (SOP; HD74HC1 38FP 
equivalent) 

• Pin compatible with 1 M monolithic static RAM 

• High speed 

- Fast access time 120 ns/150 ns (maximum) 

• Equal access and cycle time 

• Completely static RAM 

- No clock or timing strobe required 

• Low power standby and low power operation 
-Standby 40 j/W (typical) (L-version) 

- Operation 50 mW(typical) (f = 1 MHz) 

• Common data input and output, three state outputs 

• Capable of battery backup operation (L-version) 

Ordering Information 



Part No. 



Access Time 



Package 



HM66204-12 
HM66204-15 



120 ns 
150 ns 



HM66204L-12 
HM66204L-15 



120 ns 
150 ns 



- 600-mil 32-pin DIP 



Absolute Maximum Ratings 



Item 


Symbol 


Rating 


Unit 


Voltage on any pin relative to V$s 


V T 


-0.5 to +7.0 


V 


Operating temperature range 


Topr 


to +70 


°C 


Storage temperature range 


Tstg 


-55 to +125 


°C 


Storage temperature range under bias 


Tbias 


-10 to +85 


°c 


Power dissipation 


P T 


1.0 


w 




Pin Arrangement 



NcrT 




3^V„ 


A16 [T 




37JA15 


Ai4 pr 




30] NC 


Au\7 




29] W! 


A7 [7 




28] A13 


A6 [T 




2jJ A8 


AS |T 




»] A9 


A4 [7 




25] All 


A3 |T 




24] OE 


A2fJo 




23] A10 


Al [n 




S] CS 


AO Q| 




H] 1/08 


I/Ol Qi 




20] 1/07 


1/02 [77 




[9] 1/06 


1/03 [7? 




w\ 1/05 


^[lT 




if] 1/04 


(Top View) 



Pin Description 


Pin Name 


Function 


AO - A16 


Address 


I/Ol - I/O8 


Input/Output 


CS 


Chip Select 


OE 


Output Enable 


WE 


Write Enable 


VCC 


Power Supply 


yss 


Ground 


NC 


No Connection 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 83 



HM66204 Series 



Block Diagram 



AO AH (§►— 
A 15® 



1/01 1/08 O- 
WE @- 



i\. HAM N.,.l -N...4 : ]|M6i256Fl' l.KP 
<2 CMOS IWiKfcr HI)74H( 13BH' it 
lis cgu i talent 



Mode Selection 



Mode 


CS WE 


OE 


I/O 




Current Note 


Not selected (Power down) 


H X 




X 


High-Z 




•SB. 'SBl 


Read 


L H 




L 


Dout 




Ice Read cycle (1) - (3) 




L L 




H 


Din 




Ice Write cycle (1) 


Write — 


L L 




L 


Din 




Ice Write c y cle (2) 


Note) X = Don't care (H or L) 










Electrical Characteristics 














Recommended DC Operating Conditions (Ta = to +70°C) 










Parameter 


Symbol 


Min 


Typ 


Max 


Unit Notes 






4.5 


5.0 


5.5 




V 


Supply voltage — 


Vss 













V 


Input high (logic 1) Voltage 




3.85*' 




6.0 




V A15, A16.CS 


v m — 


2.2 




6.0 




V Others except A15,A16,CS 


Input low (logic 0) Voltage 


ViL "0-5 




0.8 




V 


Note) *1. Vjh min is determined by Vcc x 0.7. 












DC Characteristic. (Ta = to +70°C, V cc = 5V ± 10%, V ss = OV) 








Parameter 


Symbol 


Min 


Typ*' 


Max 


Unit 


Test Conditions Notes 


Input leakage current 


Hul 






8 


MA 


Vfn " V SS t° Vqc 






2 


mA 


V in ' V SS to 3.5V 


Output leakage current 


UloI 






8 


mA 


CS = Vjfj or OE = Vjfj 

Vl/o= v S s t° v C c 






2 


HA 


CS = V IH or OE = V IH 
Vl/O'Vss to 3.5V 


Operating power supply current: DC Ice 




10 


25 


mA 


CS=V IL 
h/O = 0mA 


Average operating power supply 


'cci 




37 


80 


mA 


MIN. cycle duty = 100% -12 


current (1) 




35 


80 


ll/O = 0mA _ 15 


Average operating power supply 
current (2) 


•CC2 




10 


15 


mA 


CS = V IL , V, H = V CC 
ViL " 0V, I I/Q = 0mA 
f = 1MHz 


Standby power supply current: DC 


'SB 




2 


12 


mA 


CS = V, H 


Standby power supply current 
(1): DC 


'SBl 




8 


400 


MA 


CS > V C c-0.2V HM66204L 
A15-A16> V C c -0.2V Series 






0.16 


8 


mA 


orOV ^ A15-A16 ^ 0.2V 


Output low voltage 


Vol 






0.4 


V 


Iol ■ 2.1 mA 


Output high voltage 


v OH 


2.4 






V 


•OH = -10 mA 


Note) •!. Typical values are at Vcc 


= 5.0V,Ta = 


+25°C and specified loading. 





HITACHI 

284 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Capacitance (Ta = 25°C, f = 1 MHz) 



Parameter 



Symbol Min Typ Max Unit 



Input capacitance 



Cin 



45 



P F 



Input/output capacitance 



C l/Q 



50 pF 



HM66204 Series 



Test Conditions 







Vin = 0V 



'I/O 



0V 



Note) This parameter is sampled and not 100% tested. 



AC Characteristics (Ta = to +70°C, V cc = 5V ± 10%, unless otherwise noted) 

AC Test Conditions 
• Input pulse levels: 

0.8V to 4.0V. . . C5, A15, A16 

0.8V to 2.4V . . . Other pin except C5", 
A15, A16 



• Input rise and fall times: 5 ns 

• Input and output timing reference level: 1 .5V 

• Output load: 1 TTL Gate and C L (TOOpF) 
(Including scope & jig) 



Re ad Cycl e 



Parameter 


Symbol 


HM66204-12 


HM66204-15 


- Unit 


min 




min 






max 


max 




Read cycle time 


«RC 


120 




150 




ns 


Address access time 


tAA 




120 




150 


ns 


Chip select access time 


'ACS 




120 




150 


ns 


Output enable to output valid 


tOE 




60 




70 


ns 


Output hold from address change 


l OH 


10 




10 




ns 


Chip selection to output in low Z 


*CLZ 


10 




10 




ns 


Output enable to output in low Z 


l OLZ 


5 




5 




ns 


Chip deselection to output in high Z 


l CHZ 





40 





50 


ns 


Output disable to output in high Z 


*OHZ 





40 





50 


ns 



Read Cycle Timing No. 1 *' 



Address 



OE 



IRC 



tAA 



\\\\\\\\\ 



Dout 




tOE 



tOLZ 



-tCLZ- 



-lACS- 



KXX 



.1 



JL 



>//////// 



tOH 



tOHZ- 

-tCHZ- 



Data Valid 



Read Cycle Timing No. 2* 1 * 2 -* 4 



Address 



Dout 





tsc 




) 


c 


) 


( 




(A A 




tOH 




tOH 




/KXXXXXX) 


Data Valid \ 


< 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



285 



HM66204 Series 



Read Cycle Timing No. 3 



C5 



Dout 



xm 



tCH l 



Data Valid 



Notes) *1 . WE is high for read cycle. 

•2. Device is continuously selected, C5 = V[l. 

*3. Address should be valid prior to or coincident with CS transition low. 

•4. m= V IL . 



Write Cycle 



Parameter 




HM66204-12 


HM66204-15 


Unit 


Symbol 


min max 


min 


max 


Write cycle time 


twe 


120 


150 




ns 


Chip selection to end of write 


tew 


100 


120 




ns 


Address valid to end of write 


tAW 


100 


120 




ns 


Address setup time 


tAS 










ns 


Write pulse width 


twp 


90 


110 




ns 


Write recovery time 


tWR 


5 


5 




ns 


Write to output in high Z 


tWHZ 


40 





50 


ns 


Data to write time overlap 


l DW 


50 


60 




ns 


Data hold from write time 


E DH 










ns 


Output disable to output in high Z 


'OHZ 


40 





50 


ns 


Output active from end of write 


tow 


5 


5 


- 


ns 


Write Cycle Timing No. 1 (51 Clock) 













Address 



X 



CS 



WE 



Dout 



Din 



twe 



X 



tew 



-tAS- 



^5 



tOHZ* 3 



tAW 



))))>))))> 



twp* I 



tpw 



tDH 



HITACHI 

286 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Write Cycle Timing No. 2* 5 (01 Low Fixed) 



Address 



C5 



WE 



Dout 



Din 





twc 






( ) 


/ 






tew 


* 2 
twR 




\Y 


s\\\\V 


k ; 




'HLL1LLL 




Iaw 








twp* 1 




tAS 




s / 


I 


to„ 


* 7 




V V V \ 


tWHZ 3 




tow 


* 6 


)?)))))))}))> 




tDH 


e 





Notes) *1 . A write occurs during the overlap (twp) °f a l° w CS and a low WE . 

*2. tyvR is measured from the earlier of C§~ or WE going high to the end of write cycle. 
*3. During this period, I/O pins are in the output state. 

The input signals of opposite phase to the outputs must not be applied. 
*4. If the CS low transition occurs simultaneously with the WE low transition or after the WE 

outputs remain in a high impedance state. 
*5. OE is continuously low. (51 = Vil) 

*6. D out should be held in phase of the written data during this write cycle. 
•7. D ut * s tne reat * data of next address. 

•8. If CS is low during this period, I/O pins are in the output state. The input signals which are opposite to the 
output level should not be applied to I/O pins. 

Low V cc Data Retention Characteristics (Ta = 0°C to +70°C) 
Data retention characteristics is guaranteed only for L version. 



Parameter 


Symbol 


Min Typ 




Unit 


Test Conditions 


Vcc for da' a retention 


V D R 


2.0 




V 


CS > V CC -0.2V 
A15, A16 > V CC -0.2V 
or A15, A16 < 0.2V 


Data retention current 


!CCDR 




200 


pA 


V cc = 3.0V, CS> 2.8V 
A15-A16 > 2.8V or 
OVg A15-A16 ^0.2V 


Chip deselect to data retention time 


l CDR 







ns 




Operation recovery time 


tR 


tRC'l 




ns 


- See retention waveform 



Note) * I . tRc = Read Cycle Time. 
Low Vcc Data Retention Waveform 



Vcc 




Vd*£ 2.0 V 
C5;sl'cc-0.2V 



4.5 V 




ov 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 287 



Package Dimensions; Unit: mm (inch) 



47.50(1.870) 
1 48.26in.x.<1.900ma». I] 





HITACHI 

288 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63921 -20/25/35 



— Product Preview 







2K x 9-Bit CMOS Parallel In-Out FIFO Memory 

■ DESCRIPTION 

The HM63921 is a First-ln, First-Out memory that utilizes a high 
performance static RAM array with internal algorithm that controls, 
monitors and declares status of the memory by empty flag, full flag 
and half-full flag, to prevent data overflow or underflow. 

Expansion logic warrants unlimited expansion capability in width 
and depth. Both read and write are independent from each other and 
their corresponding pointers are designed to select the proper loca- 
tions out of the entire array serially without address information to 
load or unload data. 

Data istoggled in and out of the device through the use of the write 
enable (W) and read enable (R) pins. The device has a read/write 
cycle time of 30/35/45ns. Organization of HM63921 provides a 9-bit 
data bus. the ninth bit could be used for control or parity for error 
checking at the option of the user. The HM63941 is fabricated using 
the Hitachi CMOS 1.3micron technology. The device is available 
in DIP. 

■ FEATURES 

• First-ln, First-Out Dual Port Memory 

• 2k x 9 Organization 

• Low-Power CMOS 1.3micron Technology 

• Asynchronous and Simultaneous Read and Write 

• Fully Expandable in Depth and/or Width 

• Single 5V (±10%) Power Supply 

• Empty and Full Warning Flags 

• Half-Full Flag 

• Access Time 20/25/35ns 

• Package 300-mil 28-pin Plastic DIP Package 

■ ORDERING INFORMATION 



Type Name 


Access Time 


Package 


HM63921P-20 


20ns 


300-mil 28-pin 


HM63921P-25 


25ns 


Plastic DIP 


HM63921P-35 


35ns 


(DP-28NA) 




PIN ARRANGEMENT 











w □ 


1 


28 


□ Vcc 


Ds C 


2 


27 


□ D 4 


D 3 C 


3 


26 


□ Ds 


D 2 □ 


4 


25 


□ D 6 


□1 C 


5 


24 


3 or 


Do C 


6 


23 


□ FL/RT 


XlC 




22 


□ RS 




8 


21 


□ ef 


Qo C 


9 


20 


□ XO/HF 


Qi C 


10 


19 


□ Q7 


Q2 L 


11 


18 


□ 06 


Q3 C 


12 


17 


□ 05 


Q8 C 


13 


16 


□ 04 


vss C 


14 


15 


□ r 




(Top View) 





PIN DESCRIPTION 



Pin Name 


Function 


Do-D g 


Data Inputs 


RS 


Reset 


W 


Write Enable 


R 


Read Enable 


FL 


First Load 


RT 


Retransmit 


xl 


Expansion-In 


XO 


Expansion-Out 


HF 


Half-Full Flag 


FF 


Full Flag 


EF 


Empty Flag 


Qo-Qs 


Data Outputs 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 289 



HM63921 -20/25/35 — 
■ BLOCK DIAGRAM 



1 



DO D1 D2 D3 D4 D5 Q6 07 D8 

?nmm 



w 



Read 
Control 



R O- 



Read 
Control 



Data Input Buffer 



Write 
Pointer 



Column Decoder 



Row 
Decoder 



Memory Array 
2048 X9 



Row 
Decoder 



Column Decoder * 



Read 
Pointer 



Flag 
Logic 



-O EF 
-O FF 




Reset 
Logic 



Q0Q1 Q2 Q3 Q4 Q5 Q6 Q7 D8 



Expansion 
Logic 



FT 



RS FL/RT 



XI XO/HF 



HITACHI 

290 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



ABSOLUTE MAXIMUM RATINGS 



HM63921 -20/25/35 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage<" 


v T 


-O.SWto +7.0 


V 


Power Dissipation 


P T 


l.O 


W 


Operating Temperature 


T 


to +70 


°c 


Storage Temperature 


T S! S 


-55 to + 125 


°c 


Storage Temperature Under Bias 


Tbias 


-10 to +85 


°c 



NOTES: 1 . Relative to V S s- 

2. -3.5V for pulse width < 10ns. 

• Recommended DC Operating Conditions (T, = to +70°C) 



Parameter 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


V SS 











V 


Input Voltage 


V 1H 


2.2 




6.0 


V 


V, L 


-0.5(1) 




0.8 


V 



NOTE: 1. -3.0V for pulse width < 10ns. 

■ DC CHARACTERISTICS (T a = 0°C to +70°C, V cc = 5V ± 10%) 



Parameter 


Symbol 


Test Conditions 




Typ. 


Max. 


Unit 


Input Leakage Current 


Uul 


V cc = 5.5V, V in = 0V - V cc 






2 




Output Leakage Current 


HloI 


R = v IH , v ou[ = 0V - V cc 






2 










-20 




120 


mA 


Operating Power Supply Current 


Icci 


Average Operating Current 


-25 




110 


mA 








-35 




100 


mA 


Standby Power Supply Current 


i SBl 


R = W = RS = FL/RT = V IH 






10 


mA 


!sB2 


All inputs a V cc - 0.2V or < V cc 






1 


mA 


Output High Voltage 


V OH 


I OH = -4mA 


2.4 






V 


E ^ 


Vol 


Iol = 8mA 






0.4 


V 



\ = 25°C, f = 1MHz) 



Parameter 


Symbol 


Test Conditions 


Typ. 


Max. 


Unit 


Input Capacitance 




V, n = 0V 




6 


pF 


Output Capacitance 


C ut 


v ou , = ov 




10 


pF 



NOTE: 



1. This parameter is sampled and not 100% tested. 



■ AC CHARACTERISTICS (T a = 0°C to 70°C, V cc = 5 ± 10%) 
• Test Conditions 

• Input Pulse Levels: V ss to 3.0V 

• Input and Output Timing Reference Level: 1.5V 



• Input Rise and Fall Times: 5ns 

• Output Load: See Figure 




♦Including scope and jig. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



291 



HM63921 -20/25/35 

• Read Cycle 



Parameter 


Symbol 


HM63921-20 


HM63921-25 


HM63921-35 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


l RC 


30 


— 


35 


— 


45 


— 


ns 


Access Time 


t A 


— 


20 


— 


25 


— 


35 


ns 


Read Recovery Time 


l RR 


10 


— ^ 


10 




10 




ns 


Read Pulse Width 


l RPW 


20 




25 




35 




ns 


Read Low to DB Low Z 


tRLZ (l) 


5 




5 




5 




ns 


Read High to DB High Z 


tRHZ (1) 




15 




15 




20 




ns 


Data Valid from Read High 


k)H 


3 




3 




3 




ns 


Read Pulse Width After Empty Flag High 


l RPE 


20 




25 




35 




ns 


Write High to DB Low Z 

(Read Data Flow Through Mode) 


t W LZ (l> 


3 




3 




3 




ns 


NOTE: 1 . tRLZ, tRHZ and twLZ are sampled and not 100% tested. 

• Write Cycle 


Parameter 


Symbol 


HM63921-20 


HM63921-25 


HM63921-35 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


'wc 


30 




35 




45 




ns 


Write Recovery Time 


l WR 


10 




10 




10 




ns 


Write Pulse Width 


'wpw 


20 




25 




35 




ns 


Data Setup Time 


l DS 


10 




15 




20 




ns 


Data Hold Time 


l DH 












5 




ns 


Effective Write Pulse Width After 
Full Flag High 


l WPF 


20 




25 




35 




ns 


• Reset Cycle 


Parameter 


Symbol 


HM63921-20 


HM63921-25 


HM63921-35 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Reset Cycle Time 


<RSC 


30 




35 




45 




ns 


Reset Pulse Width 


[ RS 


20 




25 




35 




ns 


Reset Setup Time 


•rss 

















ns 


Reset Recovery Time 


l RSR 


10 




10 




10 




ns 


• Retransmit Cycle 


Parameter 


Symbol 


HM63921-20 


HM63921-25 


HM63921-35 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Retransmit Cycle Time 


'rtc 


30 




35 




45 




ns 


Retransmit Pulse Width 


•rt 


20 




20 




35 




ns 


Retransmit Setup Time 


'rts 

















ns 


Retransmit Recovery Time 


l RTR 


10 




10 




10 




ns 



HITACHI 

292 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63921 -20/25/35 



• Flag Timing 



Parameter 


Symbol 


HM63921-20 


HM63921-25 


HM63921-35 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Reset to Empty Flag Low 


tgpL 


_ 


20 





25 





35 


ns 


Reset to Full Flag High 


tpFH 





20 





25 





35 


ns 


Reset to Half-Full Flag High 


*hfh 





30 





35 





45 


ns 


Read Low to Empty Flag Low 


*REF 


- 


20 


- 


25 


- 


35 


ns 


Read High to Full Flag High 


l RFF 




20 




25 




35 


ns 


Write High to Empty Flag High 


^WEF 




20 




25 




35 


ns 


Write Low to Full Flag Low 


<WFF 




20 




25 




35 


ns 


Write Low to Half-Full Flag Low 


l WHF 




30 




35 




45 


ns 


D aQ/ | Uinh tr* U'llf dill ETIocr Uirrh 

Keau nign to nan-run rlag riign 


•rhf 




30 




35 




45 


ns 


• Expansion Timing 
















Parameter 


Symbol 


HM63921-20 


HM63921-25 


HM63921-35 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Expansion in Setup to Write or Read 


l EFL 




15 




20 




30 


ns 


Expansion in Recovery Time 


l RFF 




15 




20 




30 


ns 


Expansion in Pulse Width 


( WHF 


10 




10 




10 




ns 


Expansion Out High Delay From Clock 


( REF 


10 




10 




10 




ns 


Expansion Out Low Delay From Clock 


l RFF 


10 




10 




15 




ns 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 2 93 



HM63921 -20/25/35 



SIGNAL DESCRIPTIONS 
Inputs 

• Reset (RS) 

The device is reset whenever RS input is taken to 
low state, for minimum reset pulse width. When 
device is reset, both read and write pointers are 
set to the first location. A reset cycle is required 
after power on. Both read enable (R) and write 
enable (W) inputs must be in the high state during 
reset. Empty flag (EF) will go low and full flag (FF) 
and half-full (HF) will go high during reset cycle. 

• Write enable (W) - 
Write cycle is initiated at the falling edge of W, if 
the full flag (FF) is not set, provided that data set- 
up and hold time requirements relative to the ris- 
ing edge of (W) are met. Data is stored in the de- 
vice sequentially and independently of any simul- 
taneous read operation. To inhibit further write op- 
erations and prevent internal data overflow full 
flag (FF) will go low. 

• Read enable (R) 

Read cycle is initiated at the falling edge of R, if 
the empty flag (EF) is not set. Data is accessed on 
a first-in, first-out basis independently of simulta- 
neous write operation. As read enable (R) goes 
high, all outputs will return to high impedance 
state, till next read operation. After the last data 
has been read from the FIFO, the empty flag (EF) 
will go low, preventing further read operations with 
output kept in high impedance state. Empty flag 
(EF) will go high during a valid write cycle (t WEF ), 
thereafter a valid read can start. 

• First load/retransmit (FL/RT) 

For depth expansion mode, this pin is grounded to 
indicate that it is the first device, while this pin of 
the rest of devices should connect to V cc for cor- 
rect operation. In single device mode, this pin re- 
sets the read pointer to the beginning of the FIFO 
memory, therefore data can be reread from the 
beginning. Both R and W should be kept high 
while RT is taken low. 

• Expansion-in (XI) 

For single device mode expansion-in (XI) is 
grounded. For_ depth expansion mode, 
expansion-in (X\) should be connected to 
expansion-out (XO) of previous device. 

• Data In (D to D 8 ) 

Data inputs for 9-bit wide data. 

Outputs 

• Full Flag (FF) _ 

The full flag (FF) will go low when FIFO is full, 
inhibiting further write operations until one or 
more read operations are completed or the FIFO 
is reset. 

• Empty flag (EF) 

The empty flag (EF) will go low when the FIFO 
becomes empty, inhibiting further read opera- 



tions, until one or more write operations are com- 
pleted, or FIFO is set to retransmit. 

• Expansion-out (XO)/Half-full flag (HF) 

This output has dual functionality depending how 
it is used. In depth expansion configuration 
expansion-ou_t_ (XO) is connected to next 
expansion-in (XI). The expansion-out (XO) oj_the 
last FIFO is connected to the expansion-in (XI) of 
the first FIFO. In this way the first FIFO indicates 
the next FIFO that it will receive the next data. In 
like manner, any FIFO which becomes full will indi- 
cate the next FIFO that it will receive the next data. 
The second function of this output is in stand 
alone and/or parallel expansion configurations to 
indicate the system user that the FIFO is almost 
full. 

• Data outputs (Q to Q 8 ) 

Data outputs for 9-bit wide data. These outputs 
are in high impedance state when R is in high 
state. 

VARIOUS OPERATIONS MODE 

• Single device mode 

If only one FIFO is used, the expansion-in (XI) pin 
should be grounded. 

• Width expansion mode 

Width expansion by 9-bit increments may be 
achieved when separately paralleling the data in- 
puts and the data outputs. In this configuration 
any flags of any device may be used. To avoid 
output contention of the flags for short periods of 
time, the flag outputs should not be wired to- 
gether. 

• Depth expansion mode 

Multiple of FIFOs could provide multiple of 2k x 9 
as (N) x (2k) by 9-bits wide, where N is the num- 
ber of FIFOs connected in depth expansion 
mode. 

The following arrangement must be provided. 

1 . First load (FL) of the first FIFO should be con- 
nected to ground. 

2. All other (FL) should be connected to V C c- 

3. Connect the expansion-out (XO) of each FIFO 
to expansion-in (XI) of the_next FIFO serially 
and XO of the last FIFO to XI of the first FIFO. 

4. Connect all the empty flag (EF) together to OR 
gate and connect all the full flag (FF) together to 
OR gate to obtain two separate valid empty flag 
(EF) and full flag (FF) outputs. 

5. (RT) and (AF) will not be available in this mode. 

• Compound expansion mode 

Combination of width and depth expansion 
modes will provide larger FIFO arrays. 



HITACHI 

294 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63921 -20/25/35 



I TIMING WAVEFORM 
Read Cycle 



R 



Q0-Q8 



tRC 



tA 



tRLZ 



-tRH 



tRPW 



tA 



tOH 



<f^) ( Data out valid ^ Q(^ ( Data out valid X X) 



tRHZ 



• Write Cycle 



Jwc 



JwPW_ 



W 



D0-D8 



tWR 



tWPW 



.<DH. 



^Data in valid^ 



tps 



R 



Data in valid 



>- 



• Reset Cycle 



tRSC 




XO/HF 



NOTES: 1. W = R = V, H during reset. 

2. tRSC = tRST, tRSR. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 295 



HM63921 -20/25/35 - 
• Retransmit Cycle 



FL/RT 



tRTS 



R, W 



tRTC 



tRT 



\_ 



tRTR 



N X 



• Full-Flag Cycle (From Last Write to First Read) 



W 



FF 




• Empty-Flag Cycle (From Last Read to First Write) 



W 



EF 



Q0-Q8 



Last Read 



First Read 




HITACHI 

296 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63921 -20/25/35 



Half-Full Flag Cycle 



Write=Read+1023 



W 



D0-D8 



Write=Read+1024 



;WHF_ 




Write=Read+1023 



l RHF. 



• Read Data Flow Through Mode 

D0-D8 

w 



^ ^ Data in valid y ^ 



tps 



Last read 



EF 



tRC 



twpw 



First write 



Irpw 



tREF 



tA 



qo-q8 <XX!irAE> 



tRR 



tDK 



*WEF 



tWLZ 



tOH 



tRPE 



Last read 



tREF 



tA 



tOH 



/V s -/ Data out \/V\__ 

KAA \ valid x KA/ 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 297 



HM63921 -20/25/35 

• Write Data Flow Through Mode 



W 



FF 



D0-D8 



Q0-Q8 



twc 



tyypw 



twFF_ 



Ids 



tWR 



Jdh 



4C 



Data in valid 



> 



First read 



tRFF 



tA 



twPF 
Last read 



tWFF 



7\ 



tos. 



.tDH. 







tOH 



yData in vaiid^ 



/V\/ Data out \A/ \ 
\J\yK valid A\AS 



• Expansion Out Cycle 1 



W 



Write to last 
physical address 

> /f 



tX0L 



Read from last 
physical address 



XO 



J Si 



Jf 



txOL 



. l XOH . 



HITACHI 

298 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Expansion Out Cycle 2 (Read Data Flow Through Mode) 

Write to last physical address 



HM63921 -20/25/35 



w 

R 
EF 

XO 



7 



Read from last 
physical address 




txoH 



• Expansion Out Cycle 3 (Write Data Flow Through Mode) 
R 



Read from last physical address 



w 



FF 



XO 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 299 



HM63921 -20/25/35 — 
• Expansion In Cycle 



txi 



XI 



w 



S 



txoL Write to first 

physical address 



ss- 



txis Read from first 
physical address 




HITACHI 

300 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63941 -25/35/45 — Preliminary 

4K x 9-Bit CMOS Parallel In-Out FIFO Memory 
■ DESCRIPTION 

The HM63941 is a First-ln, First-Out memory that utilizes a high 
performance static RAM array with internal algorithm that controls, 
monitors and declares status of the memory by empty flag, full flag 
and almost-full flag, to prevent data overflow or underflow. 

Expansion logic warrants unlimited expansion capability in width 
and depth. Both read and write are independent from each other and 
their corresponding pointers are designed to select the proper loca- 
tions out of the entire array serially without address information to 
load or unload data. 

Data istoggled in and out of the device through the use of the write 
enable (W) and read enable (R) pins. The device has a read/write 
cycle time of 35/45/60ns. Organization of HM63941 provides a 9-bit 
data bus. the ninth bit could be used for control or parity for error 
checking at the option of the user. The HM63941 is fabricated using 
the Hitachi CMOS 1.3micron technology. The device is available 
in DIP. 




PIN ARRANGEMENT 



' First-ln, First-Out Dual Port Memory 

1 4k x 9 Organization 

1 Low-Power CMOS 1.3micron Technology 

1 Asynchronous and Simultaneous Read and Write 

1 Fully Expandable in Depth and/or Width 

' Single 5V ( ± 10%) Power Supply 

1 Empty and Full Warning Flags 

1 Almost-Full Flag 

' Access Time 25/35/45ns 

' Package 28-pin DIP Package 

■ ORDERING INFORMATION 



Type Name 


Access Time 


Package 


HM63941P-25 
HM63941P-35 
HM6394IP-45 


25ns 
35ns 
45ns 


28-pin Plastic DIP 







X1 



Q2 □ 
03 □ 
08 C 
VSS C 





28 


2 


27 


3 


26 


4 


25 


5 


24 


6 


23 




22 


8 


21 


9 


20 


10 


19 


11 


18 


12 


17 


13 


16 


14 


15 



Vcc 
D 4 
D 6 
D 6 

D7_ 
FL/RT 
RS 
EF 

XO/AF 
Q7 
Q6 
Qs 

C)4 

R 



(Top View) 



PIN DESCRIPTION 



Pin Name 


Function 


D -D 8 


Data inputs 


RS 


Reset 


W 


Write enable 


R 


Read enable 


FL 


First load 


RT 


Retransmit 


xl 


Expansion-in 


XO 


Expansion-out 


AF 


Almost-full flag 


FF 


Full flag 


EF 


Empty flag 


Qo-Qs 


Data outputs 



rica, Ltd. • I 



HM63941 -25/35/45 



ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage! ') 


V T 


-0.5< 2 ) to +7.0 


V 


Power Dissipation 


P T 


1.0 


W 


Operating Temperature 


T 


to +70 


°c 


Storage Temperature 


Tstfi 


-55 to + 125 


°c 


Storage Temperature Under Bias 




-10 to +85 


°c 



NOTES: 1. Relative to V ss . 

2. -3.5V for pulse width < 10ns. 

■ ELECTRICAL CHARACTERISTICS 

• Recommended DC Operating Conditions (T a = Oto +70°C) 



Parameter 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 











V 


Input Voltage 


V,H 


2.0 




6.0 


V 


V,L 


-0.5O 




0.8 


V 


NOTE: 1 . -3.0V for pulse width < 10ns. 

■ DC CHARACTERISTICS (T a = 0°C to +70°C, V cc = 5V ± 10%) 



Parameter 


Symbol 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 




Input Leakage Current 


UliI 


V cc = 5.5V, V in = 0V - V CC 






2 




Output Leakage Current 


HloI 


R = v IH , v out = ov - v cc 






2 


pA 


Operating Power Supply Current 


Icci 


Average Operating Current 






80 


mA 


1CC2 


R = W = RS = FL/RT = V IH 






10 


mA 


Standby Power Supply Current 


!sb 


All Inputs > V cc - 0.2V or < V cc 






1 


mA 


Output High Voltage 


V OH 


I OH = -4mA 


2.4 






V 


Output Low Voltage 


Vol 


I OL = 8mA 






0.4 


V 



CAPACITANCE (T a = 25°C, f = 1MHz) 



Parameter 


Symbol 


Test Conditions 


Typ. 


Max. 


Unit 


Input Capacitance 




V in = 0V 




TBD 


pF 


Output Capacitance 


(- OUI 


v ou , = ov 




TBD 


pF 



I AC CHARACTERISTICS (T a = 0°C to 70°C, V cc = 5 ± 10%) 
Test Conditions 



Input Pulse Levels: V ss to 3.0V 

Input and Output Timing Reference Level: 1.5V 



• Input Rise and Fall Times: 5ns 

• Output Load: See Figure 




•Including scope and jig. 



302 



HITACHI 



,CA 94005-1819' 



HM63941 -25/35/45 

• Read Cycle 



Parameter 


Symbol 


HM63941-25 


HM63941-35 


HM63941-45 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


D an A r*,~\<> T; mo 
Read Cycle Time 


'rc 


35 




45 




60 




ns 


Access Time 


'a 




*>< 




jj 






ns 


Read Recovery Time 


l RR 


10 




10 




15 






Read Pulse Width 


'rpw 


25 




35 




45 




ns 


Read Low to DB Low Z 


'rlz 


5 




5 




10 




ns 


Read High to DB High Z 


l RHZ 




15 




20 




25 


ns 


Data Valid from Read High 


l OH 


5 




5 




5 




ns 


• Write Cycle 


Parameter 


Symbol 


HM63941-25 


HM63941-35 


HM63941-45 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


l wc 


35 




45 




60 




ns 


Write Recovery Time 


•wr 


10 




10 




15 




ns 


Write Pulse Width 


l WPW 


20 




35 




45 




ns 


Data Setup Time 


l DS 


15 




20 




25 




ns 


Data Hold Time 


( DH 












5 




ns 


• Reset Cycle 


Parameter 


Symbol 


HM63941-25 


HM63941-35 


HM63941-45 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Reset Cycle Time 


l RSC 


35 




45 




60 




ns 


Reset Pulse Width 


l RS 


25 




35 




45 




ns 


Reset Recovery Time 


( RSR 


10 




10 




15 




ns 


• Retransmit Cycle 




Parameter 




Symbol 


HM63941-25 


HM63941-35 


HM63941-45 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Retransmit Cycle Time 


tRTC 


35 




45 




60 




ns 


Retransmit Pulse Width 


•rt 


20 




35 




45 




ns 


Retransmit Recovery Time 


<RTR 


10 




10 




15 




ns 


• Flag Timing 


Parameter 


Symbol 


HM63941-25 


HM63941-35 


HM63941-45 


Unit 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Reset to Empty Flag Low 


( EFL 




30 




45 




60 


ns 


Read Low to Empty Flag Low 


l REF 




25 




35 




45 


ns 


Read High to Full Flag High 


'rff 




25 




35 




45 


ns 


Write High to Empty Flag High 


'WEF 




25 




35 




45 


ns 


Write Low to Full Flag Low 


*WFF 




25 




35 




45 


ns 


Write Low to Almost-Full Low 


l WAF 




30 




40 




55 


ns 


Read High to Almost-Full High 


<RAF 




30 




40 




55 


ns 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 303 



HM63941 -25/35/45 

SIGNAL DESCRIPTIONS 
Inputs 

• Reset (RS) 

The device is reset whenever RS input is taken to 
low state, for minimum reset pulse width. When 
device is reset, both read and write pointers are 
set to the first location. A reset cycle is required 
after power on. Both read enable (R) and write 
enable (W) inputs must be in the high state during 
reset. Empty flag (EF) will go low and full flag (FF) 
and almost-full (AF) will go high during reset cycle. 

• Write enable (W) _ 
Write cycle isjnitiated at the falling edge of W, if 
the full flag (FF) is not set, provided that data set- 
up and hold time requirements relative to the ris- 
ing edge of (W) are met. Data is stored in the de- 
vice sequentially and independently of any simul- 
taneous read operation. To inhibit further write op- 
erations and prevent internal data overflow full 
flag (FF) will go low. 

• Read enable (R) _ 
Read cycle is initiated at the falling edge of R, if 
the empty flag (EF) is not set. Data is accessed on 
a first-in, first-out basis independently of simulta- 
neous write operation. As read enable (R) goes 
high, all outputs will return to high impedance 
state, till next read operation. After the last data 
has been read from the FIFO, the empty flag (EF) 
will go low, preventing further read operations with 
output kept in high impedance state. Empty flag 
(EF) will go high during a valid write cycle (t W EF>> 
thereafter a valid read can start. 

• First load/retransmit (FL/RT) 

For depth expansion mode, this pin is grounded to 
indicate that it is the first device, while this pin of 
the rest of devices should connect to V cc for cor- 
rect operation. In single device mode, this pin re- 
sets the read pointer to the beginning of the FIFO 
memory, therefore data can be reread from the 
beginning. Both R and W should be kept high 
while RT is taken low. 

• Expansion-in (XI) 

For single device mode expansion-in (XI) is 
grounded. For_ depth expansion mode, 
expansion-in {X]) should be connected to 
expansion-out (XO) of previous device. 

• Data In (D to D 8 ) 

Data inputs for 9-bit wide data. 

Outputs 

• Full Flag (FF) _ 

The full flag (FF) will go low when FIFO is full, 
inhibiting further write operations until one or 
more read operations are completed or the FIFO 
is reset. 

• Empty flag (EF) 

The empty flag (EF) will go low when the FIFO 
becomes empty, inhibiting further read opera- 



tions, until one or more write operations are com- 
pleted, or FIFO is set to retransmit. 
Expansion-out (XO)/Almost-full flag (AF) 
This output has dual functionality depending how 
it is used. In depth expansion configuration 
expansion-out_ (XO) is connected to next 
expansion-in (XI). The expansion-out (XO) ofjhe 
last FIFO is connected to the expansion-in (XI) of 
the first FIFO. In this way the first FIFO indicates 
the next FIFO that it will receive the next data. In 
like manner, any FIFO which becomes full will indi- 
cate the next FIFO that it will receive the next data. 
The second function of this output is in stand 
alone and/or parallel expansion configurations to 



indicate the system user that the 
full. 

• Data outputs (Q to Q 8 ) 
Data outputs for 9-bit wide data, 
are in high impedance state when 
state. 

VARIOUS OPERATIONS MODE 

• Single device mode 
If only one FIFO is used, the expansion-in ( 
should be grounded. 

• Width expansion mode 
Width expansion by 9-bit increments may be 
achieved when separately paralleling the data in- 
puts and the data outputs. In this configuration 
any flags of any device may be used. To avoid 
output contention of the flags for short periods of 
time, the flag outputs should not be wired to- 
gether. 

• Depth expansion mode 

Multiple of FIFOs could provide multiple of 4k x 9 
as (N) x (4k) by 9-bits wide, where N is the num- 
ber of FIFOs connected in depth expansion 
mode. 

The following arrangement must be provided. 

1 . First load (FL) of the first FIFO should be con- 
nected to ground. 

2. All other (FL) should be connected to V cc . 

3. Connect the expansion-out (XO) of each FIFO 
to expansion-in (XI) of the_next FIFO serially 
and XO of the last FIFO to XI of the first FIFO. 

4. Connect all the empty flag (EF) together to OR 
gate and connect all the full flag (FF) together to 
OR gate to obtain two separate valid empty flag 
(EF) and full flag (FF) outputs. 

5. (RT) and (AF) will not be available in this mode. 

• Compound expansion mode 

Combination of width and depth expansion 
modes will provide larger FIFO arrays. 



<j§> HITACHI 

304 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63941-25/35/45 



■ TIMING WAVEFORM 
• Read Cycle 



R 



Q0-Q8 



• Write Cycle 



W 



• Reset Cycle 
RS 



EF 



tRC 



lA 



tRLZ 



Irr 



tRPW 



tA 



tOH 



<X/ K Data out valid Data out valid X X/> 



tRHZ 



twc 



twpw 



tDS _ tDH 



tWR 



^Data in valid^ 



- ^Data in vaiid^ - 



, tRS » 



tEFL 



tRSR 



NOTES: 1. W = R = Vih during reset. 

2. tRSC = tRST, tRSR. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 305 



HM63941 -25/35/45 - 
• Retransmit Cycle 



FL/RT 



I - tR 



R, W 



tRTR 



• Full-Flag Cycle (From Last Write to First Read) 



Last write 



First Read 



R 
W 

FF 



Additional reads 




• Full-Flag Cycle (Effective Write Pulse Width After FF High) 



tRFF 



FF 



W 



V 



twPW 



HITACHI 

306 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63941 -25/35/45 



• Empty-Flag Cycle (From Last Write to First Read) 



Last Read 



W 
R 

EF 




Data Out Q?X XX>l 



• Empty-Flag Cycle (Effective Read Pulse Width After EF High) 



W 

EF 
R" 



Almost-Full Flag Cycle 

Write=Read+4079 



W 



R 



AF 



^ /" 



Write=Read+4080 



Jwaf 



X 



Write=Read+4079 



tRAF 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 307 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Section 2 
Cache Static RAM 
and 

Fast SRAM Modules 



HITACHI 



■ 



<§> HITACHI 

31 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM62A168/HM62A188 Series — Preliminary 

Direct Mapped 8,192-Word x 16/18-Bit ■ PIN-OUT 

2-Way 4,096-Word x 16/18-Bit Static Cache RAM 

■ DESCRIPTION 

The Hitachi HM62A168/HM62A188 is a high speed 128/144-kbit 
static cache RAM organized as 2-way set associative 4k x 16/18 or 
direct mapped 8k x 16/18. By using two HM62A168/HM62A188 with 
Intel's 82385 cache controller a high performance 80386 system can 
be achieved. 

The HM62A168/HM62A188, packaged in a 52-pin PLCC is availa- 
ble for high density mounting. 

■ FEATURES 

• Meets INTEL 82385 cache memory controller 

• High Speed 

Access Time 25/35/45ns (max.) 

• Address Latch 

• Pin Programmable for 8k x 16/18 or 2-Way 4k x 16/18 

■ ORDERING INFORMATION 








(CP-52) 



PIN DESCRIPTION 



Type No. 


Access 


Package 


HM62168CP-25 


25ns 




HM62168CP-35 


35ns 


52-pin PLCC 


HM62168CP-45 


45ns 


HM62188CP-25 


25ns 




HM62188CP-35 


35ns 


52-pin PLCC 


HM62188CP-15 


45 ns 





■ BLOCK DIAGRAM 

Topology Two-Way Set Associative (MODE = Logic Low) 

Way A 



COEA - 
CWEA- 

A0 " 

) : 

A11- 
CALEN - 

COEB - 
CWEB - 
CE - 



WayB 



4k x 8/9 

D8- 
D15/DP1 



Pin Name 


Function 


CALEN 


Cache Address 
Latch Enable 


MODE 


Mode Select 


A toA 12 


Address 


CSq, CSj 


Cache Chip Select 


COEA, COEB 


Cache Output Enable 


CWEA, CWEB 


Cache Write Enable 


D toD„ 


Data Input/Output 


CE 


Cache Chip Enable 


NC/DP , DP, 


No connection 
Parity Input/Output 



■ PIN ARRANGEMENT 



D15/DP1 
4k x 8/9 



D0toD15/and DPO. DPI 



Topology Direct Map (MODE = Logic Low) 



COEA 
COEB 
CWEA 



CWEB 1 

12 

V> 

i 



CWEB 
A12 
AO 



A1 A2 A3 A4 AS AS Vec^A? A8 A9 AI0A11 



04 
OS 
06 
07 
NC/DPO 



UUUUUUUUUUUUl 
2 1 52 51 SO 49 48 . 



21 22 1 

n n r 



2< 



26 27 28 29 30 31 32 33 

nr-innnnnn 



«: 
«c 
«c 

43C 
42C 

«c 

39C 
38C 
37C 
36 C 

*Z 

ML 



AVsjVaCOEA CS1 VccVcc 
I COlS MOOE 

(Top View) 



DO to D157and DPO, DP1 



A11 - 

CALEN - 
CE - 

CS0 - 
CS1 - 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 31 1 



HM62A168/HM62A188 Series 



■ FUNCTION TABLE 

• Two-Way Mode (Mode = High) 2-4K x 16/18 



Input Signal 


I/O Pin 


Function 


rc 




) 


POP A 


LUCD 


W Cr\ 


CWEB 


u u 7' l-'' 




o 

n 


Y 


Y 
A 


Y 
A 


Y 
A 


Y 
A 




High-Z 


High-Z 


Disabled 


A 


o 
n 


ri 


Y 
A 


Y 
A 


Y 
A 


Y 
A 




Hioh 7 


Disabled 


I 

L. 


i 

L. 


u 
n 


1 

L* 


TJ 

n 




JJ 




High-Z 


Read Way A 


I 

L, 


I 

Lt 


n 


I] 

n 


I 


H 


LJ 




High-Z 


Read Way B 


T 

Li 


U 

n 


I 


I 


tj 
n 


n 


J-J 






Read Way A 


I 

JL< 


u 

n 


1 


O 

n 


T 


u 
n 




High-Z 




Read Way B 


I 

L> 


T 

L> 


I 

L. 


i 

L- 


TJ 

n 


n 




wuipui 


Oiitnnt 


Read Way A 


T 

Li 


T 

La 


I 

Li 


n 


i 

L< 


n 


n 


WULpUL 




Read Way B 


I 

Ll 


Li 


U 

n 


Y 


Y 


L 


j| 


Input 


High-Z 


Write Way A 


L 


L 




X 


x 




L 




High-Z 


Write Way B 


L 


H 


L 


X 


X 


L 


H 


High-Z 


Input 


Write Way A 


L 


H 


L 


X 


X 


H 


L 


High-Z 


Input 


Write Way B 


L 


L 


L 


X 


X 


L 


H 


Input 


Input 


Write Way A 


L 


L 


L 


X 


X 


H 


L 


Input 


Input 


Write Way B 


L 


L 


H 


X 


X 


L 


L 


Input 


High-Z 


Write Way A & B 


L 


H 


L 


X 


X 


L 


L 


High-Z 


Input 


Write Way A & B 


L 


L 


L 


X 


X 


L 


L 


Input 


Input 


Write Way A & B 



• Direct Mode (Mode = Low) 8K x 16/18 



Input Signal 


I/O Pin 


Function 


CE 


CS 


cs. 


COEA 


COEB 


CWEA 


CWEB 


D -D 7 /DP 


D 8 -D l5 /DP| 


H 


X 


X 


X 


X 


X 


X 


High-Z 


High-Z 


Disabled 


X 


H 


H 


X 


X 


X 


X 


High-Z 


High-Z 


Disabled 


X 


X 


X 


H 


H 


X 


X 


High-Z 


High-Z 


Disabled 


L 


L 


H 


L 


L 


H 


H 


Output 


High-Z 


Read D to D 7 


L 


H 


L 


L 


L 


H 


H 


High-Z 


Output 


Read D 8 to D ]5 


L 


L 


L 


L 


L 


H 


H 


Output 


Output 


Read D to D )5 


L 


L 


H 


X 


X 


L 


L 


Input 


High-Z 


Write D to D 7 


L 


H 


L 


X 


X 


L 


L 


High-Z 


Input 


Write D 8 to D !5 


L 


L 


L 


X 


X 


L 


L 


Input 


Input 


Write D to D, 5 



■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Value 


Unit 


Voltage on Any Pin Relative to V ss 


v fa 


-0.5' i > to +7.0 


V 


Power Dissipation 


P T 


1.2 


W 


Operating Temperature Range 


T 


to +70 


°C 


Storage Temperature Range 


T stS 


-55 to + 125 


°c 


Storage Temperature Range Under Bias 


Tbias 


-10 to +85 


°c 



NOTE: 1 . V in min. = -2.5V for pulse width - 10ns. 



HITACHI 

312 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM62A168/HM62A188 Series 



RECOMMENDED DC OPERATING CONDITIONS (T a = to 70°C) 



Parameter 




Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


V SS 











V 


Input High (Logic l) Voltage 


V, H 


2.2 




V cc + 0.3 


V 


Input Low (Logic 0) Voltage 


V,L 


-0.3(i) 




0.8 


V 



NOTE: I. Vil min. = -2.0V for pulse width < 10ns. 

■ DC CHARACTERISTICS (T a = to 70°C, V cc = 5V ± 10%, V ss = 0V) 



Parameter 


Symbol 


Test Condition 


Min. 


Typ.d) 


Max. 


Unit 


Input Leakage Current 


Ili 


V cc = Max., V in = V ss to V cc 






2.0 


M A 


Output Leakage Current 


Ilo 


CS = V,h 

V„o = V ss to V cc 






10.0 




Operating Power Supply Current 


"cc 


V in = 0V/V cc , I 1/0 = 0mA 
Min. Cycle, Duty = 100% 






220 


mA 


Output Low Voltage 


Vol 


Iol = 4mA 






0.4 


V 


Output High Voltage 


Voh 


'oh = -1.0mA 


2.4 






V 



NOTE: t. Typical limits are at Vcc = 5.0V, T a = +25°C and specified loading. 
■ CAPACITANCE (T a = 25°C, f = lMHz)<'> 



Parameter 


Symbol 


Max. 


Max. 


Unit 


Test Conditions 


Input Capacitance 


C in 




6 


pF 


V in = 0V 


Input/Output Capacitance 


C|/o 




10 


pF 


v, /0 = ov 



NOTE: This parameter is sampled and not 100% te 

■ AC CHARACTERISTICS (T a = to 70°C, V cc 
• Test Conditions 



±10%, unless otherwise noted.) 



• Input Pulse Levels: V ss to 3.0V 

• Input and Output Timing Reference Levels: 1.5V 



• Input Rise and Fall Times: 3ns 

• Output Load: See Figures 



Vcc 



Dout 



6670 



Vcc 



10000 
100 pF 



Dout 



/77 

Output Load A 



6670 




Output Load B 



♦Including scope and jig. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 1 3 



HM62A168/HM62A188 Series 
• Read Cycle 







HM62168-25 


HM62168-35 


HM62168-45 




Parameter 


Symbol 


HM62188-25 


HM62188-35 


HM62188-*5 


Unit 






Min. 


Max. 


Min. 


Max. 


Min. 


Max. 




Read Cycle Time 


tRC 


25 


— 


35 


— 


45 


— 


ns 


Address Access Time 


t-AA 





25 





35 





45 


ns 


A 12 Address Access Time 


^A12 


— 


17 





25 





30 


ns 


Chip Select Access Time 


tcs> tcE 





20 





25 


— 


30 


ns 


Output Enable to Output Valid 


tOE 





10 


— 


13 


— 


16 


ns 


Output Hold from Address Change 


toH 


3 


_ 


3 


— 


3 


— 


ns 


Chip Select to Output Low-Z 


t LZ 


3 




3 




3 




ns 


Output Enable to Output Low-Z 


tOLZ 


2 




2 




2 




ns 


Chip Deselect to Output in High-Z 


l HZ 




15 




25 




30 


ns 


Output Disable to Output High-Z 


tOHZ 




10 




14 




14 


ns 


Address Latch Enable Pulse Width 


l CALEN 


8 




10 




15 




ns 


Address Setup to Latch Low 


( ASL 


4 




6 




10 




ns 


Address Hold to Latch Low 


'ahl 


5 




5 




5 




ns 



• Read Timing Waveform (1) (CWE = High, COE = Low, CS = Low) 



CALEN 



X 



tCALEN 











tRC _ 



Address 



Dout/ 
DP0, DP1 







•asl 



<AHL 



x 



x 



External Address Valid 



tAA 



Ul2 



tOH 



JCE 



X 



Data Valid 



314 



HITACHI 

I, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Read Timing Waveform (2) (CWE = High, COE = Low, CS = Low) 



HM62A168/HM62A188 Series 




A12 



Dout/ 
DPO, DP1 



• Read Timing Waveform (3) (CWE = High) 

'CALEN 



CALEN 



Address 



CS, CE 



COE 



Dout/ 
DPO, DP1 



y 



X 



Jasl. 



tAHL 



tRC 



External Address Valid 



tAA 



tA12 



tcs 



tCE 



JLZ_ 



'OLZ 



t OE 



y 



x 



y 



'hz 



y_ 



tOHZ 



Data Valid 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 31 5 



HM62A168/HM62A188 Series 
• Write Cycle 



ParamptPr 
r dldlllcLLl 


^ v m Kr» l 

Jj 11 ILMJI 


HM62168-25 
HM62188-25 


HM62168-35 
HM62188-35 


HM62168-45 
HM62188-45 


Unit 






Min. 


Max. 


Min. 


Max. 


Min. 


Max. 




Write Cycle Time 




25 




35 




45 




ns 


Address Valid to End of Write 


^AW 


18 




25 




40 




ns 


A l2 Valid to End of Write 


^A12W 


18 


- 


25 


- 


40 


- 


ns 


Chip Select to End of Write 


^TW 


18 




25 




30 




ns 


Data Valid to End of Write 


<DW 


10 




10 




15 




ns 


uata Hold rrom tnu or write 


'dh 


o 




o 









ns 


Write Enable Active to High-Z 


l WHZ 




15 








20 


ns 


Write Enable Inactive to Low-Z 


l WLZ 


3 




3 




3 




ns 


write Pulse width 


%P 


18 




25 




30 




ns 


Cb Pulse Width During Chip Enable 
Controlled Write 




18 




25 




30 




ns 


Address Setup Time 


<AS 

















ns 


Write Recovery Time 


l WR 












2 




ns 


Address Latch Enable Pulse Width 


l CALEN 


X 




10 




15 




ns 


Address Setup to Latch Low 


( ASL 


4 




6 




10 




ns 


Address Hold to Latch Low 


'ahl 


5 




5 




5 




ns 



<§► HITACHI 

316 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Write Timing Waveform (1) (COE = High, 

'CALEN 



HM62A168/HM62A188 Series 



CALEN 



Address 



Uhl 





twc 






^ 




< 


External Address Valid 




> 


tAW 








t A !2W 




tWR 





tAS 



WE 



Din/ 

DPO, DP1 



tcp 



' ////////////////////, 



'WP 



OK 



l DW 



'DH 



Data Valid 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 1 7 



HM62A168/HM62A188 Series 

• Write Timing Waveform (2) (COE = 



High, CE Controlled) 



CALEN 



CE 



tcALEN 



<ASL 



X 



<AHL 





twc 






— (•>• 


< 


External Address Valid 




> 


« ,AW * 








Z tA12W I 




tWR 





tAS 



_ X 



tcp 



Din/ 

DPO, DP1 







OK 



'DW 



-A 



— 



DH 



Data Valid 



318 



Hitachi America, Ltd. • Hitachi Plaza • 2 



HITACHI 



HM67C932 Series- Preliminary 

8,192-Word x 9-Bit x 4-Row Static Cache RAM 

■ DESCRIPTION 

The Hitachi HM67C932 is a high speed 288-kbit static cache RAM 
organized as 4-way set associative 8k x 9 or direct mapped 32k x 9 
with 4-row selector for burst mode. By using HM67C932 with high 
speed standard microprocessors a high performance computer sys- 
tem can be achieved. 

The HM67C932, packaged in a 44-pin PLCC is available for high 
density mounting. 

■ FEATURES 

• For High Speed Standard Microprocessors 

• High Speed Access Capability with Lower 2-address by Selector 

• Pipeline Access Capability with On Chip Address and Row Latches 
(Edge Trigger Type Row Latch)* 

• On Chip Parity Generator and Checker 

• Organization 288-kbit (8-kw x 9 bit x 4 row) 

• Drivability for Heavy Load (C L = 100 pF) A 

• PLCC 44-pin 

• TTL I/O 

'For cache RAM with transparent row latch, request data sheet HM67B932. 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM67C932CP-20 
HM67C932CP-25 


20ns 
25ns 


44-pin PLCC 




PIN ARRANGEMENT 



». ] 7 

A, ] I 

A, ] 1 

NC ]« 

Vcc ]ll 

Kf ]l2 

«>• ]is 
Vcco ]i7 



A3 A4 AS « M-EVqVcc <7 M U \t 



ie la 20 21 22 23 a n n 27 28 
rir-innnnnnnnr-i 

Vmo lO, V„ IO,Vcc*aolO. lO, Vcc K).Vcco 



)»C A„ 
Ml A„ 

pc 

3SC Vo 
3<C CS 
33C M 
Sll 5e 
31 C IO. 
30 C lOr 
21 C V,„ 



(Top View) 



MAIN CHARACTERISTICS 



Item 


Spec. 


Remarks 


Access 
Time 


Address Access Time (max.) 


20/25ns 




Row Select Access Time (max.) 


10/ 13ns 


C L = lOOpFA 


OE Access Time (max.) 


10/ 13ns 




Cycle Time (min.) 


25/30ns 


Clock Frequency 
33 - 40 MHz 


Power Dissipation (typ.) 


0.8W 


V cc = 5.0V 
tcvc = 60ns 



PIN DESCRIPTION 



Pin Name 


Function 


ALE 


Address Latch Enable 


Ao-A, 2 


Address 


RLE 


Row Latch Enable 
(Edge Trigger) 


Rrj-R, 


Row 


I/O -I/O 7 


Data Input/Output 


i/o 8 


Data Input/Output 
(Even Parity) 


CS 


Chip Select 


WE 


Write Enable 


OE 


Output Enable 


PC 


Parity Control 


PError 


Parity Error Output 
(Open Drain) 


V CC 


Power 




V SS 


Ground 


V CCQ 


Power 
(For Output Transistors) 


V SSQ 


Ground 
(For Output Transistors) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 31 9 



HM67C932 Series — 
■ BLOCK DIAGRAM 



OE 



ALE 



WE ' 
R0.1: 



RLE ~t 



2 jj 

TV 



I \ / 



Dout 
Selector 



Address 
WE Dout 
8k word X 9 bit 

Dim 

~7S. 



^AJ Parity 
^ — / Checker 



,_| Parity 
Geneator 



PC ■ 
CS ■ 



D10-7 



c 



** 

Perror 



• Edge Trigger 
Ai. ** Open drain 



I FUNCTION TABLE 
Truth Table 



CS 


OE 


WE 


PC 


Mode 


V cc Current 


I/O Pin 


PError Pin 


Ref. Cycle 


H 


X 


X 


X 


Not Selected 


•sb. Isbi 


High Z 


High Z 




L 


H 


H 


X 


Output Disabled 


Ice. Icci 


High Z 


High Z 




L 


L 


H 


X 


Read 


•co Icci 


I-*out 


High Z or L (Error) 


Read Cycle No. 1, 2 


L 


H 


L 


L 


Write 


Ice. Icci 


D in 


High Z 


Write Cycle No. 1-5 


L 


L 


L 


L 


Write 


Ice Icci 


D in 


High Z 


Write Cycle No. 6, 7 


L 


H 


L 


H 


Write (Parity Generate) 


•cc> Icci 


Di„<» 


High Z 


Write Cycle No. 1 


L 


L 


L 


H 


Write (Parity Generate) 


Ice. Icci 


D m (1 > 


High Z 





NOTE: 1 . Dis input is ignored and generated as parity bit from Dio to D17. 



Input Latch Table 
Address Latch 



Row Latch 



ALE 


Mode 


Latch Output 


RLE 


Mode 


Latch Output 


H 


Load 


Address Input 


t 


Load 


Row Input 


L 


Hold 


Previous Address 


HorL 


Hold 


Previous Row 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. 



CA 94005-1819 • (415) 589-8300 



HM67C932 Series 

■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Voltage on Any Pin Relative to V s $ 


V T 


-0.5 to +7.0 


V 


Operating Temperature Range 


T 


Oto +70 


°C 


Storage Temperature Range (With Bias) 


Tstg(bias) 


-10 to +85 


T 


Storage Temperature Range 


T slg 


-55 to +125 


°C 



■ RECOMMENDED DC OPERATING CONDITIONS (T a = to +70°C) 



Item 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 











V 


Input Voltage 


V, H 


2.2 




V CC + 0.5 


V 


V,L 


-0.5(0 




0.8 


V 



NOTE: 1. -3.0V for pulse width < 20ns. 



■ DC AND OPERATING CHARACTERISTICS (V cc = 5V ± 10%, T a = to + 70°C, V ss = 0V) 



Item 


Symbol 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Input Leakage Current 


Ili 


V cc = 5.5V,V IN = V ss toV cc 






2 


/iA 


Output Leakage Current 


Ilo 


CS = V IH or OE = V IH or 
WE = V IL , V I/0 = V ss to V cc 






10 


?A 


Operating Power Supply Current 


Ice 


CS = V IL , I I/0 = 0mA 






TBD 


mA 


Average Operating Current 


Icci 


Min. Cycle, Duty: 100%, I 1/0 = 0mA 






TBD 


mA 




'SB 


CS = V IH 






TBD 


mA 


Standby Power Supply Current 


IsBl 


CS > V cc " 0.2V 

V IN < 0.2V or V, N > V cc - 0.2V 






TBD 


mA 


Output Low Voltage 


Vol'" 


I 0L = 16mA 






0.4 


V 


Output High Voltage 


V 0H 


'oh = -8mA 


2.4 






V 


I OH = -100/iA 


2.7 






V 



■ CAPACITANCE (T a = 25 °C, f = 1.0MHz) 



Item 


Symbol 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Input Capacitance 


Cta 


V in = 0V 






6 


pF 


Input/Output Capacitance 


c i/o 


Vi/o = ov 






10 


pF 


Output Capacitance (PError) 




v out = ov 






10 


pF 



<§► HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 321 



HM67C932 Series 



I AC CHARACTERISTICS (V cc = 5V ± 10%, T a = to +70°C) 
AC Test Conditions 

• Input Pulse Levels: 0.4V to 2.4V • Input Rise and Fall Times: 4ns 

• Input Timing Reference Levels: 0.8V, 2.0V • Output Load: See Figure 

• Output Timing Reference Levels: V OL = 0.8V, 

V OH = 2.0V 



Dout 
cr 



30on: 



100pF 




Output Load A 



+ 5V 



PError 
O 



:50pF* 



777 



Output Load C 



Dout 



300f 




777 777 



Output Load B 

or k:HZ' l WHZ' ^HZ- *CLZ' *OW & *OLz) 



+ 5V 
287 a 



PError 
O 



=f=5pF« 



777 



Output Load D 
(for t APH , t LEPH , t RPH , tgpH & tQ PH ) 



♦Including scope and jig. 



HITACHI 

322 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM67C932 Series 



• Read Cycle 



Item 


Symbol 


HM67C932-20A 


HM67C932-25 


Unit 


Min. 


Max. 


Min. 


Max. 


rvcdu ^ywic 11111c 


*RC 


25 




30 






Rrau Qplpptor Rpad fvclp Timp 


tRCR 


15 




_--18 






ArlHrpcc I utph Fnahlp RiiIcp AA/idth 


*LEW 


5 




7 






Addrpc« I utph Fnahlp Qptnri Timp 


l LES 


j 










Addrp<;« T atrh Fnahlp Hold Timp 
AUUICas LidLeil CllaUlC nUlU 1 1111C 


*LEH 






3 






Row I atrh Fnahlp PnRp Width 


*REW 






7 




ns 


Row T atph Fnahlp Spfnn Timp 

SSXJYV L-i0.lK.ll i^llOtUlt; OCIUU 1IJ11C 


l RES 


3 




5 






Row T atrh Fnahle Hold Time 


*REH 


3 




3 






Addrp<;*; Arres** Time 


l AA 




20 




25 


ns 


Ontniit Hold from Address f^hanap 


k)H 


5 






o 




Addrpc<; I atph Fnahlp Arrpss Timp 


'ale 




90 

zu 




ZJ 




f~^ntr»nt Hold from PnH of Addrpcc I nt/*h HolH 

WULLIUl nUlU 11U1I1 1_.HU Ul /AUU1CS& l_.all_ll 1 1U1U 


l OLEH 


e 

J 










Row Qplpr*tor Apppss Timp 
I\UW OCICU-LUI /AL\,C&» 11111C 


l RA 




in 






ns 


Ontmit Hold from Row ^plpptor Phanap 
VJLlLpUL nuiu 1IUIII lxUW OCJC-LUI l^IlallgC 


! ORH 


o 
U 




n 




ns 


l_-llip OGlCl'i rtCLCas 1 line 


l ACS 




zu 




Zj 


ns 


f^riin \p|pptif\n to fliitr^nt in t o\i/ 7 
V^IIip OLICCLIOU LU WUipUL ill LOW L, 


* ^(1), (3) 


u 




u 




ns 


f'hin Tipcplpr'tion to f~lntrMtt in Hit*h 7 
v^llip L/CdCICCLIUIl LU wiHpuL 111 nigll 


(3) 

l CHZ 


n 
u 


o 
o 


L/ 


in 


ns 


Onrnnt Fnahlp to Onrnnt Valid 
WllipUL CllaUlC LU WUipUl VdllU 


H3E 


ri 


IU 


A 

u 




ns 


f^liitnut Fnahlp to fltitont in I ow 7 
WUIJJUI ElldUlC LU WUipill 111 LOW / j 


t rtI (3) 


(J 




U 




ns 


("intniit T^ieahlp to fhitmit in Hitrh 7 
WUipiiL Ult>a\JlC LU v/UipUl 111 nigll __ 


t^„_,(l), (3) 
l OHZ ' 


o 

u 




o 
U 


in 
IU 


ns 


rtUUILsi IU rATHy CI1U1 VdllU 


« 

Upe 




z_> 




in 


ns 


Addrpco f rianftp to P_rit\/ Crrnr in Hicrh 7 

nuuicSft i^iidiigc lu rdi iiy ciiui in nigii 


t.™.(2) (3) 


c 




e 

J 




ns 


Addrpcc T atfh Fnahlp to Paritv Prrnr \7aliH 
nuuicas Ldicii ciiduic LO Jr di liy giioi VdllU 


'lepe 




Zj 




•an 


ns 


Pn/i r*f A HHrpcc T ati^h T-Ii^l H tr\ Oo r it*/ 1^ rrA r- i n Hi rrVi 7 

cjiu ui /\uurca_ Ldicii jnoiu lu raniy Error in riign __ 


t f2> (3) 

'leph 


5 




5 




ns 


Row Selector to Parity Error Valid 






15 




18 


ns 


Row Selector Change to Parity Error in High Z 


t RPH (2),(3) 


3 




A3 




ns 


Chip Selection to Parity Error Valid 


•CPE 




25 




30 


ns 


Chip Deselection to Parity Error in High Z 


t CPH (2).0) 












ns 


Output Enable to Parity Error Valid 


toPE 




15 




18 


ns 


Output Disable to Parity Error in High Z 


top H (2), (3) 












ns 



NOTES: 1. Transition is measured ± 200mV from steady state voltage with Load B. 



2. Transition is measured ± 200mV from steady state voltage with Load D. 

3. This parameter is sampled and not 100% tested. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 323 



HM67C932 Series 



• Timing Waveform of Read Cycle No. 1 (Cache Read Cycle) 0) 

tRC 



ALE 



'lew 



'LES 



V?7Z»<~ X777V////////////////% ^?ZV, 



RLE 



tLEH 



tLEW 



ILES 



'res - 



'REW 



' tLEH 



tLEPH 



■ tREH 



=5 



Dout 



PError 




tOE 



.toLZ. 



&///////// 



MS///?/////, 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Timing Waveform of Read Cycle No. 2 (Serial Read Cycle With Row Selector) ( 1 >. ( 2 ) 



HM67C932 Series 



*LEW 



*LES 







~t|_EH 



Address 7^^) ^^77//////////////////////////A 



tRES 



tRCR 



tREVV 



tAA 



tALE 



tOH 



tOLEH 



Previous 
Data Valid 



tRES H 
-tREH 



tRCR 



^REW^ 



tRA 



tORH 



'res- 

♦tREH 



Jrevv 



tRCR ^ 



tRA 



tORH 



tAPE 



tLEPE 



Japh 



S S/7V Data ^S/VV' Data ^s/VV 
jPvV^ k Valid 1 # \h/ \ Va d 2 Jt\/v\ 



tRES" 
"tREH 



Jrevv 



tRA 



tORH 



tRPE 



tRPH 



tLEPH 



tRPE 



tRPH 



PEiror Previous PError Valid ] / \ PError ^PErrorJ/ ^^J7 



"tREH 



tRA 



tORH 



Data 
Valid 3 



tRPE 



tRPH 



^s/VV r Data 
j^NA/^ k Valid 4 

tRPE 



tRPH 



NOTES: 1 . WE = Vm,_PC: Do not care 
2. CS = Viu OE = V 1L 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 25 



HM67C932 Series 
• Write Cycle 



Item 


Symbol 


HM67C932-20 


HM67C932-25 


Unit 


Min. 


Max. 


Min. 


Max. 


Write Cycle Time 


'wc 


25 





30 





ns 


Chip Selection to End of Write 


*cw 


15 





20 


_ 


ns 


Address Setup Time 


Us 














ns 


Address Latch Enable Setup Time 


'ales 





— 








ns 


Row Selector Setup Time 


l RS 














. 

ns 


Address Valid to End of Write 


[ AW 


15 





20 





ns 


Write Pulse Width 


'wp 


12 





15 





ns 




Write Recovery Time 


'WR 


3 





3 





ns 


Write Recovery to End of Address Latch Hold 


'lewr 


3 





3 





ns 


Write Recovery to Row Selector Change 


'rwr 


5 





5 





ns 


Write to Output in High Z 


t WHZ (D, (2) 





8 





10 


ns 


Data Valid to End of Write 


'dw 


8 




10 




ns 


Data Valid to End of Write (Parity Generate Mode) 


'DW2 


12 




15 




ns 


Data Hold Time 


'dh 












ns 


Output Active from End of Write 


t ow (D.(2) 












ns 


Parity Control Setup Time 


'pw 


12 




15 




ns 


Parity Control Hold Time 


'PH 









1 




ns 



NOTES: 1. Transition is measured ±200mV from steady state voltage with Load B 



2. This parameter is sampled and r 



: 100% tested. 



HITACHI 

326 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM67C932 Series 



Timing Waveform of Write Cycle No. 1 (Cache Write Cycle) 0). < 2 > 



ALE 



twc 



7l 



tLES TTeT 




RLE 



Row 



tLES ILEH 



W//////////////////MMm ~* 



Ires 



wzm . 



O 

5 tREH 



Jrs_ 







7 



(as 



'ales 



WE 



Dout 



Din 



PC 



lOHZ 



tAW 



. <RWR 



u 'WP a 



y High Impedance 



'DWl/tDW2 



1 



Ilewr 



tRES 'REH 







twn 







tOLZ 
+> 



High Impedance 




NOTES: 1 . CS = V, L , PError: Do not care. 

2. Dig input is not cared with parity generate mode. Parity of written data is not checked. 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



327 



• Timing Waveform of Write Cycle No. 2 (OE = H, WE Controlled) 17) 



Address 



RLE 



<wc 



tRES 

R0» XX 



X 



tREW 



HtREH l RES[- 

xxxxxxxxxxxxxxxxm 



WE 



Din 



Dout 



tAS 



tyyp'i 



tREH 



XX 




tRWR 



Data Valid 



;kxxxx xx xx 



High Impedance 



Address 

RLE 
Row 

CS 



of Write Cycle No. 3 (OE = H, CS Controlled) (?) 
« twe 



X 



tRES 



XX 



tREW 



tAS 



tRS- 



r 



"H tREH tRES I- 

xxxxxxxxxxxxxxxxxxW 



X 



tew 



A 



tAW 



- xWWWWWW . 



twp' 1 



Din 
Dout 



XXXXXXXXXXXXX* ' 



tow 



twR 



tRWR 



tREH 



;<x 



////////////A 



tDH, 



Data Valid 



xxxxxxxxx 



High Impedance 



HITACHI 

328 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • I 



HM67C932 Series 

• Timing Waveform of Write Cycle No. 4 (OE = Clocked, WE Controlled) P5 



Address 



RLE 



twc 



X 



tRES 

Row XX 



<REW 



X 



OE 



tREH 



XSESSEffiffiESXXX 

tAW 



5s 



Jr^ 



tAS 



tWP'1 



/////////////A 



Dout 



3> 



tOHZ'2 

High Impedance 



Din 



High Impedance 



/ 



tWR 



r 



tRES 



tREH 



tnwR 



tOLZ*2 



tDH , 



Data Valid 




> 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 29 



HM67C932 Series 



• Timing Waveform of Write Cycle No. 5 (OE = Clocked, CS Controlled) <7) 



Address 



RLE 



twc 



X 



Ires 



tREW 



X 



y — \ 



tREH 



tAW . IWR 



OE V///////4 

tRS 

cs 



tAS 



X 



tWP'1 



Din 



Dou( High Impedance 



tpw 



r 



tRES 



tREH 



'rwr 



tDH 



Data Valid 



^2X 



HITACHI 

330 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM67C932 Series 



• Timing Waveform of Write Cycle No. 6 (OE = L, WE Controlled) (7) 



Address 



'wc 



RLE 



tRES 



Row 



WE 



Dout 



Din 



tREW 



X 



tREH 



tAW 



- \\\\\\\\\M 



tfts 



tAS 



tew 



m v/////////, 



twp'i 



tyvHZ'2 



High Impedance 



tDW 



tWR 



r 



tRES 



tREH 



tRWR 



tQH 



tDH 



tORH 



Data Valid 



— » 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 331 



• Timing Waveform of Write Cycle No. 7 (OE = L, CS Controlled) W 



Address 



RLE 



CS 



Dout 



Din 



X 



tRES 

Row 



twc 



tREW 



X 



y \ 



tREH 



xmraraxmx 

tAW 



tAS 



X 



tew 



/ 



tCL2l 



twp'i 



■Si 



tWHZ 

High Impedance 



Impedance 



Jpw 



— 



r 



tRES 



tRWR 



tREH 



XX 



V////////////, 



tfJH 



Data Valid 



NOTES: 1 . A write occurs during the overlap (twp) of a low CS and a low WE. 

2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not 
be applied. 

3. Output data is the same phase of write data of this write cycle. 

4. If the CS low transition occurs after the WE low transition, output remains in a high impedance state. 

5. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the 
outputs must not be applied to them. 

6. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remains in 
high impedance state. 

7. ALE = V| H , PC = V[ L , PError: Do not care. 



HITACHI 

332 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HB66B1616A-25/35 

16,384-Word x 16-Bit High Speed Static RAM Module 

■ DESCRIPTION 

The HB66B1616A is a high speed 16K x 16 Static RAM module, 
mounted 4 pieces of 64K bit SRAM (HM6289JP) sealed in SOJ pack- 
age. An outline of the HB66B1616A is 36-pin dual in-line package. 
Therefore, the HB66B1616A makes high density mounting possible 
without surface mount technology. The HB66B1616A provides com- 
mon data inputs and outputs. Its module board has decoupling ca- 
pacitors to reduce noise. 

■ FEATURES 

• Single 5V(± 5%) Supply 

• High Speed 

Access Time 25/35ns (max.) 

• Low Power Dissipation 

Active Mode 1200mW typ. 

Standby Mode 300mW typ. (TTL level) 

• Equal Access and Cycle Time 

• Completely Static RAM 

No Clock or Timing Strobe Required 

• Directly TTL Compatible: All Inputs and Outputs 



0.4mW typ. (CMOS level) 



■ ORDERING INFORMATION 



Part No. 


Access 


Package 


HB66B1616A-25 


25ns 


36-pin dual in-line 


HB66B1616A-35 


35ns 


leaded rype 



PHYSICAL OUTLINE 




■ PIN ASSIGNMENT 



DQo 1 



DQi 
DQ 2 
DQ 3 
Ao 
A, 
A 2 
A 3 8 
A 4 9 
A 5 10L 
A 6 11[ 
A 7 12 
DQ 4 13 
DQ 5 14 
DQ 6 15 
DQ 7 16 
CS 17 
GND 18 



J36 Vcc 
35 DQ15 
34 DQ14 
33 DQ13 
32 DQ12 
31 GND 

J30 A13 
29 A12 
28 An 
27 A10 

J 26 A 9 
25 As 

J 24 DQn 

] 23 DQ10 
22 DQ 9 
21 DQ 8 
20 WE 
19 OE 



(Top View) 



■ PIN DESCRIPTION 



Pin Name 


Function 


A o ~ A 13 


Address Input 


DQo - DQ 15 


Data-in, Data-out 


CS 


Chip Select 


WE 


Write Enable 


OE 


Output Enable 


Vcc 


Power Supply (+5V) 


GND 


Ground 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (41! 



HB66B1616A-25/35 



BLOCK DIAGRAM 



OE •- 

CS •- 

DQO •- 

DQ1 •- 

DQ2 •- 

DQ3 •- 



DQ4 
DQ5 
DQ6 
DQ7 



DQ8 •- 
DQ9 •- 
Q10 •- 
DQ11 •- 



DQ12»- 
DQ13»- 
DQ14«- 
DQ15«- 



1/01 CS OE 
I/02 

I/03 MO 
I/04 



1/01 CS 
I/02 

I/03 M2 
I/04 



OE 



1/01 CS 
I/02 

I/03 M3 
I/04 



OE 









1/01 CS OE 


I/02 






I/03 


M1 




I/04 







M0-M3 : HM6289JP 



A0-A13 •- 
WE •- 
Vcc +- 



GND 



M0-M3 
M0-M3 
^ M0-M3 



C0-C5 



M0-M3 



HITACHI 

334 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



ABSOLUTE MAXIMUM RATINGS 



HB66B1616A 25/35 



Parameter 


Symbol 


Value 


Unit 


Voltage on Any Pin Relative to V ss 


v in 


-0.5(0 to +7.0 


V 


Power Dissipation 


P T 


4.0 


W 


Operating Temperature Range 


T pr 


Oto +70 


°C 


Storage Temperature Range 


T stR 


-55 to + 125 


°C 


Storage Temperature Range Under Bias 


Tbias 


-10 to +85 


°C 



NOTE: 1. V in min. = -2.0V for pulse width < 10ns. 
■ TRUTH TABLE 



CS 


OE 


WE 


Mode 


Vcc Current 


I/O Pin 


Ref. Cycle 


H 


X 


X 


Not Selected 


Isb> Isbi 


High-Z 




L 


L 


H 


Read 


Ice 


D ou . 


Read Cycle (1-3) 


L 


H 


L 


Write 


Ice 


D in 


Write Cycle (1) (2) 


L 


L 


L 


Write 


I C c 


Din 


Write Cycle (3-6) 



NOTE: X means don't care. 
■ ELEC 




nditions (T a = to 70°C) 



Parameter 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.75 


5.0 


5.25 


V 


Vss 


0.0 


0.0 


0.0 


V 


Input High (Logic 1) Voltage 


VlH 


2.2 




6.0 


V 


Input Low (Logic 0) Voltage 


VlL 


-0.5W 




0.8 


V 


NOTE: 1. Vj L min. = -2.0V for pulse width < 10ns. 

■ DC ELECTRICAL CHARACTERISTICS (T a = to 70°C, V cc = 5V ± 5%, V ss = 0V) 



Parameter 


Symbol 


Test Condition 


Min. 


Typ.O 


Max. 


Unit 


Input Leakage Current 


Ili 


V cc = Max., V in = V ss toV cc 


-10 




10 


M 


Output Leakage Current 


Ilo 


cs = V IH , V I/0 = V ss to V cc 


-2 




2 


AA 


Operating Power Supply Current 


Ice 


CS = V IL , I I/0 = 0mA 
Min. Cycle 




240 


480 


mA 


Standby Power Supply Current 


IsB 


CS = V 1H Min. Cycle 




60 


120 


mA 


Standby Power Supply Current (1) 


ISBI 


CS = > V cc -0.2V 
0V < V in < 0.2V or 
V in 2= V cc -0 2V 




0.08 


8 


mA 


Output High Voltage 


V OH 


Ioh = -4mA 


2.4 






V 


Output Low Voltage 


Vol 


Iql = 8mA 






0.4 


V 


NOTE: 1. Typical limits are at Vcc = 5.0V, T„ = +25°C and specified loading. 
■ CAPACITANCE (T a = 25°C, f = lMHz)C) 



Parameter 


Symbol 


Test Conditions 


Min. 


Max. 


Unit 


Input Capacitance (Address, CS, OE, WE) 


C in 


V, n = 0V 




35 


pF 


Input/Output Capacitance (DQ) 


c i/o 


V,/o = ov 




15 


pF 



NOTE: 1 . This parameter is sampled and not 100% tested. 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 335 



I AC CHARACTERISTICS (T a = to 70°C, V cc = 5V ± 5%, unless otherwise noted.) 
Test Conditions 

• Input Pulse Levels: V ss to 3.0V 

• Input and Output Timing Reference Levels: 1.5V 

' 



1 Input Rise and Fall Times: 5ns 
1 Output Load: See Figures 




+5V 



Dout 



255 U 



30 pF* 



255 Q 



T5pF* 



777 

Output Load A 



777 



Output Load B 
(for tc HZ , t CLZ , tQ HZ , tp LZ , t WHZ & tp W ) 



♦Including scope and ji 

• Read Cycle 



itance. 



Parameter 


Symbol 


HB66B1616A-25 


HB66B1616A-35 


Unit 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


l RC 


25 




35 




ns 


Address Access Time 


<AA 




25 




35 


ns 


Chip Select Access Time 


l ACS 




25 




35 


ns 


Chip Selection to Output in Low-Z 


tCLZ ( " 


5 




5 




ns 


Output Enable to Output Valid 


l OE 




12 




15 


ns 


Output Enable to Output in Low-Z 


tOLZ<" 












ns 


Chip Deselection to Output in High-Z 


tCHZ<" 





12 





20 


ns 


Chip Disable to Output in High-Z 


W* 





10 





10 


ns 


Output Hold from Address Change 


tOH 


3 




5 




ns 


Chip Selection to Power Up Time 


l PU 












ns 


Chip Deselection to Power Down Time 


l PD 




25 




30 


ns 



NOTE: I. Output transition is measured ±200mV 
This parameter is sampled and not 100% 



from steady state voltage with Load (B). 
tested. 



HITACHI 

336 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Read Timing Waveform (1) 0) 



Address 



tRC 



X 



tAA 



OE £ 



tOE 



tOLZ 



5s 



tACS 



tCLZ 



Dout 



x 



#/////////, 



tOH 



/? ///////////, 



tOHZ 



tCHZ 



XC^ 



Read Timing Waveform (2) (D (2) W 



Address 



tRC 



X 



tAA 



tQH 



Dout 



x 



tQH 



Read Timing Waveform (3) 0) (3) (4) 



CS 



Dout 



tACS 



tCLZ 



tpu 



Vcc supply , 
current — 



A™ 



X 







tCHZ 



50% 



NOTES: 1 . WE is high for read cycle. 

2. Device is continuously selected, CS = Vil. 

3. Address valid prior to or coincident with CS transition low. 

4. OE = V IL . 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



337 



HB66B1616A-25/35 



Write Cycle 



Parameter 


Symbol 


HB66B1616A-25 


HB66B1616A-35 


Unit 


Min. 


Max. 


Min. 


Max . 


Write Cycle Time 




25 




35 




ns 


Chip Selection to End of Write 




20 




30 




ns 


Address Valid to End of Write 




20 




30 




ns 


Address Setup Time 









o 




ns 


Write Pulse Width 


^WP 


20 




30 




ns 


Write Recovery Time 


t\YR 












ns 


Output Disable to Output in High-Z 


W" 





10 





10 


ns 


Write to Output in High-Z 


t WH Z (1) 





8 





10 


ns 


Data to Write Time Overlap 


'dw 


12 




20 




ns 


Data Hold from Write Time 


( DH 












ns 


Output Active from End of Write 


W" 


5 




5 




ns 



NOTE: 



Output transition is measured ±200mV from steady state voltage with Load (B). 
This parameter is sampled and not 100% tested. 



rm(1) (OE = H, WE Controlled) 



Address 



twc 



X 



WE 



Data In 



Dout 



>C 















* tAS „ 


tAW > 

I _ twp*1 










> 


t 






^ Data Valid ^( 


x<xxxxxx 



High Impedance 



HITACHI 

338 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Write Timing Waveform (2) (OE = H, CS Controlled) 



HB66B1616A-25/35 



Address 
CS 

wi 

Data In 
Dout 



> 


< ) 








tAW „ 

< tew , 










\ / 


„ twR*2 > 






V////////////, 










XXXXXXXXXXXXXXXX) 


^ Data Valid )< 


:xxxxxxx> 



High Impedance 



• Write Timing Waveform (3) (OE = Clocked, WE Controlled) 



Address 



OE 



twe 



X 



'/////////# 



cs 



WE 



Dout 



Din 



tew 



'aw 



tAS, 



#////////////, 



twp'1 



tQHZ*3 



High Impedance 



tpw 



X 



.tWR'2 , 



X 



tOLZ 



tc 



, tDH 



Data Valid 



xx> 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 39 



HB66B1616A-25/35 

• Write Timing Waveform (4) (OE = Clocked, CS Controlled) 

twc 



Address 

OE 
CS 

WE 

Din 
Dout 



x 



X 



— 



tAS 



tew 



tWP'1 











XX 



, <////////////, 



Data Valid 



High Impedance 



XXX 



340 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Write Timing Waveform (5) (OE = L, WE Controlled) 



Address 



'wc 



X 



WE 



Dout 



Din 



tew 



//////////////, 



tAW 



IAS ty 



tWP'1 



tWHZ'3 
>■ 



»»»»»»»» 2> 



High Impedance 



High Impedance 



tDW 



x 



.tWR'2. 



Y 



tow 



tOH 



tDH 



tC^Xffi 



Data Valid 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 341 



HB66B1616A-25/35 



• Write Timing Waveform (6) (OE = L, CS Controlled) 



Address 
CS 

WE 

Dout 

Din 









) 


< > 


/ 














s 


* > 


twR "2 




tAW 












\ ) 




V////////, 


tCLZ 




' ^ High Impedance 





fflffl> 



<x 



tpw 



Data Valid 



NOTES: 1 . A write occurs during the overlap of a low CS and a low WE (twp)- 

2. twR is measured from the earlier of CS or WE going high to the end of write cycle. 

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be 
applied. 

4. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output 
buffers remain in a high impedance state. 

5. If CS is low during this period, I/O pins are in the output state after tow- Then the data input signals of opposite phase 
to the outputs must not be applied to them. 

6. Doui is the same phase of write data of this write cycle, if twR is long enough. 

7. If the CS low transition occurs simultaneously with the OE high transition or after the OE transition, the output 
buffers remain in a high impedance state. 



HITACHI 

342 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HB66A2568A-25/35 

262,144-Word x 8-Bit High Speed Static RAM Module 

■ DESCRIPTION 

The HB66A2568A is a high speed 256K x 8 Static RAM module, 
mounted 8 pieces of 256K bit SRAM (HM6207HJP) sealed in SOJ 
package. An outline of the HB66A2568A is 60-pin zigzag in-line 
package. Therefore, the HB66A2568A makes high density mounting 
possible without surface mount technology. The HB66A2568A pro- 
vides separate data inputs and output. Its module board has decoup- 
ling capacitors to reduce noise. 

■ FEATURES 

• Single 5V (± 10%) Supply 

• High Speed 

Access Time 25/35ns (max.) 

• Low Power Dissipation 

Active Mode 2400mW typ. 

Standby Mode 800mW typ. (TTL level) 

0.8mW typ. (CMOS level) 

• Equal Access and Cycle Time 

• Completely Static RAM 

No Clock or Timing Strobe Required 

• Directly TTL Compatible: All Inputs and Outputs 

■ ORDERING INFORMATION 



Part No. 


Access 


Package 


HB66A2568A-25 


25ns 


60-pin zigzag in-line 


HB66A2568A-35 


35ns 


leaded type 



PHYSICAL OUTLINE 







t 0.25 



mm 



,1, 



iv.::r. 



, 6 3S Kf 
.250 REF 











1 




B pr> 





PIN ASSIGNMENT 



PD0(OPEN) 2 

NC 4 
Vcc 6 

D 8 

Qo 10 

A t2 

A 2 14 

A 4 16 

A 6 18 

Vss 20 

D 2 22 

Q 2 24 

WE 26 

_A 9 28 

CSt 30 



NC 32 
NC 34 
Vcc 36 
D 4 38 
Q 4 40 
A, 42 
A12 44 
A 14 46 
Al6 48 
NC 50 
De 52 
Q 6 54 
NC 56 
NC 58 
Vss 60 



J 1 


Vss 


] 3 


PD1(GND) 


] 5 


NC 


] 7 


D, 


] 9 


Qt 


] 11 


NC 


]13 


Ai 




Am 


17 


Am 


19 




_ 21 


U3 


23 




J 25 


Vcc 


J 27 


A _ 

Ae 


J29 




]31 


CS2 


]33 


NC 


]35 


NC 


3 37 


D 5 


]39 


Qs 


J41 


Vss 


]43 


Ait 


]45 


A13 


]47 


Al5 


]49 


A 17 


]« 


07 


]53 


Q7 


]55 


Vcc 


]57 


NC 


]59 


NC 



(Top View) 



■ PIN DESCRIPTION 



Pin Name 


Function 


An ~ A, 7 


Address Input 


D - D 7 


Data-in 


Qo ~ Qv 


Data-out 


CS,, CS 2 


Chip Select 


WE 


Write Enable 


Vcc 


Power Supply (+5V) 


Vss 


Ground 


NC 


Non-connection 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 43 



HB66A2568A-25/35 



BLOCK DIAGRAM 



CS1 
WE 
ADD 



DO •- 
QO •- 



D2 •- 
Q2 •- 



D4 



D6 •- 
Q6 •- 



ADD WE CS 
MO 

Din 
Dout 



ADD WE CS 
M2 

Din 
Dout 



ADD WE CS 
M4 

Din 
Dout 



ADD WE CS 
M6 

Din 
Dout 



CS2 



D1 •- 
Q1 •- 



D3 •- 
Q3 •- 



D5 •- 

Q5 



D7 
Q7 



ADD WE CS 
M1 

Din 
Dout 



ADD WE CS 
M3 

Din 
Dout 



ADD WE CS 
M5 

Din 
Dout 



ADD WE CS 
M7 

Din 
Dout 



Vcc 
Vss 



'C0-C7 



M0-M7 



C=0.22pF 



* M0-M7 : HM6207HJP 



HITACHI 

344 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HB66A2568A-25/35 



ABSOLUTE MAXIMUM RATINGS 



THt r a m *» 1 1* r 
idl alllClCl 


Svmhnl 


Value 


Unit 


Voltage on Any Pin Relative to V ss 


V in 


-0.5O to +7.0 


V 


Power Dissipation 


P T 


8.0 


w 


Operating Temperature Range 


T 

■opr 


Oto +70 


°c 


Storage Temperature Range 


T stf> 


-55 to + 125 


°c 


Storage Temperature Range Under Bias 


Tbias 


-10 to +85 


°c 



NOTE: 1. V in min. = -2.5V for pulse width < 
■ TRUTH TABLE 



CS,, cs 2 


WE 


Mode 


Vcc Current 


D out Pin 


Ref. Cycle 


H 


X 


Not Selected 


!SB. IsBl 


High-Z 




L 


H 


Read 


I C c 


Dout 


Read Cycle 


L 


L 


Write 


Ice 


High-Z 


Write Cycle 



NOTE: X means don't care. 

■ ELECTRICAL CHARACTERISTICS 

• Recommended DC Operating Conditions (T a = to 70°C) 



Parameter 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Vss 


0.0 


0.0 


0.0 


V 


Input High (Logic 1) Voltage 


Vffl 


2.2 




6.0 


V 


Input Low (Logic 0) Voltage 


V,L 


-0.5C) 




0.8 


V 


NOTE: 1. Vil min. = -2.0V for pulse width < 10ns. 

■ DC ELECTRICAL CHARACTERISTICS (T a = to 70°C, V cc = 5V ± 10%, V ss = 0V) 



Parameter 


Symbol 


Test Condition 


Min. 


Typ.d) 


Max. 


Unit 


Input Leakage Current 


lu 


V cc = Max., V jn = V ss toV cc 


-10 




10 




Output Leakage Current 


Ilo 


CS„ CS 2 = V m , V I/0 = V ss to V cc 


-10 




10 




Operating Power Supply Current 


I C C 


CS,, CS 2 = V IL , I I/0 = OmA 
Min. Cycle, Duty = 100% 




480 


960 


mA 


Standby Power Supply Current 


!SB 


CS,, CS : = V, H Min. Cycle 




160 


320 


mA 


Standby Power Supply Current ( 1 ) 


IsBl 


CS,, CS 2 = >: V cc -0-2V 
0V < V jn < 0.2V or 
V in > V cc -0-2V 




0.16 


16 


mA 


Output High Voltage 


V 0H 


I OH = -4mA 


2.4 






V 


Output Low Voltage 


Vol 


I OL = 8mA 






0.4 


V 



NOTE: 1. Typical limits are at V C c = 5.0V, T a = +25°C and specified loading. 
■ CAPACITANCE (T, = 25°C, f = lMHz)<0 



Parameter 


Symbol 


Test Conditions 


Min. 


Max. 


Unit 


Input Capacitance (Address, WE) 


C,l 


V in = OV 




70 


pF 


Input Capacitance (CS) 


C,2 


v,„ = OV 




45 


pF 


Input Capacitance (Data in) 


C,3 


v,„ = OV 




12 


pF 


Output Capacitance (Data out) 


Co 


v ou , = OV 




16 


pF 



NOTE: 1 . This parameter is sampled and not 100% tested. 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 345 



HB66A2568A-25/35 



I AC CHARACTERISTICS (T a = 0°C to 70°C, V cc = 5V ± 10%, unless otherwise noted.) 
Test Conditions 

• Input Pulse Levels: V ss to 3.0V • Input Rise and Fall Times: 5ns 



• Input and Output Timing Reference Levels: 1.5V 


+5 V 

Dout * 4801 

o- 



Output Load: See Figures 



Dout 



+5 V 

4800 



2550 



: 30 pF* 



2550 



/77 



Output Load A 



Output Load B 

(fOr t HZ , t LZ , t WZ & tpw) 



including scope and jig capacitance. 

• Read Cycle 



NOTE: 



1 . Transition is measured ± 200mV from steady state voltage with Load (B) 
This parameter is sampled and not 100% tested. 



Parameter 


Symbol 


HB66A2568A-25 


HB66A2568A-35 


Unit 


Min. 


Max. 


Min. 


Max. 


Read Cycle Time 


l RC 


25 




35 




ns 


Address Access Time 


t AA 




25 




35 


ns 


Chip Select Access Time 


<ACS 




25 




35 


ns 


Output Hold from Address Change 


[ OH 


5 




5 




ns 


Chip Selection to Output in Low-Z 


tLZ<" 


5 




5 




ns 


Chip Deselection to Output in High-Z 


t H z"> 





12 





20 


ns 


Chip Selection to Power Up Time 


tpu 












ns 


Chip Deselection to Power Down Time 


l PD 




15 




25 


ns 



<§> HITACHI 

346 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HB66A2568A-25/35 



• Timing Waveform of Read Cycle (1) ( 1 ) ( z ) 



Address 



Dout 











< > 


( 




tAA 




tOH h 


cz 








> 


<xx> 


^ Data Valid ^> 



• Timing Waveform of Read Cycle (2) 0) ( 3 ) 



CS 



Dout 



tRC 



tACS 



tCLZ 



tpu 



Vcc supply 
current 



tHZ 



, tpp. 



50% 



NOTES: 1 . WE is high for read cycle. 

2. Device is continuously selected, CS = Vil. 

3. Address valid prior to or coincident with CS transition low. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 47 



HB66A2568A-25/35 
• Write Cycle 



Parameter 


Symbol 


HB66A2568A-25 


HB66A2568A-35 


Unit 


Min. 


Max. 


Min. 


Max. 


W/nf*> i~'\rr*\f* TitTl*» 

wnic Lycic lime 


'wc 


25 




35 






\- IIIU JLICLIHIH \Kj dllKl LM VVI1LG 














rtuuicsa Valiu IU miu Ul wine 


'aw 






VI 








AS 


o 




o 






Write Pulse Width 


*WP 


20 




30 




ns 


Write Recovery Time 


l WR 


3 




3 




ns 


Data Valid to End of Write 


*dw 


15 




20 




ns 


Data Hold Time 


l DH 












ns 


Write Enabled to Output in High-Z 


twz"> 





8 





10 


ns 


Output Active from End of Write 


tow (2) 












ns 



NOTE: 



1 . Transition is measured ±200mV from high impedance voltage with Load (B). 
This parameter is sampled and not 100% tested. 



HITACHI 

348 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Timing Waveform of Write Cycle (1) (WE Controlled) 



HB66A2S68A-25/35 



Address 



>C 



X 



WE 

Din 
Dout 







s ////////, 








tAW „ 

tuup*1 


„ twR'2 fc 








^ ^ 


< 




xxxxxxxxxxxxxxx 


KXXXXX d-v« )<XX 


xxxxxx 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 49 



HB66A2568A-25/35 

• Timing Waveform of Write Cycle (2) (CS Controlled) 



Address 



CS1.2 



WE 
Din 
Dout 



twc 



— 



X 



tAW 



X 







tAS 



tew 



X 



X 



tWP'1 



tpw 



, twR*2 , 



y/////////////. 



. tDH 



XXXXXXXXXXXXXXXX* Data in v5 >kxxxxxxx> 

High Impedance * 3 



NOTES: 1 . A write occurs during the overlap of a low CS and a low WE. 

2. twR is measured from the earlier of CS or WE going high to the end of write cycle. 

3. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output 
buffers remain in a high impedance state. 

4. Dei is the same phase of write data of this write cycle, if twR is long enough. 



® HITACHI 

350 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM644332 



2K Entry TAG Memory for Cache Sub System 



The HM644332 TAGM is a 2048 entry tag memory 
fabricated with CMOS technology. It supports 
compact cache systems with 2-way or 4-way set 



associativity and a high level of performance for 
32-bit microprocessor systems, when used to- 
gether with fast static RAMs as data RAMs. 



Features 

• Programmable organization: 512-entryx 4-way or 

1024-entry x 2-way 

• Memory organization: 512 words x 98 bits 

98 bits = (20 tag bits + 1 parity bit + 2 validity bits) x 
4 ways + 6 LRU bits 

• Fast access time: 25/30 ns max from address inputs, 

18 ns max from tag data inputs 

• Single + 5 V supply 



• TTL-compatible inputs and outputs 

• LRU (least recently used) replacement algorithm 

• Purge functions (all purge and partial purge) 

• Internal parity generator/checker 

• 64-pin pin-grid-array 



Ordering Information 



Part No. 



Access Time 



From Address 



From Tag Data 



Package 



HM644332G-25 
HM644332G-30 



25 ns 
30 ns 



18 ns 
18 ns 



64-pin PGA 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 351 



Pin Arrangement 




Pin No. 


Function 


Pin No. 


Function 


Pin No. 


Function 


1 


N.C. 


23 


A 4 


45 


TD 6 


2 


MHIT 


24 


A 5 


46 


TD 9 


3 


HIT /REP 


25 


A 7 


47 


V CC 


4 


HIT 2 /REP 2 


26 


A 9 


48 


TD <3 


5 


HIT3/REP3 


27 


N.C. 


49 


TD ,5 


6 


TD o 


28 


N.C. 


50 


TD ,7 


7 




29 


PINV 


51 


TD ,9 


8 


EXTH 


30 


SBLK 


52 


A 


9 


MHENBL 


31 


SB, 


53 


A 2 


10 


N.C. 


32 


INH 


54 


V 

ss 


11 






INVL 


55 


A 6 


12 


TD e 


34 


SET 


56 


A 8 


13 


*>,o 


35 


H/R 


57 


PURGE 


14 


™„ 


36 


HIT 


58 


MODE 


15 


TD , 2 


37 


HC /RC 


59 


VINV 


16 


TD ,4 


38 


H^/RC, 


60 


SB o 


17 


TD ,6 


39 


HIT/REP, 


61 


v cc 


18 


TD ,8 


40 


V SS 


62 


WRITE 


19 


N.C. 


41 


TD , 


63 


RLATCH 


20 


N.C. 


42 


TD 3 


64 


PERR 


21 


A , 


43 


TO 4 






22 


A 3 


44 


TD 5 







HITACHI 

352 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM644332 



Pin Description 



Symbol 


Pin Name 


Pin No. 


I/O 


Function 


MODE 


Mode 


58 


1 


Mode selection 

MODE • H: 512-entry x 4-way 
MODE = L : 1 024-entry x 2-way 


V A 9 




Address 


52,21,53,22,23, 
24, 55, 25, 56, 26 


1 


Address inputs: A g is not used for 4-way; fix 
it to H or L 




TD 0- TD ,9 


Tag Data 


6, 41. 7, 42^»5, 
11, 12,46, 13, 14, 
15, 48, 16, 49, 17, 
50, 18,51 


1 


Tag information 












PURGE 


Purge 


57 


1 


All purge is done when PURGE = L 


INVL 


Invalidate 


33 


1 


Partial purge: V bit of specified address is 
forced to (L) 


SBLK 


Way Select Enable 


30 


1 


Enables external way selection in replace- 
ment and invalidation cycles 


CD CD 


External Way Address 60, 31 


1 


rZXlwiMdl Way dUUIcsb input. CndUiBQ WflBn 

SBLK - H 


WRITE 


Write 


62 


1 


Enables write 


SET 


Set 


34 


1 


Timing pulse 

Read cycle: Updates LRU 

Write cycle: Stores tag, sets V bits to H, 

dnu UpQalBS LrlU 

Partial purge cycle: Shifts LRU and sets 
V bits to L 


iNH 


Inhibit 


32 


1 

1 


Inhibits all functions except all purge 


H/R 


Hit/Replace Selection 


35 


1 


Output selection 

H/R = H: Hit information 
H/R = L: Replace information 


RLATCH 


Replace Latch 


63 


1 


Latch control for replace information 


PINV Parity Inversion 


29 


1 


Used for testing only 


viNV 


Validity Inversion 


59 


1 


Used for testing only 


MHENBL 


MHIT Enable 


9 


1 


Enables MHIT output 


EXTH 


External Hit Control 


8 


1 


Forces MHIT output to L 


HIT 


Hit 


36 


o 


LJ!* miIhiiAi fc 1 /*"\ n> _< l_ll"T" 4n U 1 "T 

Hit output. NUH Ot HI l Q tO HI i 3 


HC,/RC° 


Hit/Replace Code 


37, 38 


yj 


Coded output of hit or replace information 


HIT /REP Q - 
HIT 3 /REP 3 


Hit/Replace 


3,39, 
4,5 


o 


Uncoded output of hit or replace information 


PERR 


Parity Error 


64 


o 


Indicates parity error 


MHIT 


Modified Hit 


2 


o 


Hit output modified by MHENBL and EXTH 


V cc 


Power 


47, 61 


1 


Connects to + 5V power supply 


v ss 


Ground 


40,54 




Connects to ground 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 353 



HM644332 



Block Diagrams 



Internal Blocks 



fl oO- 



A 8 o- 



Address 

bultef 

and 

decoder 



Entry 



3 



Parity 
data 



Parity 
generator 



TO, 



O- 



TD. 



ISO- 



data 
buller 



Memory cells 

512 entries 
x 23 bits 
x 4 ways 



Tag 
data 



Purge 
buffer 



PURGE 



la 

l/ Memory cell 



512 entries 
x 6 bits 



Replace information 



Sense out 



7 



Comparators 



Hit information 



Parity 
checker 



Replace information 



Vi 



Iz 



LRU 

,-| logic 



MPX and 
output control 



Output control 



Hit/replace 
information 



Parity error 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 



HM644332 



Output Control Block 



TD <fJ D ,9 



"o 

\ 20 



V A e°-V 



Cell 
array 
(TAG, V) 



.88 



MHENBL EXTH 
9 9 



ft 



Compare 
and validity 
check 



■j Latch 




LRU 
update 



SET 



i 



\ 4 



Decode 



MPX 



NOR 



>HIT 



MPX 



SBLK 



-oHiyREP 
-o HIT/REP, 
-oHITj/REP 2 



Encode 



Parity 
check 




NOR 


7^ 



PERR 



6 

H/R 











HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 355 



HM644332 

Function Tables 



L Basic Functions (all combinations not listed below are inhibited) 







Input 






Tag Info. 


Control Info. LRU 
















P Bit 


VBits 




INH 


PI 


RGE SET 


WRITE 


INVL 


Tag Bits 


(Parity) 


(validity) lhu Hits 


Function Mode 


L 


H 


X 


X 


X 


No change 


No change 


No change No change 


Inhibit 3 


H 


H 


H 


X 


X 


No chanqe 


No chanqe 


No chanqe No chanqe 


Taq read 


H 


H 




H 


H 


No change 


No change 


No change No change 1 
or updated 


Tag read 


- 


H 




L 


H 


TD 0- TD ,9 


Set 


H Updated 


Tag write 


X 


L 


H 


x 


X 


Undefined 


Undefined 


L (All) Initialized 


All purge 


H 


H 


V 


H 


L 


No change 


No change 


No change No change 1 
L' 2 or shifted"* 


Partial purge 



x: HorL 

Notes: "1 When SBLK • L and there is no hit, LRU is not changed. 

"2 When SBLK = L and there is no hit, the V bits are not changed. 

"3 In inhibit mode, HIT and PERR outputs are H but all other outputs are L. 

•4 Shifted means that the partially-purged way becomes the least recently used way. 



2. Hit or Replace Information Output 



Input Internal Information 1 ' 2 Output 







hiy 


hit,/ 


hiy 


hlt 3 / 


HIV 


HIT,/ 


HIT 2 / 


HIT 3 / 


HC„/ 


HC,/ 


•3 




MODE 


\ 


re Po 


rep, 


rap 2 


rep 3 


REP 


REP, 


REP 2 


REP 3 


RC o 


RC, 


fiff 


Mode 


H 


X 


L 


L 


L 


L 


L 


L 


L 


L 


L 


L 


H 


4-way 


H 


X 


H 


L 


L 


L 


H 


L 


L 


L 


L 


L 


L 




H 


X 


L 


H 


L 


L 


L 


H 


L 


L 


H 


L 


L 




H 


X 


L 


L 


H 


L 


L 


L 


H 


L 


L 


H 


L 




H 


X 


L 


L 


L 


H 


L 


L 


L 


H 


H 


H 


L 




L 


L 


L 


X 


L 




L 


L 


L 


L 


L 


L 


H 


2-way 


L 


L 


H 


X 


L 


X 


H 


L 


L 


L 


L 


L 


L 






L 


L 


X 


H 


X 


L 


L 


H 


L 


L 


H 


L 




t 


H 


X 


L 


X 


L 


L 


L 


L 


L 


L 


L 


H 




L 


H 


X 


H 


X 


L 


L 


H 


L 


L 


H 


L 


L 




L 




H 


X 


L 


X 


H 


L 


L 


L 


H 


H 


H 


L 





x : HorL 

Notes: *1 Internal information rep Q to rep^is determined by on-chip LRU logic when SBLK = L. 

When SBLK «= H, the internal information is determined by external signals SB Q and SB 
"2 Correct operation is not guaranteed if 2 or more ways are hit at the same time. 
*3 HIT output is valid when H/R - H. 



HITACHI 

356 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM644332 



3. Partial Purge (INVL = U 
Input 



Internal Info. 



Purged Way SET 



MODE 


A 9 


SBLK 


SB o 


SB, 




hit, 


hlt 2 


hlt 3 





1 


2 


3 


u 

LRU 


Mode 


H 


X 


L 


X 


X 


L 


L 


L 


L 


— 


— 


— 


— 


No change 


4-way 


H 


X 


L 


X 


X 


H 


L 


L 


L 


Q 


— 


— 


— 


Shitted 




H 


X 


L 


X 


X 


L 


H 


L 


L 


— 


Q 


— 


- 


Shifted 




H 


X 


L 


X 


X 


L 


L 


H 


L 


— 


— 


Q 


— 


Shifted 




H 


X 


L 


X 


X 


L 


L 


L 


H 


— 


— 


— 


Q 


Shifted 




H 


X 


H 


L 


L 


X 


X 


X 


X 


Q 


— 


— 


— 


Shifted 




H 


X 


H 


H 


L 


X 


X 


x 


X 


— 


Q 


— 


— 


Shifted 




H 


X 


H 


L 


H 


X 


X 


X 


X 


— 


— 


Q 


— 


Shifted 




H 


X 


H 


H 


H 


X 


X 


X 


X 


— 


— 


— 


Q 


Shifted 




L 


L 


L 


X 


X 


L 


X 


L 


X 


— 


— 


— 


— 


No change 


2-way 


L 


L 


L 


X 


X 


H 


X 


L 


X 


Q 


— 


— 


— 


Shifted 




L 


L 


L 


X 


X 


L 


X 


H 


X 




_ 


Q 


_ 


Shifted 




L 


L 


H 


L 


L 


X 


X 


X 


X 










Shifted 




L 


L 


H 


L 


H 


X 


X 


X 


X 






Q 




Shifted 




L 


H 


L 


X 


X 


X 


L 


X 


L 










No change 




L 


H 


L 


x 


X 


x 


H 


X 


L 




Q 






Shifted 




L 


H 


L 


X 


X 


X 


L 


X 


H 








Q 


Shifted 




L 


H 


H 


H 


L 


X 


X 


X 


X 




Q 






Shifted 




L 


H 


H 


H 


H 


X 


X 


X 


X 








Q 


Shifted 





Note: Correct operation is not guaranteed if 2 or more ways are hit at the same time. 
4. Parity Error and V Bits' 



(n: 0to3) 



pen 




vn, 


PEn 


Hit Info'. 2 


L 


L 


L 


L 




L 


L 


H 


H 


Hit 


L 


H 


L 


H 


Hit 


L 


H 


H 


L 


Hit 


H 


L 


L 


L 




H 


L 


H 


H 


Hit 


H 


H 


L 


H 


Hit 


H 


H 


H 


H 


Hit 



Notes: *1 PERR is the NOR of PEO to PE3. 

"2 Output information when internal hit is valid. 



pen: Internal parity error in way n 
vnjjMi,: Duplicate validity bits. 

PEn: Determined by the following equation: 
PEn= (vn + vn,) • pen + (yn Q svn,) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 357 



HM644332 



Absolute Maximum Ratings 



»- - 
Hem 


Symbol 


Rating 


1 Intt 

unit 




Supply Voltage 


V„„ 
cc 


-0.5 to +7.0 


V 




Input Voltage at Any Pin Relative to V ss 


V 

in 


-3.0 to +7.0 


V 




Output Voltage at Any Pin Relative to V ss 


V 

out 


-0.5 to +7.0 


V 




Output Current 


'out 


±20 


mA 




Power Dissipation 


P T 


1.5 


W 




Operating Temperature 




-10 to +85 


°C 




Storage Temperature 




-65 to +125 


°C 





Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation 
should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to 
absolute maximum rating conditions for extended periods may affect device reliability. 



Recommended DC Operating Conditions (T a = to +70°C) 



Item 


Symbol 


Mln. 


Typ. 




Max. 


Unit 






Supply Voltage 


V * 1 

v cc 


4.5 


5.0 




5.5 


V 






Input Low Voltage 


V IL 


-0.5 " 2 






0.8 


V 






Input High Voltage 


V * 1 


2.2 






6.0 


V 






Notes: *1 All voltages are relative to V ss . 

*2 -3.0 V for pulse width of 20 ns or less. 














DC and Operating Characteristics (T a = to +70°C, V cc 


= 5 V ±10%, V ss = 


V) 




Item 


Symbol 


Test Conditions 




Mln. 


Typ. 


Max. 


Unit 




Operating Power 


'cc 


Min. cycle, l oul - mA 








200 


mA 




Supply Current 




Cycle = 1 00 ns, l oul - mA 






180 


mA 




Input Leakage Current 


V 


V in = V SS toV CC 




-10 




10 


uA 




Output Voltage 


V 


l 0L = 8 mA 








0.4 


V 






V OH 


'oh " ~* mA 




2.4 






V 






















Capacitances (T a 


= 25°C, f = 


1MHz) 














Item 


Symbol 


Test Condition 




Mln. 


Typ. 


Max. 


Unit 




Input Capacitance 


C in 


V = ov 








10 


PF 




Output Capacitance 


C out 










TBD 


PF 


- 



Note: These parameters are sampled, not 100% tested. 



HITACHI 

358 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 



HM644332 



AC Characteristics (T a = to +70°C, V cc = 5 V ±10%, V ss =0V, 
unless otherwise noted) 



AC Test Conditions 

• Input pulse levels: 

• Input pulse rise and fall times: 

• Input and output timing reference levels: 

• Output load: 



V to 3.0 V 

ns to 5 ns (time between 0.8 V and 2.2 V) 
1.5 V 

See figure. 



Load 



Q +5V 



D U T°- 



30pF" ' 



480 n 



255 n 



7/7- 777- 



'Including scope and jig 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 359 



HM644332 



1. Tag Read Cycle (MODE = H or L, PURGE = H, WRITE = H, INVL = H, PINV = H or L, VINV = H or L, 
INH = H) 

HM644332G-25 HM644332G-30 



Item 


Symbol 


Mln. 


Max. 


Mln. 


Max. 


Unit 


Read Cycle Time 


'rc 


50 


— 


50 


— 


ns 


Address Valid to Hit, HC , HIT 

it n 


•ah 


— 


25 


— 


30 


ns 


Address Valid to MHIT 


'amh 


— 


27 


— 


32 


ns 


Tag Data Valid to HIT, HC , HIT 




— 


18 


— 


18 


ns 


Tag Data Valid to MHIT 


'tmh 


— 


20 


— 


20 


ns 


HIT, HC . HIT Hold Time 

n n 


'hh 





- 





— 


ns 


Address Valid to RC, REP 

n n 


'ar 


— 


35 


— 


40 


ns 


Address Valid to PERR 


'ap 


— 


35 


— 


40 


ns 


Address Setup Time for SET 


'as 


25 


— 


25 


— 


ns 


Tag Data Setup Time for SET 


'ts 


25 


— 


25 


— 


ns 


SET Pulse Width 


'sw 


20 


— 


20 


— 


ns 


SET Recovery Time 


*SR 


5 


— 


5 


— 


ns 


R LATCH Setup Time 


'rls 


10 


— 


10 


— 


ns 


RC n . REP„ Hold Time for RLATCH 


'rh 





— 





— 


ns 


SBLK, SB„, SB, Setup Time for RC , REP 
1 n n 


'SBR 




25 




25 


ns 


SBLK, SB Ql SB. Hold Time 


'sBH 


5 




5 




ns 


RC , REP Hold Time for SBLK, SB„, SB, 

n n 1 


*SH 












ns 


SBLK, SB , SB, Setup Time for SET 


'SBS 


25 




25 




ns 


PERR Hold Time 


*PH 












ns 


H/R to Multiplex Output Change 


*HR 




10 




12 


ns 


MHENBL, EXTH to MHIT Output 


'mmh 




10 




12 


ns 



HITACHI 

360 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM644332 



2. Tag Write Cycle (MODE = H or L, PURGE = H, WRITE = L, INVL = H, H/R = L, INH = H) 

HM644332G-25 HM644332G-30 



Item 


Symbol 


Min. 


Max. 


Min. 


Max. 


Unit 


Write Cycle Time 


'wc 


50 


— 


50 


— 


ns 


Address Valid to RC , REP„ 
n n 


<ar 


— 


35 


— 


40 


ns 


Address Setup Time for SET 


'as 


25 


— 


25 


— 


ns 


Tag Data Setup Time for SET 


<TS 


25 


— 


25 


— 


ns 


SET Pulse Width 


'sw 


20 


— 


20 


— 


ns 


SET Recovery Time 


«SR 


5 


— 


5 


— 


ns 


R LATCH Setup Time 


RLS 


10 


— 


10 


— 


ns 


SBLK, SB , SB, Setup Time for SET 


'sBS 


25 




25 




ns 


SBLK, SB , SB, Setup Time for RC n , REP n 


'sBR 




25 




25 


ns 


RC , REP Hold Time for SBLK, SB„, SB, 
n' n 1 


<SH 












ns 


SBLK Hold Time 


*SBH 


5 




5 




ns 


PINV, VINV Setup Time for SET 


<IS 


25 




25 




ns 


PINV, VINV Recovery Time for SET 


l IR 


5 




5 




ns 


3. Partial Purge (MODE = H or L, PURGE 


= H, WRITE 


= H, INVL 


= L, H/R = 


HorL, INH 


= H, 




RLATCH = L, PINV = H or L, VINV = 


HorL) 














HM644332G-25 


HM644332G-30 




Item 


Symbol 


Min. 


Max. 


Min. 


Max. 


Unit 


Partial Purge Cycle 


'ppc 


50 




50 




ns 


Address Setup Time for SET 


'as 


25 




25 




ns 


Tag Data Setup Time for SET 


'ts 


25 




25 




ns 


SET Pulse Width 


'sw 


20 




20 




ns 


SET Recovery Time 


<SR 


5 




5 




ns 


SBLK, SB Q , SB, Setup Time for SET 


'sBS 


25 




25 




ns 


SBLK. SB , SB, Hold Time 


'sBH 


5 




5 




ns 



4. All Purge (SET = H, other control inputs are H or L) 



HM644332G-25 HM644332G-30 
Item Symbol Min. Max. Min. Max. Unit 



All Purge Cycle Time 


'apc 


100 




100 




ns 


Purge Pulse Width 


'ppw 


50 




50 




ns 




Purge Recovery Time 


'PR 


50 




50 




ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 361 



HM644332 



Timing Charts 

1. Tag Read Cycle 



H/R 



HIT, 



MHENBL, 
EXTH 



MHIT 



PERR 



SET 



R LATCH ' 



SBLK 



SB , SB,' 6 



(MODE = H or L, PURGE = H, WRITE = H, INVL = H, PINV = H or L, VINV = H or L, INH = H) 
< 'rc 







Input valid 



Input valid 



3IC 



| Khri 



X 



X 



)j ( Output valid ) C 
I 

3fC 



3 £ Output 



valid 



Input valid 



I. Vpi- 



-'amh ~ ™ H ^ =g 

) ( Ouiput valid 



I 



X 



Output valid 



| RLS 



■U 



X 



X 



Input valid 















- Input valid 



Notes: 

•1 Valid when H/R = H. 

•2 Valid when H/R = L. 

"3 LRU is updated when SET - L 

'4 Replace information is latched when RLATCH - H. 

•S Valid when SBLK . L. 

•6 Valid when SBLK = H. 



^HITACHI 

362 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM644332 



2. Tag Write Cycle 



H/R 



SET 



RLATCH ' 



SBLK 



PINV, VINV 



(MODE = H Of L, PURGE = H, WRITE = L, INVL = H, INH = H) 



Input valid 



X 



3C 



Outpul valid 



3C 



Input valid 



-'as — 



X 



X 



Input valid 



X 



X 



-A 



Input valid 



X 



Input valid 



X 



Notes: 

"1 Tag is stored, V bits go H, and LRU is updated. 
*2 Replace information is latched when RLATCH ■ H. 
'3 Valid when SBLK = L. 
•4 Valid when SBLK = H. 







HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 63 



HM644332 



3. Partial Purge Cycle 



V A 9 



SET 



SBLK 



(MODE = H or L, PURGE = H, WRITE = H, INVL * L. H/R = H or L, INH = H. RLATCH - L, 
pW=HorL,VINV = Hor L) 



Notes: 

•1 Valid when SBLK = L. 

*2 LRU is shifted and V bits go L. 

•3 Valid when SBLK = H. 





« 'ppo » 




> 


£ Input valid ^ 












/ 


« 'as » 


* 'sw » 














" *SBH 


) 


( Input valid 


'« 








> 


£ Input valid 


>( 




HITACHI 

364 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM644332 



Function Description 

Tag Read 

The TAG input data (TD Q -TD 19 ) and the contents of 
the addressed location are compared. If they are the 
same, a hit is assumed . HIT goes low and the HCn and 
HITn outputs indicate the hit way associatively. If 
there is no hit, the LRU logic of the tag RAM automati- 
cally specifies which way is to be replaced. 

The replacement information is presented at the RCn 
and REPn outputs by forcing the H/R input low. 
These signals will be latched and used for writing 
data into data memory. 

Tag Write 

If there is no hit, the tag RAM must be updated. A 
write operation i s per formed by setting WRITE low 
and inputting a SET pulse. The tag data will be 
written into the appropriate way by the internal LRU 
logic. 

The way can be also specified externally by using 
SBLK, SBjj, and SBj inputs. In tag write mode, the V 

bits (validity bits) and the parity bit are set, and the 
LRU is updated. 



All Purge 

By asserting the PURGE input low, all the V bits are 
reset and LRU is initialized. 

In this operation, the contents of each tag and its 
parity will not be identified. 

Partial Purge 

A pa rtial purge operation is p erformed by setting 
INVL low and inputting a SET pulse. 

The V bit specified by the address input is reset and 
the LRU is shifted so that the partially-purged way 
becomes the least recently used way. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM644332 



Package Dimensions 



Unit: mm (inches 



64-Pin Ceramic PGA 




2 54 ±0 25 
I (.100 i 010) 



18.24(718 ) SQ 



TYP 

26.20 .,, 



26.20_ 03 , 
(1.032*° 1 \) 



533 (.210) 
MAX 



22 86 ( 900) 
REF 



:1 



— i- 



.27 (.050) TYP DIA 



o o o o 



o o o o o © 

o o o o o o 

o o 

o o 

o o 

o o 

o o 



o o oooooooo 
6) o ooooooo© 



(-050! ) 



340 -0.36 -.014 ' 



HITACHI 

366 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Section 3 
MOS Pseudo Static RAM 



HITACHI 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



32768-word X 8-bit High Speed Pseudo Static RAM 

■ FEATURES 

• Single 5V (±10%) 

• High Speed 
Access Time 

CE Access Time 100/1 20/ 150/200ns 

Address Access Time 50/60/7 5/ 100ns 

(in Static Column Mode) 
Cycle Time 

Random Read/Write Cycle Time .... 160/1 90/235/3 10ns 
Static Column Mode Cycle Time 55/65/80/105ns 

• Low Power 
175mW typ. Active. 

• All inputs and outputs TTL compatible 

• Static Column Mode Capability 

• Non Multiplexed Address 

• 256 Refresh Cycles (4ms) 

• Refresh Functions 
Address Refresh 
Automatic Refresh 
Self Refresh 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM65256BP-10 


100ns 




HM65256BP-12 


120ns 




HM65256BP-15 


150ns 




HM65256BP-20 


200ns 


600 mil 28 pin 


HM65256BLP-10 


100ns 


Plastic DIP 


HM65256BLP-12 


120ns 




HM65256BLP-15 


150ns 




HM65256BLP-20 


200ns 




HM65256BSP-10 


100ns 




HM65256BSP-12 


120ns 




HM65256BSP-15 


150ns 




HM65256BSP-20 


200ns 


300 mil 28 pin 


HM65256BLSP-10 


100ns 


Plastic DIP 


HM65256BLSP-12 


120ns 




HM65256BLSP-15 


150ns 




HM65256BLSP-20 


200ns 




HM65256BFP-10T 


100ns 




HM65256BFP-12T 


120ns 




HM65256BFP-15T 


150ns 




HM65256BFP-20T 


200ns 


28 pin 


HM65256BLFP-10T 


100ns 


Plastic SOP 


HM652S6BLFP-12T 


120ns 




HM65256BLFP-15T 


150ns 




HM65256BLFP-20T 


200ns 





HM65256BP Series 




(DP-28) 



HM65256BSP Series 




(DP-28N) 



HM65256BFP Series 




(FP-28DA) 




PIN ARRANGEMENT 



















TjJ] A, j 


*E 




3 A- 


*{? 




24J A» 


A. (T 




7J] A.. 






a]m 






3 a,. 






m)ce 


a. [nr 




77] 10, 


i (77 






I/O. Q7 




TtJi/oi 


i d. [77 




Jji)l/o. 






77J I/O, 



(Top View) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 69 



HM65256B Series- 



■ BLOCK DIAGRAM 



I 

I 'OiO- - ■ 



Latch 



a 

si 

WE 



Conlrs 



8^- 







Timuif PuIk Chi 
Read WrrM Control 



■ TRUTH TABLE 



CE 


OE 


WE 


I/O Pin 


mode 


L 


L 


H 


Low Z 


Read 


L 


X 


L 


High Z 


Write 


L 


H 


H 


High Z 




H 


L 


X 


High Z 


Refresh 


H 


H 


X 


High Z 


Standby 



■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage with Respect to V ss 


V T 


-1.0 to +7.0 


V 


Power Dissipation 


P T 


1.0 


W 


Operating Temperature 


T 

1 opr 


to +70 


°c 


Storage Temperature 


T.« 


-55 to +125 


"C 


Storage Temperature Under Bias 


T bia* 


-10 to +85 


°c 



RECOMMENDED DC OPERATING CONDITIONS (T a = to +70°C) 



Item 




Symbol 


min. 


typ. 


max. 


unit 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


v ss 











V 


Input Voltage 


V,H 


2.2 




6.0 


V 


VlL 


-0.5*' 




0.8 


V 



Note) •!. V IL min - -3.0V for pulse width g 10ns. 



<§> HITACHI 

370 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM65256B Series 



DC ELECTRICAL CHARACTERISTICS (T a = to +70°C, V C c = 5V ±10%) 



Parameter 


Symbol 


Test Conditions 


HM65256B Series 


HM65256BL Series 


Unit 


min. 


typ. 


max. 


min. 


typ. 


max. 


Operating Power 
Supply Current 


'cci 


1,10 = 0mA 
t C y C = min. 




35 


65 




35 


65 


mA 


Standby Power 


<SB1 


CE= V IH ,OE = V IH 




1 


2 




1 


2 


mA 


Supply Current 


'SB2 


CE > V CC -0.2V, OE> V cc -0.2\ 


- 


- 


- 


_ 


0.05 


0.1 


mA 


Operating Power Supply 


'CC2 


CE= K m ,6E = V IL 


- 


1 


2 




0.6 


1 


mA 


Current in Self Refresh Mode 


'CC 3 


CE> V CC -0.2V, 61<0.2V 










50 


100 


nA 


Input Leakage 
Current 


'LI 


K CC =5.5V 

Vin - V SS to V CC 


-10 




10 


10 




10 


nA 


Output Leakage 
Current 


Ilo 


OE= V,„ 

y i/o - V SS t0 V CC 


-10 




10 


-10 




10 


mA 


Output Voltage 


vol 


I L » 21 mA 






0.4 






0.4 


V 


VOH 


lOH' -1 mA 


2.4 






2.4 






V 



■ CAPACITANCE 



Item 


Symbol 


Test Conditions 


typ. 


max. 


Unit 


Input Capacitance 


On 


Vin i 0V 




5 




Input/Output Capacitance 


C l/0 






7 


PF 




Note) This Parameter is sampled and not 100% tested. 



AC CHARACTERISTICS (T a = to +70°C, V CC = SV ±10%) 
AC Test Conditions 

Input Pulse Levels 2.4V, 0.4V 

Input Rise and Fall Times 5ns 

Timing Measurement Level 2.2V, 0.8V 

Reference Level V QH = 2.0V, V 0L = 0.8V 

Output Load 1 TTL and 100pF (including scope and jig) 



Item 


Symbol 


HM65256B-10 


HM65256B-12 


HM65256B-15 


HM65256B-20 


Unit 


min. 


max. 


min. 


max. 


min. 


max. 


min. 


max. 


Random Read or Write Cycle Time 


'RC 


160 




190 




235 




310 




ns 


Static Column Mode Read or Write 
Cycle 


>RSC 


55 




65 




80 




105 




n. 


Chip Enable Access Time 


ice a 




100 




120 




150 




200 


ns 


Address Access Time 


<AA 




50 




60 




75 




100 


ns 


Output Enable Access Time 


'OEA 




40 




50 




60 




75 


ns 


Chip Disable to Output in High Z 


<CHZ 




25 




25 




30 




35 


ns 


Chip Enable to Output in Low Z 


<CLZ 


30 




30 




35 




40 




ns 


Output Enable to Output in Low Z 


IOLZ 


10 




10 




10 




10 




ns 


Output Disable to Output in High Z 


tOHZ 




25 




25 




30 




35 


ns 


Chip Enable Pulse Width 


'CE 


lOOn 


4m 


120n 


4m 


150n 


4m 


200n 


4m 


s 


Chip Enable Precharge Time 


'P 


50 




60 




75 




100 




ns 


Address Set-up Time 


'AS 






















ns 


Row Address Hold Time 


'RAH 


20 




20 




25 




30 




ns 


Column Address Hold Time 


'CAH 


100 




120 




150 




200 




ns 


Read Command Set-up Time 


IRCS 






















ns 


Read Command Hold Time 


<RCH 






















ns 


Output Enable Hold Time 


'OHC 






















ns 


Output Enable to Chip Enable Delay 
Time 


'OCD 






















ns 


Output Hold Time from Column 
Address 


'OH 


5 




5 




5 




10 




ns 


Write Command Pulse Width 


<WP 


25 




25 




30 




35 




ns 


Chip Enable to End of Write 


'cw 


100 




120 




150 




200 




ns 


Column Address Set-up Time 


'ASW 






















ns 



) be continued) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



371 



HM65256B Series 



Item 


Symbol 


HM65256B-10 


HM65256B-12 


HM65256B-15 


HM65256B-20 


Unit 


min. 


max. 


min. 


max. 


min. 


max. 


min. 


max. 


Column Address Hold Time after Write 


'AHW 





- 





- 





- 





- 


ns 


Data Valid to End of Write 


'DW 


20 


— 


20 




25 


— 


30 


— 


ns 


Data In Hold Time for Write 


'DH 






















ns 


Output Active from End of Write 


t OW 


5 




5 




5 




5 




ns 


Write to Output in High Z 


<WHZ 




25 




25 




30 




35 


ns 


Transition Time (Rise and Fall) 


it 


3 


50 


3 


50 


3 


50 


3 


50 


ns 


IXC11CSI1 V-Ultl II Idl 1U L^cidy tunc 


! RFD 


50 




60 




75 




100 




ns 
ns 


Refresh Precharge Time 


tf-p 


30 




30 




30 




30 






Refresh Command Pulse Width for 
Automatic Refresh 


'FAP 


80 


10000 


80 


10000 


80 


10000 


80 


10000 


ns 


Automatic Refresh Cycle Time 


'FC 


160 




190 




235 




310 




ns 


Refresh Command Pulse Width for Self 
Refresh 


'FAS 


10000 




10000 




10000 




10000 




ns 


Refresh Reset Time for Self Refresh 


<FRS 


160 




190 




235 




310 




ns 


Refresh Period 


'REF 




4 




4 




4 




4 


ms 



Notes 
(1) 
(2) 
(3) 
(4) 
(5) 



'CHZ< 'OHZ and 'WHZ are defined as the time at which the output achieves the open circuit conditions. 
'CLZ' Iqlz a "d ! ow are sampled under the condition of 1 7-=5ns, and not 100% tested. 
A write occurs during the overlap of a low CE and low WE. 

If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high impedance state. 
If input signals of opposite phase to the outputs are applied in write cycle, OE or WE must disable output buffers 
prior to applying data to the device and data inputs must be floating prior to OE or WE turning on output buffers. 
Vjff (min) and V 1L (max) are reference levels for measuring timing of input signals. Also, transition times are meas- 
ured between Vju and 



(6) 

(7) An initial pause of 1 00/js is required after power-up followed by a minimum of 8 initialization cycles 



■ TIMING WAVEFORMS 

• Read Cycle No. 1 (CE controlled) 



V 



ddress \/YY\ r 
o~A? AAA/ . 



Add 
A 



Address \/YY\' 
Ab-Au AAA/, 



tit: 



(KC'H 



WE 



7ZZF 



OE 



Dout- 



tci.x 



I OH 



Valid 
Data Out 



tcHX 



HITACHI 

372 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Read Cycle No. 2 (OE controlled) 



CE- 



\ 



Addres 
An-A 



Address YYYV r 
A» -An AAA/ > 



WE 



OE 



Dout- 



UAH 



It KA 



/()«( 



i 



/ok* 



Unix 



//////// ///////77 



Write Cycle No. 1 (OE Clock) 

CE 



Address 
An 



V 



Add 

A. -A 



d A"M>C 



WE- 



™ ////////////// 



Din- 



U>H, 

3x> 



\\\\\\\H 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 3 73 



HM65256B Series - 



• Writ* Cycle No. 2 (OE low fix) 



CE- 



Add 

At 



OE- 



• Static Column Mode Read Cycle 



Address 
A0-A7 



Address 
A8-A14 



Us 



OE 



5 



mUZZETH 



374 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 







• Static Column Mode Write Cycle 



CE 



Address 
A0-A7 



Address 
A8-AU 



(HAH 



Dout 



4 Val 



X 



f u p ~~ ~ — m — 

\ J.TMl 



( Valid Data In) | 



• Automatic Refresh Cycle 



CE- 



/ 


(«FD 


(FC 










fF/tP 


(FP 


(F/tP , 


////////// 


\ 1 


I 




///////// 



• Self Refresh Cycle 



CE- 



X 



IRFD 



« milium k 



tFRS 



V 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



375 



HM6S8128 



131072-word x 8-bit High Speed CMOS Pseudo Static RAM 



The Hitachi HM658128 is a pseudo-static RAM organized as 
131,072-word x 8-bit. HM658128 realizes low power consump- 
tion and high speed access time by employing 1.3/um CMOS 
process technology. 

The HM658128 supports 3 refresh functions: Address Refresh, 
Auto Refresh and Self Refresh. Low power version dissipates 
only 0.5mW (typ.) in Self Refresh Mode and retains the data with 
battery backup for short time. Self Refresh Mode is guaranteed 
only for L-version. 

The HM658128 is pin-compatible with 256k-bit PS RAM and 
static RAM. 

■ FEATURES 

• Single 5V (±10%) 

• High Speed 

o Access Time 

CE Access Time . . . 100/1 20/1 50ns 
o Cycle Time 

Random Read/Write Cycle Time . . . 180/210/250ns 

• Low Power . . . 200mW typ. (Active) 

0.5mW (standby) 

• All inputs and outputs TTL compatible 

• Non Multiplexed Address 

• 512 Refresh Cycles (8ms) 

• Refresh Functions 

Address Refresh 

Automatic Refresh 

Self Refresh (Only for L-version) 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM658128DP-10 
HM658128DP-12 
HM658128DP-15 


100ns 
120ns 
150ns 


600 mil 32 pin 


HM658128LP-10 
HM658128LP-12 
HM658128LP-15 


100ns 
120ns 
150ns 


Plastic DIP 


HM658128DFP-10 
HM658128DFP-12 
HM658128DFP-15 


100ns 
120ns 
150ns 


32 pin Plastic 
SOP 


HM658128LFP-10 
HM658128LFP-12 
HM658128LFP-15 


100ns 
120ns 
150ns 



HM658128P Series 




(DP-32) 



HM658128FP Series 




(FP-32D) 



PIN ARRANGEMENT 



376 



HITACHI 



HFSH fT 




32] Vn 


An|T 




17] An 


Am[I 




30] CS 


Ai.'JT 




29] W K 


At \J 




HjA,, 


A« [6 




27j A« 


A, [7 




26] A. 


A. [J 




|U An 


a, n 




24] OE 


A, [10 




23] Ai. 


A, (n 




22] CE 


a« [TJ 




ID i n, 


1 0.,[l3 




20] 1 0.. 


1 0, \u 




TJ 1 0-. 


1 o^g 




TJ 1 Oi 


Vsa UJ 




Jf] 1 CI, 




(Top View) 




■ PIN DESCRIPTION 


Symbol 


Pin Name 


AO - A16 


Address Inputs 


I/O - 1/07 


Data Input/Output 


RFSH 


Refresh 


CE 


Chip Enable 


OE 


Output Enable 


WE 


Write Enable 


CS 


Chip Select 


v C c 


Power Supply 


Vss 


Ground 



Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM658128 Series 



■ BLOCK DIAGRAM 

H.0 {£ZI 



RFSH O— 



CEO- 



MEMORY MATRIX 
1512*2561*8 



Address L»lch Control 



Timing Pulse Cenerilor 



■ TRUTH TABLE 



CE 


CS at CE going Low 


RFSH 


OE 


WE 


I/O Pin 


Mode 


L 


H 


X 


L 


H 


Low Z 


Read 


L 


H 


X 


X 


L 


HighZ 


Write 


L 


H 


X 


H 


H 


HighZ 




L 


L 


X 


X 


X 


HighZ 


CS Standby 


H 


X 


L 


X 


X 


HighZ 


Refresh*' 


H 


X 


H 


X 


X 


HighZ 


Standby 



Note) *1. Self refresh is guaranteed only for L-version. 
■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage with Respect to V ss 


V T 


-1.0 to +7.0 


V 


Power Dissipation 


P T 


1.0 


w 


Operating Temperature 


Topr 


to +70 


"C 


Storage Temperature 


T stg 


-55 to +125 


°c 


Storage Temperature Under Bias 


Tbias 


-10 to +85 


°c 


■ RECOMMENDED DC OPERATING CONDITIONS (T a = to +70°C) 


Item 


Symbol 


min. 


typ. 


max. 


Unit 


Supply Voltage 


v C c 


4.5 


5.0 


5.5 


V 


Vss 











V 


Input Voltage 


v m 


2.2 




6.0 


V 


Vn. 


-0.5*" 




0.8 


V 


Note) *1. V IL min = -3.0V for pulse width < 10ns. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • 



377 



HM6581 28 Series 



■ DC CHARACTERISTICS (T a = to +70°C, V cc = 5V ± 10%) 



Parameter 


Symbol 


Test Condition 


min. 


typ. 


max. 


Unit 


Operating Power 
Supply Current 


•fee J 


hio f 

'eye = mm - 


- 


40 


75 


mA 


Standby Power 
Supply Current 


hBl 


CE= v lH 

RFSH = V IH 


- 


1 


2 


mA 


Standby Power 
Supply Current 


ISB2 


CE > V cc -0-2V 
RFSH > V cc -0-2V 


- 


100 


200 


MA 


Operating Power 


ICC2 


CE= V IH 
RFSH = 


- 


1 


2 


mA 


Supply Current in Self Refresh Mode* 1 


ICC3 


CE ^ K cc -0.2V 
RFSH ^ 0.2V 


— 


100 


200 


nA 


Input Leakage Current 


•u 


K CC = 5.5V 

ffcl = ^ss to K CC 


-10 




10 


^A 


Output Leakage Current 


Ilo 


OE = K /if 

^//o = Vss to Kcc 


-10 




10 


MA 


Output Voltage 


Vol 


/ 0i = 2.1mA 






0.4 


V 


Vqh 


l OH = -1mA 


2.4 






V 



Note) * 1 . This characteristics is guaranteed only for L-version. 



■ CAPACITANCE (T a = 25°C,/= 1MHz) 



Item 


Symbol 


Test Condition 


typ. 


max. 


Unit 


Input Capacitance 


Cin 


V in = OV 




8 


PF 


Input/Output Capacitance 


C llO 


K //o = 0V 




10 


PF 



Note) This Parameter is sampled and not 100% tested. 



■ AC CHARACTERISTICS (T a = to +70°C, V cc = 5V ± 10%) 
• AC Test Conditions 

Input Pulse Levels 

Input Rise and Fall Times 

Timing Measurement Level 

Reference Level 

Output Load 



Item 


Symbol 


HM658128-10 


HM658128-12 


HM658128-15 


Unit 


min. 


max. 


min. 


max. 


min. 


max. 


Random Read or Write Cycle Time 


tRC 


180 




210 




250 




ns 


Random Read Modify Write Cycle Time 


! RWC 


240 




280 




330 




ns 


Chip Enable Access Time 


'CEA 




100 




120 




150 


ns 


Output Enable Access Time 


'OEA 




30 




40 




50 


ns 


Chip Disable to Output in High Z 


'CHZ 




30 




35 




40 


ns 


Chip Enable to Output in Low Z 


>CLZ 


30 




35 




40 




ns 


Output Disable to Output in HighZ 


'OHZ 




25 




30 




35 


ns 


Output Enable to Output in Low Z 


<OLZ 


5 




5 




5 




ns 


Chip Enable Pulse Width 


'CE 


lOOn 


lM 


120n 


lM 


150n 


lu 


s 


Chip Enable Precharge Time 


'P 


70 




80 




90 




ns 


Address Set-up Time 


'AS 

















ns 


Address Hold Time 


'AH 


30 




35 




40 




ns 


Read Command Set-up Time 


( RCS 

















ns 


Read Command Hold Time 


f RCH 

















ns 


RFSH Hold Time 


*RHC 


15 




15 




15 




ns 


Refresh Command Delay Time (Standby Mode) 


<RCD 




5 




5 




5 


ns 



(to be continued) 



2.4V, 0.4V 
5ns 

2.2V, 0.8V 

V OH =2.0V, Vol =0.8V 
1 TTL and lOOpF (including scope and jig) 



HITACHI 

378 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



HM658128 Series 



Item 


Symbol 


HM658128-10 


HM658128-12 


HM658128-15 


Unit 


min. 


max. 


min. 


max. 


min. 


max. 


Chip Select Set-up Time 


'ess 





- 





- 





- 


ns 


Chip Select Hold Time 


'CSH 


30 


- 


35 


- 


40 


- 


ns 


Write Command Pulse Width 


'WP 


30 


- 


35 


- 


40 


- 


ns 


Chip Enable to End of Write 


! cw 


100 


- 


120 


- 


150 


- 


ns 


Data In to End of Write 


'dw 


25 


- 


30 


- 


35 


- 


ns 


Data In Hold Time for Write 







— 





~ 





— 


ns 


Output Active from End of Write 


'ow 


5 




5 




5 




ns 


Write to Output in High Z 






25 




30 




35 


ns 


Transition Time (Rise and Fall) 


<T 


3 


50 


3 


50 


3 


50 


ns 


Refresh Command Delay Time 


tRFD 


70 




80 




90 




ns 


Refresh Precharge Time 


t pp 


40 


_ 


40 




40 




ns 


Refresh Command Pulse Width for Automatic 
Refresh 


<FAP 


80n 


8u 


80n 


8u 


80n 


OM 


s 


Automatic Refresh Cycle Time 


'fc 


180 




210 




250 




ns 


Refresh Command Pulse Width for Self Refresh 


'FAS*' 


8 




8 




8 




MS 


Refresh Reset Time for Self Refresh 


*RFS*' 


180 




210 




250 




ns 


Refresh Reset Time for Automatic Refresh 


>RFA 

















ns 


Refresh Period (512 cycles) 


*REF 




8 




8 




8 


ns 



Notes: 

(1) r CHZ> f OHZ an d ' WHZ are defined as the time at which 
the output achieves the open circuit conditions under 
the condition of tj - 5ns and not 100% tested. 

(2) tCHZ, tCLZ, *OHZ, tOLZ, tWHZ and tow are sampled 
under the condition of rr = 5ns and not 100% tested. 

(3) A write occurs during the overlap of a low CE and a 
low WE._Write end is defined at the earlier of WE going 
high or CE going high. 

(4) If CE goes low simultaneously with WE going low or 
after WE going low, the outputs remain in high im- 
pedance state. 

(5) If input signals of opposite phase to the outputs are 

■ TIMING WAVEFORMS 
• Read Cycle 



applied in write cycle, OE or WE must disable output 
buffers prior to applying data to the device and data 
inputs must be floating prior to OE or WE turning on 
output buffers. 

(6) V IH (min) and V™ (max) are reference levels for 
measuring timing of input signals. Also, transition times 
are measured between V If f and Vj^. 

(7) An initial pause of lOOjis is required after power-up 
followed by a minimum of 8 initialization cycles. 

(8) After Self Refresh, Auto Refresh should be started with- 
in 15^s. (only for L-version) 

(9) This characteristics is guaranteed only for L-version. 



X 



^ (XXXXXXXXXXXXXXXXXXXXXX wmYXY) 



27L 



V.lid 
Dau Out 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



379 



HM658128 Series - 



• Write Cycle- 1 (OE Clock) 



of 

IFsh" 

Din 



Address 
Ao~ Ait 



X 



7ZZJT 



7ZZZZL 7 ZZZD t 



Kxxxxx xxxx x xx xxxxx xx xx xx x ^mx 



/ 



Z77 



Write Cycle-2 (OE Low Fix) 



cs 



7ZZA 



Add™.. YVY\ ! ~~ 
a.-a„ A/VVV 



^xxxxxxxxxxxxxxxxxxxxxxx^ mx^ 



WE 



KF5TT 



X WWWWWWWWWWWN 1 



7Z 



7? 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Read Modify Write Cycle 



\ 



Address 
A. -A,. 



2Z7T 



r E ZZ7 



M: 



XXXSa /777 //////// 



\ \\\\\ 



3^ 



'/////// 



• Automatic Refresh Cycle 



CE 



RFSH 





IKFD tFC 


trc 








Inco 








(f it? ( 









//////Will 


\ 













• Self Refresh Cycle 



BFSTT 



niiuiim l % 



Note) Self refresh is guaranteed only for L-version. 
• CS Standby Mode 



X 



i 'ess 



///////////////////////////////Z 22 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 381 



HM658128 Series 



SUPPLY CURRENT VS. SUPPLY VOLTAGE ) 



SUPPLY CURRENT VS. AMBIENT TEMPERATURE (1) 



1.3 



S 1.2 

■ 

I ,.1 

z 

- 1.0 



0.7 









Ta=25 1 C 












































4.50 4.75 



5.00 5.25 

Voltage Vcc (V) 



5.50 



1.3 
* 1.2 



I L 1 



I 09 



0.8 









Vcc =5.0V 











































20 40 60 

Ambient Temperature Ta CO 



80 



SUPPLY CURRENT VS. SUPPLY VOLTAGE<2) 



SUPPLY CURRENT VS. AMBIENT TEMPERATURE ( 2 ) 



1.6 



| 

I 1.2 



% 1.0 



0.6 
04 









Ta=25Tj 











































4.50 4.75 5.00 5.25 

Supply Voltage Vcc (V) 



5.50 



1.3 

| 1.2 

1 

| 1.1 

1 l * 

u 

>■ 0.9 

a 

a 

0.8 
0.7 









V CC =5.0V 











































20 40 60 80 

Ambient Temperature Ta ("CI 



SUPPLY CURRENT VS. SUPPLY VOLTAGE(3) 



1.6 



1.2 



Z 1.0 
c 

a 

u 

* 0.8 



0.6 



0.4 









Ta=25X; 











































4.50 



4.75 5.00 5.25 

Supply Voltage Vcc (V) 



5.50 



SUPPLY CURRENT VS. AMBIENT TEMPERATURE (3) 



1.2 
1.0 
0.8 
0.6 



0.4 



Vcc = 5.0V 



20 40 60 

Ambient Temperature Ta (*C) 



80 



382 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM658128 Series 



ACCESS TIME VS. SUPPLY VOLTAGE 



ACCESS TIME VS. AMBIENT TEMPERATURE 




U, 4.50' 



4.75 5.00 5.25 5.50 

Supply Voltage Vcc (VI 




20 40 60 80 

Ambient Temperature Ta (*C) 



STANDBY CURRENT VS. SUPPLY VOLTAGEd) 

1.6 

1 1.4 



STANDBY CURRENT VS. AMBIENT TEMPERATURE (1 ) 



z 1.2 



0.8 



0.4 









Ta = 25r 











































4.5 



4.75 5.0 5.25 

Supply Voltage Vcc (V) 



5.5 



1.6 



! U 



t 

" 0.8 



* 0.6 









Vcc = 5.0V 











































20 40 60 80 

Ambient Temperature Ta CO 



STANDBY CURRENT VS. SUPPLY VOLTAGE(2) 



STANDBY CURRENT VS. AMBIENT TEMPERATURE^) 



1.6 



I 1.2 

z 



t 

tS 0.8 



0.4, 









Ta=25TD 











































4.5 



4.75 5.0 5.25 

Supply Voltage Vcc (V) 



5.5 



1.6 

a 1.4 

I 1.2 
z 

I 1.0 

3 0.8 

"E 

m 0.6 
0.4 









V cc = 5.0V 











































HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



20 40 60 80 

Ambient Temperature Ta t*C) 



383 



HM658128 Series 



LOW LEVEL INPUT VOLTAGE VS. SUPPLY VOLTAGE 



HIGH LEVEL INPUT VOLTAGE VS. SUPPLY VOLTAGE 



1.3 



0.8 
0.7 









Ta = 25t: 











































1.75 5.00 5.25 

Supply Voltage Vcc (V) 



5.50 



1 U 
H 

I 

o 

z 1.2 



■ 

I 1.1 



a 0.9 



0.7 









Ta = 25t 











































4.50 



4.75 5.00 5.25 

Supply Voltage Vcc (V) 



5.50 



HIGH LEVEL OUTPUT CURRENT VS. OUTPUT VOLTAGE 



LOW LEVEL OUTPUT CURRENT VS. OUTPUT VOLTAGE 



1.6 



1 1.4 



~ 1-2 

| 1.0 

Q 

| 0.8 

o 

Ji 0.6 
0.4 

































Ta = 25t 
Vcc = 5.0V 



















1.6 



2 3 4 5 

High Level Output Voltage Vuh (V) 



1.0 
0.8 



0.1 

































Ta = 251C 
Vcc = 5.0V 



















0.2 0.4 0.6 0.8 

Low Level Output Voltage Vol (V) 



HITACHI 

384 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



HM658128 Series 



ACCESS TIME VS. LOAD CAPACITANCE 



1.8 
1 16 




< 0.8 



100 200 300 400 500 

Lead Capacitance CiipF 1 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



385 



HITACHI 



Section 4 





HITACHI 



387 



HM63021 Series 



2048-word x 8-bit Line Memory 



HM63021 is a 2048-word x 8-bit static Serial Access Memory 
(SAM) with separate data inputs and outputs. Since it has an 
internal address counter, no external address signal is required 
and internal addresses are scanned serially. Using five different 
address scan modes, it is applicable to FIFO memories, double- 
speed conversions, 1H delay lines and 1H/2H delay lines for 
digital TV signals. Its minimum cycle times are 28 ns and 34 ns 
each corresponding to 8 fsc of PAL TV signals and NTSC TV 
signals. All inputs and outputs are TTL-compartiable. This device 
is packaged in a 300-mil dual-in-line plastic package. 

Features 

• Five modes for various applications 

• Corresponds to Digital TV system with 4 fsc sampling 

(PAL, NTSC) 

• Decoder signal output pin; Fewer external circuits 

• Asynchronous Read/Write operation; 

Separate address counters for Read/Write 
No Address Input required 

• High Speed; Cycle Time 28/34/45 ns (min) 

• Completely Static Memory; No refresh required 

• 8-bit SAM with separate I/O 

• Low Power; 250 mW typ. Active 

• Single 5 V supply 

• TTL compatible 



Pin Arrangement 



D 1H/2H 


TBC DSC I TBCE 




TBCE DSC TBC 


1H/2H 


D 


M0DE1 








V« 


p 


Read 

Contr 






CLK 


RCLK 


1 


^ 

3 
3 


M0DE2 


RES 


RRES 


MODE3 | RDEC | DEC2 


DinO 
Dinl 
Din2 

DM 

Din4 

Mi 

Din6 
DM 


Li 
CI 
D 
d 
ES 
E 

i 

F 


Input 




oF 


Output 


3 
23] 

22] 

3 
3 
3 
3 
3 


DoutO 
Doull 
Boot! 
Dout3 
Dout4 
Dout5 
Dout6 
Dout7 


WE 


lH 




DEC1 | WDEC | HijhZ 




Write 


H 


WRES 


DS 


DEC3 




h 




Control 


3 


WCLK 


WT 


DEC4 







(Top Vie. ) 



(DP-28N) 



Ordering Information 



Type No. Cycle 



Package 



HM63021P-28 28 ns „„„ . . 

niumiiDii ia 300-mil 28-pin 

HM63021P-34 34 ns p » 

HM63021P-45 45 ns 



HITACHI 

388 Hitachi America, Ltd. » Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63021 Series 



Pin Description 



Pin No. 



1 



4-11 



12 



13 



14 



15 



16 



17-24 
25 



26 



27 



28 



Pin Name 



MO DEI 



RCLK/CLK 



RRES/RES 



Din - Din 7 



WE 



High Z/WDEC/DEC1 



V SS 



WCLK/WT/DEC4 



WRES/DS/DEC3 



Dout - Dout 7 



OE 



MODE3 /RDEC/DEC2 



MODE 2 



Functions 



Mode Input 1 (All Modes) 



Read Clock Input (TBCE, DSC, TBC) 
Clock Input (1H/2H, D) 



Read Reset Input (TBCE, DSC, TBC) 
Reset Input (1H/2H.D) 



Data Inputs (All Modes) 



Write Enable Input (All Modes) 



High Impedance (TBCE, DSC) 
Write Decode Pulse Output (TBC) 
Decode Pulse Output 1 (1H/2H, D) 



Ground (All Modes) 



Write Clock Input (TBCE, DSC, TBC) 
Write Timing Input (1H/2H) 
Decode Pulse Output 4 (D) 



Write Reset Input (TBCE, DSC, TBC) 
Delay Select Input (1H/2H) 
Decode Pulse Output 3 (D) 



Data Outputs (All Modes) 



Output Enable Input (All Modes) 



Mode Input 3 (TBCE) 

Read Decode Pulse Output (TBC) 

Decode Pulse Output 2 (1H/2H, D) 



Mode Input 2 (All Modes) 



Power Supply (+5V) (All Modes) 




Mode Table 



Mode Signals 



MODE1 


MODE2 


MODE3 


Mode 


Application Example 


H 


H 


H 


Time base compression/expansion (TBCE) 


Picture in Picture 


H 


H 


L 


Double speed conversion (DSC) 


Non interlace 


H 


L 


_ *1 


Time base correction (TBC) 


Time Base Corrector 


L 


H 


_ *l 


1H/2H delay (1H/2H) 


Vertical filter 


L 


L 


_ *1 


Delay line (D) 


Delay line 



Note) •! . Decoder Output Signal (RDEC, BTC2) 



Absolute Maximum Ratings 



Parameter 


Symbol 


Rating 


Unit 


Voltage on Any Pin relative to Vgg 


V T 


-0.5 *' to +7.0 


V 


Power Dissipation 


P T 


1.0 


W 


Operating Temperature 


Topr 


to +70 


°C 


Storage Temperature 


Tstg 


-55 to +125 


4 C 


Storage Temperature under bias 


Tbias 


-10 to +85 


°C 


Note) »1. -3.5V for pulse width g 10 


ns 







HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 389 



HM63021 Series 
Block Diagram 



RCLK/CLK- 
RRES/RES- 
WCLK/WT- 
WRES/DS - 
MODE) - 
MODE2 
MODE3 - 




Timing 
Logic 





\ 




Matrix 


WriK 








Ro* 








Decoder 


y 


1128x64) | 


1128x64) 



Read Column Switch 



Read Column Decoder 



Read 
Row 
Decoder 



Address 
Decoder 



-Cp Read Address 
Control 



DoutO Doul7 



OE 



1900, 1810) 



-RDEC 
-DEC! 
-DEC2 



-DEC4 



Parameter 


Symbol 


min 


typ 


max 


Unit 


Supply Voltage 


v CC 


4.5 


5.0 


5.5 


V 


v S s 











V 


Input Voltage 


Vm 


2.4 




6.0 


V 


V,L 


-0.5*1 




0.8 


V 



Note) 



-3.0V for pulse width < 10 ns. 



390 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



DC and Operating Characteristics (Ta= to +70°C, V 


CC~ 


5V± 10% 


,v ss = 


0V) 


Parameter Symbol 


min 


typ*' 


max 


Unit 


Test Condition 


Input Leakage Current 1 I L i 1 






10 


M 


V CC = 5.5 V 

Vin = V ss to V CC 


Output Leakage Current 1 Ilo 1 




- 


10 


mA 


OE= V, H 

v out = V ss to V C c 


Operating Power Supply Current Ice 




50 


90 


inA 


Min. cycle, lout = mA 


Vol 






0.4 


V 


I OL = 8 mA*2, Dout to Dout 7, 
DEC Output pin 


Output Voltage 

VOH 


2 4 






V 


!oH = "4 mA, Dout to Dout 7 
pin 


2.4 






V 


•OH 1 m/\, ur.L t_*uipui pm 


Notes) M. Typical values are at VCC = 5 V, Ta = 
*2. IOL = 6mA for 45ns version. 


25°C and for reference only. 




Capacitance (Ta = 25°C,/= 1 .0 MHz) 












Parameter Symbol 


min 




typ 


max 


Unit Conditions 


Input Capacitance Cin 








6 


pF Vin = 0V 


Output Capacitance" 2 Cout 








9 


pF Vout = 0V 



Notes) *1 . This parameter is sampled and not 1 00% tested. 
•2. 13, 15 - 24, 26 pin 

AC Characteristics (V cc = 5V ± 10%, Ta= to +70°C, unless otherwise noted.) 
• AC Test Conditions 

Input and Output timing reference levels: 1.5V 

Input pulse levels: V ss to 3V 

Input rise and fall times: 5 ns 



HM63021 -28/34 



DEC Output Load 

O +5V 



Dout Output Load (A! 

P*5V 



Dout Output Load (B) 



DEC O- 



Dout O— 



~ 30pF « 1 



*1 

' 30pF 




frr 



77T 



+ 1 Including scope and jig. 



HM63021-45 



DEC Output Load 



Dout Output Load (A) 



Dout Output Load (B) 
( toLZ. tonz ) 



DEC O- 



Dout O- 



777 



Dout O- 



294H 




777" 

1 Including scope and jig 



777 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 391 



HM63021 Series 



Read Cycle 



Parameter 






HM63021-28 


HM63021-34 


HM63021-45 






Symbol — 


min 


max 


min 


max 


min 


max 


— Unit 


Read Cycle Time 




>RC 


28 


- 


34 


- 


45 


- 


ns 


Read Clock Width 




tRWL 


10 


- 


10 


- 


15 


- 


ns 




tRWH 


10 


- 


10 


- 


15 


- 


ns 


Access Time 




'AC 


- 


20 


- 


25 


- 


30 


ns 


FlpmHp Ontniif Arpp«« Ximp 
UCLUUC VJUljJUl .*\L.l-LSN 1111IC 


(fall) 


'DAI 


- 


20 


- 


25 


- 


30 


ns 


(rise) 


'DA 2 




40 




50 




60 


ns 


Output Hold Time 




'OH 


5 




5 




5 




ns 


Decode Output Hold Time 


(fall) 


'DOH1 


5 




5 




5 




ns 


(rise) 


'D0H2 


5 




5 




5 




ns 


Output Enable Access Time 




tOE 




20 




25 




30 


ns 


Output Disable to Output in 


HighZ 


tOHZ 





15 





20 





25 


ns 


Output Enable to Output in Low Z 


'OLZ 


5 




5 




5 




ns 


Write Cycle 


Parameter 






HM63021-28 


HM63021-34 


HM63021-45 






Symbol — 


min 


max 


min 


max 


min 


max 


— Unit 


Write Cycle Time 




'WC 


28 




34 




45 




ns 


rn»C(lH/2H Mode) 


56 




68 




90 


- 


ns 


Write Clock Width 




'WWL 


10 




10 




15 




ns 




'WWH 


10 




10 




15 




ns 


Input Data Setup Time 




'DS 


5 




5 




7 




ns 


Input Data Hold Time 




'DH 


5 




5 




7 




ns 


WE Setup Time 




'WESL 


5 




5 




7 




ns 




tWESH 


5 




5 




7 




ns 


WE Hold Time 




'WEHL 


5 




5 




7 ~ 


ns 




tWEHH 


5 




5 




7 




ns 


WT Setup Time 




'WTSL 


5 




5 




7 




ns 




'WTSH 


5 




5 




7 




ns 


WT Hold Time 




'WTHL 


5 




5 




7 




ns 




tWTHH 


5 




5 




7 




ns 


Reset Cycle 




















Parameter 




HM63021-28 


HM63021-34 


HM63021-45 




Symbol — 


min 


max 


min 


max 


min 


max 


— Unit 


Reset Setup Time 




'RES 


8 




9 




10 




ns 


Reset Hold Time 




tREH 


5 




5 




7 




ns 


Clock Setup Time Before Reset 


(REPS 


8 




9 




10 




ns 


Clock Hold Time Before Reset 


'REPH 


5 




5 




7 




ns 



Mode Description 

• Time Base Compression/Expansion Mode 

This mode turns HM63021 into a 2048-word x 8- 
bit FIFO memory with asynchronous input/ 
output. The HM63021 provides 2 clocks 
(RCLK, WCLK) and 2 resets (RRlS, WRES), 
one each for read and write. The internal address 
counters increment by 1 address clock and are 



reset to address 0. A write-inhibit function of 
HM63021 stops writing automatically after the 
data has been written into all addresses to 
2047. The write-inhibit function is released by 
reset using WRES, and the HM63021 restarts 
writing into address 0. 

• Double-Speed Conversion Mode 

This mode turns HM63021 into a 1024-word x 



392 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



8-bit x 2 memory with asynchronous input/ 
output. It is used for generating non-interlaced 
TV signals. When the original signal and the 
interpolated signal (1 field delay) of interlaced 
signals are input to the HM63021, multiplexed 
per dot, it outputs non-interlaced signals for each 
line. 8 fsc should be input to RCLK and WCLK. 
A standard H synchronizing signal and a non- 
interlace H synchronizing signal are input to 
WRES and RRES respectively. A write-inhibit 
function is provided in this mode, making it 
applicable to PAL TV, where extra data 
(1135-1024= 111 bits) is ignored. 

• TBC Mode 

This mode turns HM63021 into 2048-word x 
8-bit FIFO memory with asynchronous input/ 
output. The HM63021 provides 2 clocks 
(RCLK, WCLK) and 2 resets (RRF5, WRES), 
one each for read and write. The internal address 
counters increment by 1 address at each clock 
and are reset to address 0. The internal address 
counters return to address after they reach 
address 2047. The HM63021 outputs a write 
decode pulse from WDEC, synchronizing it with 
address 2047 in the write address counter, and 
read a decode pulse from RDEC, synchronizing 
with address 2047 in the read address counter. 
Using these pulses, the memory area can be ex- 
tended easily (multiple-HM63021s can be used 
with ease). 

• 1H/2H Delay Mode 

This mode turns HM63021 into a 1024-word x 
8-bit x 2 delay line with synchronous input/ 
output. Delay time is defined by the reset period 

(1) Read after Write (3 bits delay) 



HM63021 Series 

of RES. Since the HM63021 outputs a 901 
decode pulse (DEC1) and a 910 decode pulse 
(DEC2), connecting DEC2 to FHE3, for example, 
outputs 1H- and 2H- delayed signals alternately 
at a 8- fsc cycle when the original signal is input 
at a 4- fsc cycle. A write-inhibit function is pro- 
vided in this mode, making it applicable to PAL 
TV, where extra data (1135-1024 = 111 bits) is 
ignored. 

• Delay Line Mode 

This mode turns HM63021 into a 2048-word x 
8-bit delay line with synchronous input/output. 
Delay time (3 to 2048 bits) is defined by the 
reset period of RES. The delay is 2048 bits 
when RES is fixed High. Signals delayed by 910 
bits to 1135 bits for example, can be easily ob- 
tained without external circuits by just connect- 
ing selected decoded pulses on DEC1 - DEC4 to 
RES. 

Notes on Using HM63021 

• Hitachi recommends that pin 13 (high im- 
pedance) should be fixed by pulling up or down 
with a resistor (of several kfi) in TBC or DSC 
mode. 

• Hitachi recommends that the mode signal input 
pins and DS pin should be fixed by pulling them 
up or down with a resistor (of several kfi). 

• Data integrity cannot be guaranteed when mode 
is changed during operation. 

• When a read address coincides with a write 
address in TBCE, TBC or DSC mode, the data is 
written correctly but it is not always read 
correctly. 



-0 




Wrile Cycle 



Read Cycle 



lilieemin 



(2) Write after Read (2048 bits delay) 



RCLK 




Wrile Cycle 



Re.d Cycle 



I SOns 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 3 93 



HM63021 Series 



At power on, the output of the address counter 
is not defined. Therefore, operations before the 
system is reset cannot be guaranteed, and decode 
signal output is not defined until after the first 
reset cycle. 

The decode signal is latched by a decode output 
latch circuit at the previous address of the in- 
ternal counter address and is output synchron- 
ized with the next address. For example, WD EC 
in TBC mode is latched at write address 2046 
and is output at write address 2047. If a write 
reset is performed on address 2047 at this time, 



the write address becomes and WDEC is out- 
put. 

The same operation is performed in other modes. 

In the reset cycle, the input levels of WRES, 
RRlS, RE5 are raised to satisfy f/j eh • and are 
fixed high until t RE PH in the next pre-reset cycle 
is satisfied. The rise timings of the reset signals 
(RES; WRES, RRES) are optionals provided that 
the tfjsps specification is satisfied. The timings 
at which RES, WRES, and RRES fall after pre- 
reset are also optional, provided that the tREPH 
and f/jfs specifications are satisfied. 



CLK 



• Hitachi recommends that t m (time between 
mode set and the first cycle (Pre-reset)) should 

( 1 ) TBCE, TBC, DSC and Delay Line Mode 



be kept for 2 cycle time (56ns / 68ns / 90ns) or 
more while the power supply is on. 



wcu 

(CLK) 



WRES 
(RES! 





Mode 


Pre 

reset 1 


Reset 




xxxw 


Valid 
























V / 




////A 


'//////////////A 


' v 










xxxxx 1 




00000000 


[ Valid ] 


l 



394 



HITACHI 

Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63021 Series 



(2) 1H /2H Delay Mode 



CLK 



wwwwwwwv 



tzzzlwzzzzzzzzzzzzzwzzzzz 



s 



Note : When mode pins are fixed with V CC .GND in mode set 
while the power supply is on, t m spec is not needed. 















Decode Signal 










When internal address counter reaches the specified address as shown below, decode outputs become low. 


Mode 


Pin 

No. 


Pin 
Name 


Internal Address 
counter 


Timing of the 
Output Signal 


Operation 


TBC 


13 


WDEC 


Write 2047 


After Write 2047 


Completion of Writing on all bits is detected. 


26 


RDEC 


Read 2047 


Output of 2046 


Completion of Reading from all bits is detected. 


1H/2H 


13 


DEC1 


Read 900 (2H) 


Output of 900 (1H) 


By inputting this signal to pin #3, 901/1802-bit 
delay output is obtained. 


26 


DEC2 


Read 909 (2H) 


Output of 909 (1H) 


By inputting this signal to pin #3, 910/1820-bit 
delay output is obtained. 








Read 900 


Output of 899 


By inputting this signal to pin #3, 901-bit delay 
output is obtained. 




13 


DEC1 


Read 1810 


Output of 1809 


By inputting this signal to pin #3 after the 
frequency of DEC1 is devided into two, 1811-bit 
delay output is obtained. 


Delay 
line 






Read 909 


Output of 908 


By inputting this signal to pin #3, 910-bit delay 
output is obtained. 


26 


DEC2 


Read 1819 


Output of 1818 


By inputting this signal to pin #3 after the 
frequency of DEC2 is devided into two, 1820-bit 
delay output is obtained. 




16 


DEC3 


Read 1134 


Output of 1133 


By inputting this signal to pin #3, 1135-bit delay 
output is obtained. 




15 




Read 1125 


Output of 1 1 24 


By inputting this signal to pin #3, 1126-bit delay 
output is obtained. 



Note) When counter is reset by Reset Signal (RRES, RES, WRES), address becomes 0. 
Write-inhibit Function 

When internal address counter is as follows, writing is inhibited automatically for the next cycle. The write- 
inhibit function is cancelled by reset through WRES or RES. 



Mode 



Write-inhibit Function 
(internal counter address) 



TBCE 



Write-inhibit after address 2047 



DSC 



Write-inhibit after address 1023 x 2 



TBC 



No function 



1H/2H 



Write-inhibit after address 1023 



D 



No function 



Note) When address counter is reset by WRES or RES, address becomes 0. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



395 



HM63021 Series 



Read Reset Cycle (TBCE, TBC Modes) 



"Y 



— n l Cycle 



/ \ r 



///////// { 



Douf' •' (i 



\ r 




zzzzzzzzzzzzzzzzzz 



Notes) •}. The read address counter is reset at the first falling edge of RCLK after RRES f alls, me eting the specifications 
of tREPS and 'REPH- and *' is not reset at the next falling edge of RCLK even if RRES is kept low. 
When tREg. *REH. 'REPS. and 'REPH cannot meet the specifications, the reset operation is not guaranteed. 
*2. Outpu t is fro m the read address of the previous cycle. 

*3. When RRES is fixed high, the data at the read address counter is reset after the data of address 2047 is output, 
and the same operation restarts. 

Write Reset Cycle (TBCE, TBC Modes) 



Did 



- j n-1 Cycle | 1 n Cycle Firsl Cycle U— Second Cycle -4- | Third CydT 



^ ■ <///////////////////, 



Note) The write address counter is reset at the first falling edge of WCLK a fter WR ES fall s, meeting the specifications of 
tREPS a " d 'REPH. an d '« •» not reset at the next falling edge of WCLK even if WRES is kept low. 
When Ires. <REH, 'REPS- and 'REPH cannot meet the specifications, the reset operation is not guaranteed. 



HITACHI 

396 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM63021 Series 



Reset Cycle (DSC Mode) 



* 1, * 3. * 4 
WRES ~~ 



*///////////* 



£_Jzzz 



RCLK 



*2. *3, »4 



Z7 



unnm 



Tl7ZL1J-\ 



1 



X (Bl) Y <B2> Y < B3 > )l( < A0 ' %. < A1 > X < AZ ' X < A3 > )fe <»> }fe <B1> X <B2) X 



Reset Timing 1 



Reset Timing 2 



Notes) *1. The write address counter is reset at the first falling edge of WC LK afte r WRES falls, m eeting the specifications 
of tfiEPS anti { REPH' an<1 is not resct at tne next falling edge of WCLK even if WRES is kept low. 
When t RE $, t RE pf, t RE pg, and t RE pff cannot meet the spe cificati ons, the rese t operation is not guaranteed. 

*2. The read address counter is reset at the first falling edge of RCL K after RRES f alls, me eting the specifications 
of t RE pg and t RE pjj, and it is not reset at the next falling edge of RCLK even if RRES is kept low. 
When t RE $, t RE fj, t RE ps an d tREP H cannot meet the specifications, reset oper ation is n ot guar anteed. 

•3. When t REPH , t RESi t REH (WRES to WCLK), or t REPS , t REPH , t RES , t REH (PRES to RCLK) cannot meet 
the specifications, the output of video signal A is not guaranteed. (Reset Timing I). 

*4. When tREPS (WRES to RCLK), or tR£S> tREH. tREPS- tREPH (PRES to RCLK) cannot meet the specifica- 
tions, the interpolation signal B is not guaranteed. (Reset Timing II). 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 397 



HM63021 Series 

Reset Cycle (1H/2H Mode) 



■ [Address ljAddress Address 
nes " I lOi lHiOutpulJlOlZH Oulputll lnpui 



CLK 
(8f,e) 



«1 

NT 

ItU) 

_ *2 



WE 



mm 



nr 



2H 1H 



Jo* ^'o* Jo* 

2H 1H Til I" 

I WESL I WtHL 



\ r 



(Hi«h> or (Low) 



Notes) *1. WT is the input during half cycle of CLK, meeting the specifications of fHTSZ,. 'HTHL> f HTSA/. and t WTHH' 

Data is written when WT is low. Reset is possible when WT is hig h. 
*2. Read address counter is reset at the first falling edge of CL K afte r RES falls, meeting the specifications of 

r REPS and t REPH< and '* ' s not reset at the next falling edge of CLK even if RES is kept low. 

When tRjrs, tRgH, tj^EPS> and IrePH cannot meet the specifications, the reset operation is not guaranteed. 
*3. When DS is fixed h igh 1 H output data is delayed by n bits and 2H output data is delayed by 2n bits where 2n 

is the reset cycle of RES. 

When DS is fixed low, 1H output data is delayed by n-5 bits and 2H output data is delayed by 2n-5 bits. 



HITACHI 

398 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Reset Cycle (D Mode) 



CLK 



WE 



7777/7 , 



'-^////////////////////////// 



2X 



r\ r\ r\ 



xxx (»-2> XXX XX* <n> xXX io) XXX 111 XXX 12 



















'on 




( '"' aa) 




f (1) ) 



Note) *1. The read address counter is reset at the first falling edge of CL K" aft er RES falls , meeting the specifications of 
*REPS and <REPH. and >' is not re s et at the next falling edge of CLK even if RES is kept low. 
When tR£s, tp,£H. 'REPS. and *REPH cannot meet the specifications, the reset operation is not guaranteed. 



Write Enable (TBCE, DSC, TBC, D Modes) 



WCLK' 2 

ICLK 



WE*' 




- | nCyck U- | n^lCytlt M - | i,»2Cyclt | 4 f" n + 3 Cycle \ 4 \ n + 4Cyck 



Dm 



Notes) *i. When t\vEHL. l WESH. *WEHH. and *WESL cannot meet this specifications, the write enable operation is not 

guaranteed. 

*2. In the delay line mode, CLK takes the place of WCLK. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, GA 94005-1819 • (415) 589-8300 3 99 



HM63021 Series 

Write Enable (1H/2H Mode) 



sc. ^ m 



WE'l ~\ f 



wrmi 



' WISH ■ WIHH , 

¥/////¥ i \mf 



Note) *1. When t\yj-SL> 'WTHL' *WEHL- an<1 'WEHH cannot meet the specifications, the write enable operation is not 
guaranteed. 



Decode Output (TBC, D Mi 



1 



CLK* 1 
WCLK 
RCLK 



DEC* 2 



Notes) »1, In TB C mode, W CLK or RCLK t akes t h e place of CLK . 

*2. DECTis WD EC or RDEC in TBC, DEC1, DEC2, DEC 3 or DEC4 in D mode. 



Decode Output (1H/2H Mode) 



CLK 



WT*' 



BSE 



W ^ z 



Note) *1. When t\VTSL. ( WTHL. *WTSH. and 'WTHH cannot meet the specifications, the decode output operation is not 
guaranteed. 



HITACHI 

400 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Output Enable (All Modes) 



D««l 



Note) *1 . Transition of toHZ an< ^ *WLZ is measured ±200 mV from steady state voltage with Output Load B. 
This parameter is sampled and not 100% tested . 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 401 



HM53051P 



• An Application Note is available for this device, contact your local Hitachi representative. 
262144-word x 4-bit Frame Memory 

HM53051P is a 262,144-word x 4-bit frame memory, using the 
most advanced 1.3Mm CMOS processes. It performs serial access 
by an internal address generator. 

It offers a high-speed cycle time of 45ns or 60ns (min). As 
input data and output data can be written or read in any cycle, 
synchronized with a system clock, and the delay between data 
read/write operations is freely settable. Y/C separation and 
frozen pictures can be realized easily in 4fsc NTSC digital TV or 
VCR systems. Also, it enables random access in 32-word x 4-bit 
data block. With this function, picture in picture or a multi- 
plexed picture can be displayed with ease. 
Features 

• 262,144-word x 4-bit serial access memory 

• Organized with dual ports 

Serial input x 4-bit 
Serial output x 4-bit 

• High Speed 

Read/Write Cycle Time: 45ns/60ns (min) 
Access Time: 35ns/40ns (max) 

• Semi-synchronous Read/Write Cycle 

• Low Power 

Active: 200m W (typ) 

• Random Access in 32-word x 4-bit blocks 

• External Refresh Control is unnecessary 
Ordering Information 




Pin Arrangement 





Doul2 | 1 




18 | Vss 


Dout3 | 2 




17 | Dou.ll 


OE [IT 




16 | DoutO 


TAS [T^ 




15 | SAD 


CLK [T| 




~U~| SAS 


CGW | 6 




13 | CGl 


Din3 | 7 




WE 


Din2 | 8 




11 1 DinO 


vr. \jr 






(Top View) 



Pin Description 



Type No. 


Cycle Time 


Package 


Pin Name 


Function 


HM53051P-45 


45ns 


300 mil 18-pin 


Din 


Data Input 


HM53051P-60 


60ns 


Plastic DIP 


Dout 


Data Output 



Block Diagram 



OE 



Output Enable 



External 
Address 
Register 



Address 
Counter 

R & 



Read/ Write/Refresh 



rV 



Row 
Decoder 



Memory Array 

262.144 X 4 



Column Decoder 




6 6 6 6s 

OE DoutO Dout2 DinO Din2 WE 

Doutl Dout3 Dinl Din3 



TAS 



Transfer Address Strobe 



CLK 



System Clock 



CGW Clock Gate (Write) 
CGR Clock Gate (Read) 



SAD 



Serial Address 



SAS 



Serial Address Strobe 



WE 



Write Enable 



HITACHI 



-HM53051P 



Functional Description 

Serial access memory with I/O separated 

Read cycle and write cycle of HM53051 can be 
operated independently synchronized with a system 
clock. It realizes time compression or expansion for 
picture in picture in digital TV, for example. 



• Write cycle by CGW 

Write data are taken in at the falling edge of the 
system clock CLK when CGW is low. If CGW is 
high, HM53051 does not enter write cycle (cycle 
time is defined by system clock cycle time). Time 
is compressed easily with CGW. 



~l I L 



i i i i i r 



• Read Cycle by CGR 

Read data is output at the falling edge of the system 
clock CCK when CG~E is low. If CG~FT is high, 
HM53051 does not enter read cycle (cycle time is 



defined by system clock time), 
is realized easily with CGR. 



Time is expanded 




Random Access 

The HM53051 is also capable of random access by 
serial address input, SAD. Random access by the 
unit of 32-word x 4-bit is performed, when TAS is 
low after read address (ARO — AR12), write address 
(AWO - AW12) and mode setting flags, "RT (Read 



Flag), WF (Write Flag) and MT (Mode Flag) are i 
into by SAD with synchronous SAS. In order to 
output data continuously, the address specified by 
SAD increments automatically. 




Mode Programming 

Operation mode in HM53051 is programmed by the combination of SAD 5-bit. 



MF 


WF 


W 


AWO 


ARO 


Mode 











X 


X 


Write/read address asynchronous transfer 








1 


X 


X 


Write address asynchronous transfer 





1 





x 


X 


Read address asynchronous transfer 





1 


1 


X 


X 












X 


X 


Write/read address synchronous transfer 







1 


X 


X 


Write address synchronous transfer 




1 





X 


X 


Read address synchronous transfer 




1 


1 


1 


1 


System reset 




; 
i 


; 

1 


: 

1 




1 




Inhibit 



Note) x means Don't care. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



403 



HM53051 P 

Read/Write Address Asynchronous Transfer Mode 
• Read address asynchronous transfer mode 

(1) Read address asynchronous transfer mode (1) (CGR: Low) 



CLK 
TAS 

CGR 
Dout 




1 f 







Add AR . Add AR + 1 



Note) The data block at read address AR, specified by SAD, is output starting from the 32-nd system clock after the 
of TAS. 

(2) Read address asynchronous transfer mode (2) (CGR: High) 



CLK 
TAS 
CGR 
Dout 



Add AR 



Notes) *1. The data block at read address AR, specified by SAD, is output starting from the 32-nd system clock after 
th e falli ng of TKS. 

*2. If CG"K is turned to low after 33-r d cloc k fro m the falling edge of TA~S, the data at read address AR (D2, D3, 
D4 . . .) is output with synchronous CLK while CGR is low. 

• Write address asynchronous transfer mode 

( 1 ) Write address asynchronous transfer mode ( 1 ) (CGW : Low) 



CLK 



TAS -| f 




CGW 

Add AW AddAW + 1 Add AW + 2 



Note) T he dat a block at write address AW, specified by SAD, is taken in starting from the 1-st clock after the falling edge 
ofTSS. 



(2) Write address asynchronous transfer mode (2) (CGW; High) 




Note) If CGW is turned to low after falling of TAS, the data block at write address AW is taken in with synchronous CLK. 



HITACHI 

404 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Read/Write Address Synchronous Transfer Mode 

• Read address synchronous transfer mode 



64 65 66 




U Add ARN — U 




Note) When TAS turns to low, the data block at read address AR, specified by SAD, is output after the data block at the 
present read address ARN, and the next address ARN+1 is put out. 



• Write address synchronous transfer mode 



CLK 
TAS 

CGW 
Din 



n n + 1 31 32 33 1 S n g 32 




Add AW 



Note) When TAS turns to low, the data block being written is taken into write address AW. 
System Reset Mode 

System reset mode is the same as read/write address asynchronous transfer mode except that read/write 
address are reset to 0. 

• System reset by SAD 

Note) System reset mode starts when MF, WF, RF, AWO, and ARO are all high. 

• System reset by SAS and TAS 




Note) System reset mode starts when both SAS and TAS are low at the falling edge of the CLK. 
• 1 field delay 

Note) Field-delayed data is output, when CGR and CGW turn to high before the system reset at the beginning of every 
field, and turn to low simultaneously after the 33rd clock from the system reset. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM53051P 



Notes on Using HM53051 

• Input/output data of 32 words is not written or 
read in read/write address asynchronous transfer 
mode or during system reset. The data is written 
or read out in blocks of 32-word x 4-bit. Input 
data of less than 32 words is not written in write 
address asynchronous transfer mode or during 
system reset. When asynchronous read address 
transfer mode or system reset mode is activated, 
output from the current data block will 
continue. When output data from the current 
data block is finished, the next data block is not 
read out if it has less than 32 words. 



Input data is not read out immediately. The data 
(32 word x 4-bit) is written into the memory 
array in the next 32 cycles after it is taken in. 
The data can be read out only after writing to 
the memory array is completed. If read address 
transfer mode is programmed after the 33 word 
clock from on input data block, new data can be 
read out. If this mode is programmed before the 
33 word clock, new data or old data is output. 



(1) Read/write address asynchronous transfer mode 



CLK 
cycle 



1 2 3 



1 2 3 



1 2 3 



1 2 3 



(Write Address 
AN) 



(Read Address 

AN) 



Din of 
Address AN 



Writing on 
Address AN 



Reading from 
Address AN 



Dout of 
Address AN 



(2) Read/write address synchronous transfer mode 



Din 



Dout 





1 2 3 • ■ • 


32 


1 2 3 ■ ■ ■ 32 


1 


2 3 ■ ■ ■ 32 1 2 3 ■ ■ ■ 32 
















Writing on 
Address AN 






' Write Address 
AN) 






( Read Address 
AN) 






Din of 
Address AN 







. . , t u Dout of 

Dout of Reading from Address AN Address 

Address AR | _ Dout of Address AR 1 J_ AN 




HM53051P 



Mode programming 

Do not reprogram read address transfer mode 
before a read operation of the previous read 
address transfer mode or system reset mode is 
completed. If it is reprogrammed during a read 
operation, address becomes invalid, and the 
device may malfunction. 



Do not reprogram write address transfer mode or 
system reset mode before a write operation of 
the previous write address transfer mode or 
system reset mode is completed. If it is repro- 
grammed during a write operation, address 
become invalid, and the device may malfunction. 



(1) Read address asynchronous transfer mode 



CLK 
cycle 



1 2 3 



Uout 



Read Address AN! 



Reading from 
Address AN 



'Read Address AM) 



Reading from 
Address AM 



Dout of 
Address AN 



Doul of 
Address AM 



(2) Read address synchronous transfer mode 



CLK 


1 | 2 | 3 | • ■ | 32 


1 | 2 | 3 | • • ■ | 32 


1 1 2 1 3 1 ••• 1 32 


, | 2 


cycle 


1 1 




TAS 


(Read Address AN) 




u 

(Read Address AM) 














Dout 





















Address AN 


Address AN 


Address AM 









(3) Write address asynchronous transfer mode 



CLK 
cycle 



Wrile Address AN J 



Din of 
Address AN 



1 2 3 



32 1 2 3 



W ruins on 
Address AN 



I Write Address AM 



Din of 

Address AM 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 4 °7 



HM53051P 



(4) Write address synchronous transfer mode 



CLK 



(Wrile Address AN I 



Writing on 

Address AN 



(Wrile Address AMI 



Din of 

Address AM 



• Addresses must be set by read and write address 
asynchronous transfer or system reset 100/^s 
after power on. Before an address can be set. 

Absolute Maximum Ratings 



32 CLK initialization cycles or more are re- 
quired. 



Parameter 




Symbol 


Rating 




Unit 




Voltage on Any Pin Relative to Vgs 


V T 


-1.0 to +7.0 


V 




Power Dissipation 




P T 


1.0 




W 




Operating Temperature 




Topr 


to +70 




"C 




Storage Temperature 




Tstg 


-55 to +125 




"C 




Storage Temperature (under bias) 


Tbias 


-10 to +85 




°C 




Recommended DC Operatir 


ig Conditions (Ta 


= to +70°C) 










Parameter 


Symbol 


min typ 


max 


Unit 




v C c 


4.5 5.0 




5.5 


V 




Supply Voltage 


v SS 










V 




Input Voltage 


VlH 


2.7 




6.5 


V 






VlL 


-0.5" 




0.8 


V 





Note) *1. -3.0V for pulse width g 10ns. 












DC and Operating Characteristics (Ta = to +70°C, V cc = 5V ± 10%, V 


ss = 0V) 








Parameter 


Symbol 


Test Conditions 


min 


typ 


max 


Unit 


Operating Power Supply Current I C c 


Min. cycle, 
lout = mA 




40 


60 


mA 


Input Leakage Current 


Ili 


V C c = 5.5 V 
Vin = V ss to V CC 


-10 




10 


uA 


Output Leakage Current 


Ilo 


OE = V IH 

Vout = V ss to V cc 


-10 




10 


kA 


Output Voltage 


Vol 


I L = 4.2 mA 






0.4 


V 


VOH 


'OH = _2 mA . 


2.4 






V 


Capacitance (Ta = 25°C, f = 


1.0 MHz) 












Parameter 


Symbol 


Test Conditions 


min 


typ 


max 


Unit 


Input Capacitance 


Cin 


Vin = 0V 






5 


PF 


Output Capacitance 


Cout 


Vout = V 






7 


pF 



Note) This parameter is sampled and not 100% tested. 



408 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



AC Characteristics (V cc = 5 V ± 10%, Ta = to +70°C) 
AC Test Conditions 

• Input and output timing reference levels: 1 .5 V 

• Input pulse levels: V ss to 3 V 

• Input rise and fall times: 5 ns 

• Output Load: 2 TTL + 50 pF 

(Including scope and jig) 



HM53051-45 HM53051-60 
Parameter Symbol : ; Unit 







nun 


max 


min 


max 




System Clock Cycle Time 


'CC 


45 


300 


60 


300 


ns 


CLK Pulse Width 


'CL 


15 


_ 


15 


_ 


ns 


tCH 


15 


__ 


15 


__ 


ns 


Access Time from CXK 


'AC 


_ 


35 


_ 


40 


ns 




Output Hold Time 


'OH 


5 


_ 


8 


_ 


ns 


Output Enable Access Time 


'OEA 


_ 


25 


_ 


30 


ns 


Output Enable to Output in Low Z 


'OLZ 


5 


_ 


5 


_ 


ns 


Output Disable to Output in High Z 


'OHZ 





20 





20 


ns 


CTJR Setup Time 


'GRS 


15 


_ 


15 


_ 


ns 


CUR" Hold Time 


'GRH 


5 


_ 


5 


_ 


ns 


CGW Setup Time 


'GWS 


15 


_ 


15 




ns 


CGWHold Time 


>GWH 


5 


_ 


5 




ns 


Write Command Setup Time 


'WCS 


15 




15 




ns 


Write Command Hold Time 


<WCH 


5 




5 




ns 


Data Input Setup Time 


'DS 


15 




15 




ns 


Data Input Hold Time 


'DH 


5 




5 




ns 


SAS Cycle Time 


<SC 


45 




60 




ns 


SAS Pulse Width 


'SL 


15 




15 




ns 


'SH 


15 




15 




ns 


Serial Address Setup Time 


'SAS 


15 




15 




ns 


Serial Address Hold Time 


'SAH 


5 




5 




ns 


SAS Setup Time during Mode Programming 


'SSH 


15 




15 




ns 




SAS Hold Time during Mode Programming 


'SHH 


5 




5 




11 s 


TAS Setup Time 


'TS 


15 




15 




ns 


TAS Hold Time 


'TH 


5 




5 




ns 


SAS Setup Time during System Reset by SAS/TAS 


'SSL 


15 




15 




ns 


SAS Hold Time during System Reset by SAS/TAS 


'SHL 


5 




5 




ns 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



409 



HM53051P 



Read/Write Cycle 



1 



CLK 



WE 



iz: 



jz: 



Notes) * 1 . Write Cycle starts when CGW is low and WE is lo w. Dat a are not written when WE is high. 
Time-compression mod e is re alized by controlling CGW. 
*2. Read cycle starts when CGR is low. Time-expansion mode is realized by controlling CGR. 

Read Cycle (OE control) 




Notes) *1. tQHZ > s defined by the time at which the output achieves the open circuit condition. 
*2- <-OLZ *OHZ are sampled and not 100% tested. 



HITACHI 

410 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Mode Selection 




Note) SAS operates asynchronously with CLK. When TAS is low at the falling edge of the CLK, the 
starts. SAS should be high during the address transfer cycle. 



transfer cycle 



SAS, TAS Reset Mode 





CLK 



SAS 



TAS 



t 


c 

ten 











L IsSL . 

5t 



5£ 



\ 



H////////////////M 



^////////////////%/$ 



Note) The mode which was selected by SAD before SAS and TAS reset, if SAS and TAS are reset, should be changed 
because SAD is newly taken into by SAS. The mode should be reselected by SAD after 5"£S and TAS reset. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 41 1 



HMS3461 Series 

65,536-word x 4-bit Multiport CMOS Video RAM 

The HM53461 is a 262, 144-bit multiport memory equipped 
with a 64k-word x 4-bit Dynamic RAM port and a 256-word x 4- 
bit Serial Access Memory (SAM) port. The SAM port is con- 
nected to an internal 1,024-bit data register through a 256-word x 
4-bit serial read or write access control. In the read transfer 
cycle, the memory cell data is transferred from a selected word 
line of the RAM port to the data register. The RAM port has a 
write mask capability in addition to the conventional operation 
mode. Write bit selection out of 4 data bit can be achieved. 

Utilizing the Hitachi 2j/m CMOS process, fast serial access 
operation and low power dissipation are realized. All inputs and 
outputs, including clocks, are TTL compatible. 



■ FEATURES 

• Multiport organization 

(RAM; 64k-word x 4-bit and SAM; 256 word x 4-bit) 

• Double layer polysilicon/polyicide n-well CMOS process 

• Single 5V (±10%) 

• Low power Active RAM; 380mW max. 

SAM; 220mWmax. 
Standby 40mW max. 

• Access Time RAM; 100ns/1 20ns/1 50ns 

SAM; 40ns/40ns/60ns 

• Cycle Time Random read or write cycle time (RAM) 

190ns/220ns/260ns 

Serial read or write cycle time (SAM) 

40ns/40ns/60ns 

• TTL compatible 

• 256 refresh cycles 4ms 

• Refresh function R AS — only refresh 

CA5 - before - RAS refresh 
Hidden refresh 

• Data transfer operation (RAM^SAM) 

• Fast serial access operation asynchronized with RAM port 
except data transfer cycle 

• Real time read transfer capability 

• Write mask mode capability 



■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM53461P-10 


100ns 




HM53461P-12 


120ns 


400 mil 24-pin 


HM53461P-15 


150ns 


Plastic DIP 


HM53461ZP-10 


100ns 




HM53461ZP-12 


120ns 


24-pin Plastic ZIP 


HM53461ZP-15 


150ns 





HITACHI 

412 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM53461P Series 




(DP-24A) 



HM53461ZP Series 




(ZP-24) 



HM53461 Series 



■ PIN ARRANGEMENT 

' HM53461P Series 




• HM53461ZP Series 



1/04 2 
SI/03 4 

V ss 6 
.JI/01 8 
DT/0E10 



RAS 14 
A5 16 
V cc 18 



(Bottom View) 





1 1/03 




3 SOE 




5 SI/04 




7 SC 




9 SI/02 




11 1/01 




13 WE 




15 A6 




17 A4 




19 A7 




21 A2 




23 AO 



PIN DESCRIPTION 



Pin Name 


Function 


AO - A7 


Address Inputs 


I/Ol - 1/04 


RAM Port Data Input/Output 


SI/01 - SI/04 


SAM Port Data Input/Output 


RAS 


Row Address Strobe 


CAS 


Column Address Strobe 


SC 


Serial Clock 


WE 


Write Enable 


DT/OE 


Data Transfer/Output Enable 


SOE 


SAM Port Enable 


V CC 


Power Supply 


v ss 


Ground 



(Top View) 



BLOCK DIAGRAM 



Write Mask 
control 



WEc 
CASC 

RASc 
Ai 



WE clock 
generator 



CAS 


clock 


gene 


rator 



WAS elook 
generator 



i O- - — ^ 



X address 
1 buffer 



~t FT 



Y address 
buffer 



Refresh 
address 
counter 



RAS 



10 1 



T 

SIO. 



103 10. 

J L 



64K m« 
array 



i 

SIO? 



SIO? 



64 K memory 
array 



T 

SIO. 



256 data 
register 


256 data 
register 


256 
regi 


data 
sler 


256 
reg 


data 
ster 


m 




Pointer 




Pointer 












SI buffer 


SI buffer 


SI buffer 


SI buffer 





ock 


gener 






DT OE 



Transfer 
control 



SOE clock 
generator 



)SOE 



SC clock 
generater 



) SC 



Van generator 



Hitachi / 



HITACHI 

• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



413 



HM53461 Series 



■ ABSOLUTE MAXIMUM RATINGS 

Voltage on any pin relative to Vss -1 V to +7V 

Power supply voltage relative to V ss -0.5V to +7V 

Operating temperature, Ta (Ambient) 0°C to +70°C 

Storage temperature -55°C to +1 25° C 

Short circuit output current 50mA 

Power dissipation 1W 

■ RECOMMENDED DC OPERATING CONDITIONS (T a =0 to +70°C) 



Parameter 


Symbol 


min. 


typ. 


max. 


Unit 


Supply voltage 


Vcc 


4.5 


5.0 


5.5 


V 


Input High voltage 


Vih 


2.4 




6.5 


V 


Input Low voltage 


VlL 


-0.5* 2 




0.8 


V 



DC ELECTRICAL CHARACTERISTICS (T fl = to +70"C, V cc = 5V ±10%, V ss = 0V) 



Notes: 1. All voltages referenced to 

2. -3.0V for pulse width 10ns. 



RAM PORT 


Symbol 


SAM PORT 


HM53461 
-10 


HM53461 
-12 


HM53461 
-15 


Unit 


Standby 


Active 


Operating current RAS, CAS cycling 

t RC = m ' n ' 


'cc\ 


O 


X 


70 


60 


50 


mA 


icct 


X 


O 


110 


100 


80 


mA 


Standby current RAS, CAS » V IH 


l CC2 





X 


7 


7 


7 


mA 


r CCS 


X 


O 


40 


40 


30 


mA 


RAS only refresh current 

CAS ■ Vj H , RAS cycling t^c - min. 


l CC3 





X 


60 


50 


40 


mA 


<CC9 


X 





100 


90 


70 


mA 


Page mode current RAS = V r i, 
CAS cycling tpc* min. 


l CC4 





X 


50 


40 


35 


mA 


'ccio 


X 





90 


80 


65 


mA 


CBR refresh current RAS cycling 
t RC = mm. 


'ccs 





X 


60 


50 


40 


mA 


'ecu 


X 





100 


90 


70 


mA 




Data transfer current 

RAS, CAS cycling t RC • min. 


>CC6 





X 


75 


65 


55 


mA 


ICC\2 


X 





115 


105 


85 


mA 






Parameter 


Symbol 


min. 


max. 


Unit 


Input leakage 


<LI 


-10 


10 


MA 


Output leakage 


'w 


-10 


10 


ma 


Output high voltage /q w = -2m A 


VOH 


2.4 




V 


Output low voltage / oi =4.2mA 


Vol 




0.4 


V 



■ INPUT/OUTPUT CAPACITANCE 



Parameter 


Symbol 


typ. 


max. 


Unit 


Address 


CI1 




5 


pF 


Clocks 


CI2 




5 


pF 


I/O, SI/O 


c i/o 




7 


pF 



HITACHI 

414 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM53461 Series 

■ ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING 
CONDITIONS (T a =0 to +70°C, K CC =5V±10%, V S s=Wf km ' W 



Parameter 


Symbol 


HM5 3461-10 


HM5 3461-12 


HM5 3461-15 


Unit 


Note 


min. 


max. 


min. 


max. 


min. 


max. 


Random Read or Write Cycle Time 


! RC 


190 


- 


220 


- 


260 


- 


ns 




Read-Modify-Write Cycle Time 


<RWC 


260 


- 


300 


- 


355 


- 


ns 




Page Mode Cycle Time 


'PC 


70 


- 


85 


- 


105 


- 


ns 




Access Time from RAS 


<RAC 


_ 


100 


- 


120 


- 


150 


ns 


2, 3 


Access Time from CAS 


'CAC 


- 


50 


- 


60 


_ 


75 


ns 


3,4 


Output Buffer Turn Off Delay referenced to CAS 


'OFF! 





25 





30 





40 


ns 


5 


Transition Time (Rise and Fall) 


<T 


3 


50 


3 


50 


3 


50 


ns 


6 


RAS Precharge Time 


'rp 


80 


_ 


90 


- 


100 


- 


ns 




RAS Pulse Width 


<ras 


100 


10000 


120 


10000 


150 


10000 


ns 




CAS Pulse Width 


'cas 


50 


10000 


60 


10000 


75 


10000 


ns 




RAS to CAS Delay Time 


'rcd 


25 


50 


25 


60 


30 


75 


ns 


7 


RAS Hold Time 


'rsh 


50 




60 




75 




ns 




CAS Hold Time 


'CSH 


100 


_ 


120 




150 


_ 


ns 




CAS to RAS Precharge Time 


'CRP 


10 


_ 


10 


_ 


10 


_ 


ns 




Row Address Setup Time 


'ASR 





_ 





_ 





_ 


ns 




Row Address Hold Time 


'rah 


15 


_ 


15 


_ 


20 


_ 


ns 




Column Address Setup Time 


'asc 










_ 







ns 




Column Address Hold Time 


'CAH 


20 




20 


_ 


25 


_ 


ns 




Write Command Setup Time 


'wcs 





- 





_ 





_ 


ns 


8 


Write Command Hold Time 


'WCH 


25 


- 


25 


- 


30 


- 


ns 




Write Command Pulse Width 


'wp 


15 


_ 


20 


— 


25 


_ 


ns 




Write Command to RAS Lead Time 


<RWL 


35 




40 


_ 


45 


— 


ns 




Write Command to CAS Lead Time 


'CWL 


35 


— 


40 


- 


45 


_ 


ns 




Data-in Setup Time 


'ds 





_ 





_ 





- 


ns 


9 


Data-in Hold Time 


'dh 


25 


- 


25 


- 


30 


- 


ns 


8,9 


Read Command Setup Time 


<RCS 





_ 





_ 





_ 


ns 




Read Command Hold Time 


'rch 





- 





_ 





- 


ns 




Read Command Hold Time referenced to RAS 


'rrh 


10 


_ 


10 


_ 


10 


_ 


ns 




Refresh Period 


'rbf 


_ 


4 


_ 


4 


_ 


4 


ms 




RAS Pulse Width (Read-Modify-Write Cycle) 


'rws 


170 


10000 


200 


10000 


245 


10000 


ns 




CAS to WE Delay 


l CWD 


85 




100 


_ 


125 


_ 


ns 


8 


CAS Setup time (CAS-before-RAS refresh) 


'CSR 


10 


_ 


10 


_ 


10 


_ 


ns 




CAS Hold Time (CAS-before-RAS refresh) 


'CHR 


20 




25 




30 




ns 




RAS Precharge to CAS Hold Time 


'rpc 


10 




10 




10 




ns 




CAS Precharge Time 


'CP 


10 


_ 


15 


_ 


20 


_ 


ns 




Access Time from OE 


'OAC 




30 




35 




40 


ns 




Output Buffer Turn-off Delay referenced to OE 


'OFF2 





25 





30 





40 


ns 




OE to Data-in Delay Time 


'odd 


25 




30 


_ 


40 


_ 


ns 




OE Hold Time referenced to WE 


'OEH 


10 




15 




20 




ns 




Data-in to CAS Delay Time 


'DZC 

















ns 




Data-in to OE Delay Time 


'dzo 

















ns 




OE to RAS Delay Time 


<ORD 


35 




40 




45 




ns 




Serial Clock Cycle Time 


'sec 


40 




40 




60 




ns 




Access Time from SC 


'SCA 




40 




40 




60 


ns 


10 


Access Time from SOE 


'sea 




25 




30 




40 


ns 


10 


SC Pulse Width 


'sc 


10 




10 




10 




ns 





(to be continued) 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 41 5 



HM53461 Series 



r aramcicr 


J; in I'm 


HM5 3461-10 


HM5 3461-12 


HM53461-15 


Unit 


Note 


min. 


max. 


min. 


max. 


min. 


max. 


SC Prechaige Width 


'SCP 


10 


_ 


10 


- 


10 


- 


ns 




Serial Data-out Hold Time after SC High 


'SOH 


10 




10 




10 


_ 


ns 




Serial Output Buffer Turn-off Delay from SOE 


'SEZ 





25 





25 





30 


ns 




Serial Data-in Setup Time 


'SIS 















_ 


ns 




Serial Data-in Hold Time 


<SIH 


15 




20 




25 


„ 


ns 




DT to RAS Setup Time 


'DTS 





_ 





_ 








ns 




DTto RAS Hold Time(Read Transfer Cycle) 


'rdh 


80 




90 




110 


- 


ns 




DT to RAS Hold Time 


'dth 


15 


_ 


15 


_ 


20 


_ 


ns 




T3T to CAS Hold Time 


! CDH 


20 


- 


30 


- 


45 


- 


ns 




Last SC to DT Delay Time 


'SDD 


5 


_ 


5 


_ 


10 


_ 


ns 




First SC to DT Hold Time 


'SDH 


25 


_ 


25 


_ 


30 


_ 


ns 




DT to RAS Delay Time 


'dtr 


10 


_ 


10 


- 


10 


_ 


ns 




WE to RAS Setup Time 


'ws 





_ 





_ 





_ 


ns 




WE to RAS Hold Time 


'WH 


15 




15 


_ 


20 


_ 


ms 




I/O to RAS Setup Time 


'MS 





_ 





_ 





_ 


ns 




I/O to RAS Hold Time 


'MH 


15 


_ 


IS 




20 


_ 


ns 




Serial Output Buffer Turn-off Delay from RAS 


'SRZ 


10 


50 


10 


60 


10 


75 


ns 




SC to RAS Setup Time 


'SRS 


30 


_ 


40 


_ 


45 


_ 


ns 




RAS to SC Delay Time 


'SRD 


25 


_ 


30 


_ 


35 


_ 


ns 




Serial Data Input Delay Time from RAS 


'SID 


50 


_ 


60 


_ 


75 


_ 


ns 




Serial Data Input to DT Delay Time 


'SZD 





_ 





_ 





_ 


ns 




SOE to RAS Setup Time 


'es 





_ 





_ 





- 


ns 




SOE to RAS Hold Time 


'eh 


15 




15 




20 




ns 




Serial Write Enable Setup Time 


'sws 

















ns 




Serial Write Enable Hold Time 


'SWH 


35 




35 




55 




ns 




Serial Write Disable Setup Time 


'SWIS 

















ns 




Serial Write Disable Hold Time 


'SWIH 


35 




35 




55 




ns 




DT to Sout in Low-Z Delay Time 


'DLZ 


5 




10 




10 




ns 





Notes) 

1 . AC measurements assume t7-=5ns. 

2. Assumes that iKC£>Sr RC£) (max). If t RCD is greater 
than the maximum recommended value shown in this 
table, t RAC exceeds the value shown. 

3. Measured with a load circuit equivalent to 2TTL loads 
and lOOpF. 

4. Assumes that f rcd^i RCD (na\). 

5 'OFF( max ) defines the time at which the output 
achieves the open circuit condition and is not referenced 
to output voltage levels. 

6. K//y<min) and Vnfinix) are reference levels for measur- 
ing timing of input signals. Also, transition times are 
measured between V IH and Vj^. 

7. Operation with the fjj co (max) limit insures that t KAC 
(max) can be met, r RCO (max) is specified as a reference 
point only, if t R cD ' s greater than the specified t R cD 
(max) limit, then access time is controlled exclusively be 
'CAC. 



ft-'wcs an d 'cwd *** not restrictive operating parameters. 
They are included in the data sheet as electrical charac- 
teristics only: if t wcs ^t W cs( m >"). the cvcle is an early 
write cycle and the data out pin will remain open circuit 
(high impedance) throughout the entire cycle; if t CWD 
=t c w D (min), the cycle is a read/write and the data 
output will contain data read from the selected cell; if 
neither of the above sets of conditions is satisfied, the 
condition of the data out (at access time) is indeter- 
minate. 

9. These parameters are referenced to CAS leading edge in 
early write cycle and to WE leading edge in delayed 
write or read-modify-write cycles. 

10. Measured with a load circuit equivalent to 2TTL and 
50pF. 

11. An initial pause of 100ms is required after power-up. 
Then execute at least 8 initialization cycles. 



HITACHI 

416 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



■ WAVE FORMS 
• READ CYCLE 



RAS - 



CAS ■ 



IRAK lASC 



Address^' 

* '////////// 



I/O 

(Output) 



— Sr 

DT/OE 



HM53461 Series 



wzzzzzzzzzzzz 



<: 



VALID 
Doul 



tarrZ 



• EARLY WRITE CYCLE 



RAS ■ 



X 



CAS- 



Address 



tR AH tASC 



P7Z Do not care 



I/O "\ r 

(Input) 



yZZZZZZZMZL 



' ///////////, 



I/O 

(Output) 



DT/OE • 



High Z 



2* ^zzzzzzzzzzzzzzzzzzzzzz 



V7Ji Do not care 

Note) * 1 . When WE is "H" level, the all data on the I/O can be written into the cell. 

When WE is "L" level, the data on the I/O are not written except for when I/O is 'high' at the falling edge of RAS. 



<gr HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



417 



• DELAYED WRITE CYCLE 

RAS • 



CAS- 



Address 



WE 



DT/OE 



t in 

oe 



»: 



v 



: </////////////////. 



wmr^-s //// //////// 



-wmnmnnm. 



whuhzhr 



VALID 
Din 



I/O 

(Output)" 



High Z 



1/// Do not care 

"H" level, all the data on I/01-I/04 can be written into the memory cell. 

level, the data on I/Os are not written exept for when I/0"H" at the falling edge of RAS. 



Note) 

• READ MODIFY WRITE CYCLE 

RAS 



X 



Address 



I/O 
(Input)" / 



I/O 

(Output) 



DT/OE / // f ' 



/ 



777777; 



^y 



\ ^V77777777, 




'/////////, 



lnv?2 



H////////A 

l// A Do not care 



Note) * 1 . When WE is "H" level, all the data on I/O 1 -1/04 can be written into the memory cell. 

When WE is "L" level, the data on I/Os are not written except for when I/0="H" at the falling edge of RAS. 



418 



<§> HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM53461 Series 



• PAGE MODE READ CYCLE 



RS5- 



CAS- 



Address 



zx 



lHAH 
tAM 



X 




OLUMNJI 



mm 



I/O 

(Output) 



(Input) "[]_ 




VALID \ 
Pout j r 



(CP 

M»- (C/IH 



-t«s« 
(c*s 



/ — V 

* J,.., ^ 1 ' 



zzzzSzzMdgzzzmzzz 

'*51-L. „,cs toes COLUMN to !^ I' 



tCAC tOhhl 



(valid\ 
Pout j f 



■ ^"-"^ few 



iwf2 



izzzz 



VALID 

Dout 



> 



tf)A( ttthhl 



1 jsr-fjl 

M* . >77777: 



Do not care 



• PAGE MODE WRITE CYCLE (Early Write) 



RAS- 
CAS- 

Adress 

WEi 

I/O 
(Input) 

I/O 



5t 



X 



(Output) ip 



X 



» «| furs | Mrs . 

f»S«t-» (uh (osl 1 -"»"•) — - (HJ- 



VALID 
Din 



kzzzzzx: 



. ITTTTTTTT, 



twv » H 



■*(DH«H /DS|-»] f— /OH— • 

mmM&mnm 



High Z 



7/ ^iiiiim/iiiimiiiiii/iiiimnmih 



not care 



Note) *1. When WE is "H" level, all the data on I/0-I/04 can be written into the memory cell. 

When WE is "L" level, the data on I/Os are not written except for when I/0="H" at the falling edge of RAS. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 - (415) 589-8300 41 9 



HM53461 Series 



• PAGE MODE WRITE CYCLE (Delayed Write) 



RAS ■ 



CAS - 



/ 



\ 



Address /)ff~ ROW 




nmumni 



tCAS " * tCAS . i i 
*" »- tCAS .1 " ~ P 



77TTT ^IIIimilll, 



mmmmm 



High Z 



DT'OE 



wmiiim 

V/A Do not care 

Note) * 1 . When WE is "H" level, all the data on I/0-I/04 can be written into the memory cell. 

When WE is "L" level, the data on I/Os are not written except for when I/0="H" at the falling edge of RAS. 

• RAS-ONLY refresh cycle 



CAS 



msmm 



toFrl 



I/O 7 
(Output) ' 



2ZZ> 



I/O . 
(Input) 



tors 

DT/OE 



Ml A Do not care 



<§> HITACHI 

420 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• CAS-BEFORE-RAS REFRESH 



HM53461 i 



ra5 ■ 



CAS • 



\ 



7 



tCSB 


ICHH 


\ 





^ 777777777//////////////////777777m. 
« 7 777777////////////////////77TTT77TT / 
K- >///////////////////////////////////, 

I/O High Z 

(Output) 

" «. 777777Z///////////////////////////, 

V/A Do not care 

> HIDDEN REFRESH CYCLE 



RAS 



CAS" 



Address 



7^ ROW 



tA 

i 



if 



WE 



I/O 

(Output) 



DT/OE 



I/O 

(Input) 



^ ni/h/r/z/n/mnm, 



^tnnnnnnm 

tOFFl 



< 



VALID 
Do,. 



tott-2 



> 



High Z 



V/A Do not care 



^HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



421 



HM53461 Series 

• READ TRANSFER CYCLE (1)* 1 * 2 

RAS" 



CAS 



Address 



WE 



7K 



I/O 

(Output) 



IH»'h 3 lASt'S' 



mMZZM 



DT'OE 



tnrs 

2£ 



sc 



Note 



SI/O 
(Output) 

SI/O 

(Input) ' 



:eru 



Valid 
Soul 



Previous 
Row ** 



"I HighZ 1 



- New Row 



Do not care 



*1) In the case t hat th e previous data transfer cycle was read transfer. 
*2) Assume that SOE is "L" level. 
*3) CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM start address. 
• READ TRANSFER CYCLE (2)* 1 -* 2 

tar 

RAS 



CAS ■ 



tCHf 



if 



WE , 



I/O 

(Output) 



I/O 
(Input) 



_ l£SH I _ 



High Z 



DT/OE \- 



J (urn 



V (SB 



%///////// 




Do not care 
| Inhibit rising transient 



Note) 

• 1) In the case t hat th e previous data transfer cycle was write transfer or pseudo transfer. 

• 2) Assume that SOE is "L" level, 

*3) CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM start address. 



422 



HITACHI 

America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM53461 Series 



• PSEUDO TRANSFER CYCLE 
RAS 



CAS 



Address 

WE 
DT/OE 
SOE 
SC 



tOTS 



J. 



IK 



— - lire 

2f 



SAM START 
ADD 



wnmmnimm 



ii/iiii/iiiin/niiiinm 



mmmmmzmzmnL 



SI/O 
(Input) ■ 



SI/0 
(Output) 



gzzzzzzzz^ 



VALID 

Si> 



Do not care 



Note) 

CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM start address. 
• WRITE TRANSFER CYCLE 



RAS ' 



CAS 



Address 



WE 



DT/OE 



SOE 



2£ 



2£ 



2f 



3 s ' 



)0p^ m77m/////////// 

tCSH I 

fllll/l/llll/lW/l/II/ll, 



ymmnmmnnnnm. 



\zymmnnmnL 



i ffn . ' scc j 



SC 



ts/s 



SI/0 
(Input) 



SI/0 
(Output) ' 



High-Z 



V/A Do not care 

Inhibit rising transient 



Note) *1. 

CAS and SAM start Address need not be supplied every cycle, only when it is desired to change to a new SAM start Address. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



423 



HM 53461 Series 



• SERIAL READ CYCLE 

Has 



X 



* /////////////////////F V//JT/ 
/ \ 



sc 



SI o 
(Output) 




T 



xzzdD 



/ v.i,d V / /V * M 

Do not care 



• SERIAL WRITE CYCLE 







^ /////////////////////F 

] 1 tswis - ^ 



X 



vmzL 



SOE 



SC 



1 | . 'sep , ' l.i | tscp I ). tscr i I ^ / 

Isc ^ \ ( _ tsc _ Y f m Isc Y / | Isc a V ^/ 



XZZXI 



K/^ Do not care 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



65,536-word x 4 bits Multiport CMOS Video RAM (with Logic operation mode) 



The HM53462 is a 262, 144 bit multiport memory equipped 
with a 64k-word x 4 bit Dynamic RAM port and a 256-word x 
4-bit Serial Access Memory (SAM) port. The SAM port is con- 
nected to an internal 1,024-bit data register through a 256-word 
x 4-bit serial read or write access control. In the read transfer 
cycle, the memory cell data is transferred from a selected word 
line of the RAM port to the data register. The RAM port has a 
write mask capability in addition to the conventional operation 
mode. Write bit selection out of 4 data bit can be achieved. 
RAM port has another new function, logic operation capability. 
By this function logic operation between memory data and input 
data can be done in one cycle. Utilizing the Hitachi 2/um CMOS 
process, fast serial access operation and low power dissipation are 
realized. All inputs and outputs, including clocks, are TTL 
compatible. 

■ FEATURES 

• Multiport organization 

(RAM; 64k-word x 4 bit and SAM; 256-word x 4 bit) 

• Double layer polysilicon/polyicide n-well CMOS process 

• Single 5V (±10%) 

• Lowpowr Active RAM; 380 mW max. 

SAM; 220 mW max. 
Standby 40 mW max. 

• Access Time RAM; 100ns/120ns/150ns 

SAM; 40ns/40ns/60ns 

• Cycle Time Random read or write cycle time (RAM) 

190ns/220ns/260ns 
Serial read or write cycle time (SAM) 
40ns/40ns/60ns 



TTL compatible 
256 refresh cycles 
Refresh function 



4ms 

RAS — only refresh 
CAS - before - RAS refresh 
Hidden refresh 
Bidirectional data transfer operation (RAM J± SAM) 
Fast serial access operation asynchronized with RAM port ex- 
cept data transfer cycle 
Real time read transfer capability 
Write mask mode capability 
Logic operation capability between Din and Dout 
SAM organization can be changed to 1024 x 1 



HM53462P Series 



i(0 



(DP-24A) 



HM53462ZP Seires 




(ZP-24) 



■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM53462P-10 
HM53462P-12 
HM53462P-15 


100ns 
120ns 
150ns 


400 mil 24 pin Plastic 
DIP 


HM53462ZP-10 
HM53462ZP-12 
HM53462ZP-15 


100ns 
120ns 
150ns 


24 pin Plastic ZIP 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 4 25 



HM 53462 Series 



■ PIN ARRANGEMENT 

• HM53462P Series 



sc |T" 


24j Vss 


ji/\Ji \ & 


23] SI/O4 




99 1 ci/n 
fa— 1 


nT/nr 1 4 


oTI SOF 

fal 1 O W Li 


i/o, PT 


20I I/O. 


\/Q t | 6 


19] I/O3 


WE | 7 


Igj CAS 


rasQT 


hJa,, 


A<,[7 


Ti] Ai 


As Qo 


15) A.- 


a, (77 


h] Aj 


V'cc [l2 


13] A> 



• HM53462ZP Series 

1.04 2 = 
SI 03 4 H 
V« 6 = 

jim 8 = 
iff oe 10 = 
1,02 12 = 

RAS 14 = 

A5 16 = 
V cc 18 ' 

A3 20 = 

A122 = 
CAS 24 s 

(Bottom View) 



PIN DESCRIPTION 









1 1/03 




3 SOE 




5 SI 04 




7 SC 




9 SI/02 




11 I/O! 




13 WE 




15 A6 




17 A4 




19 A7 




21 A2 




23 AO 



(Top View) 



BLOCK DIAGRAM 




We 











(A tt> 





Dout 

Memory Array 
(256x 256) 



Pin Name 


Function 


AO - A7 


Address Inputs 


I/Ol - 1/04 


RAM Port Data Input/Output 


Sl/Ol - SI/04 


SAM Port Data Input/Output 


RAS 


Row Address Strobe 


CAS 


Column Address Strobe 


SC 


Serial Clock 


WE 


Write Enable 


DT/OE 


Data Transfer/Output Enable 


SOE 


SAM Port Enable 


v C c 


Power Supply 


vss 


Ground 




SI/Ol 



BY 1 Mode 
(1024X1) 
Other SI/O (2-4) 
Are in High Z State. 



SI/Ol 



BY 4 Mode 256X4 
(Normal Mode) 



426 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 53462 Series 



■ ABSOLUTE MAXIMUM RATINGS 

Voltage on any pin relative to V ss -1V to +7V 

Power supply voltage relative to V$s -0.5V to +7V 

Operating temperature, Ta (Ambient) 0°Cto+70°C 

Storage temperature -55°C to +1 25°C 

Short circuit output current 50mA 

Power dissipation 1W 

■ INPUT/OUTPUT CAPACITANCE 



Parameter 


Symbol 


typ. 


max. 


Unit 






Address 


CI, 




5 


PF 






Clocks 


CI 3 




5 


pF 






I/O, SI/O 


Ci/O 




7 


PF 






RECOMMENDED DC OPERATING CONDITIONS (Ta = to 


Parameter 


Symbol 


min. 


typ. 


max. 


Unit 


Supply voltage 


v C c 


4.5 


5.0 


5.5 


V 


Input High voltage 




2.4 




6.5 


V 


Input Low voltage 


VlL 


-0.5 




0.8 


V 



Notes) 1. All voltages referenced to Kjj. 
2. -3.0V for pulse width g 10ns. 



■ DC ELECTRICAL CHARACTERISTICS (Ta = to +70°C, V C C = 5V ± 10%, V SS = 0V) 



RAM PORT 


Symbol 


SAM PORT 


HM53462 


HM53462 


HM53462 


Unit 


Standby 


Active 


-10 


-12 


-15 


Operating current RAS, CAS cycling 


!CCI 


O 


X 


70 


60 


50 


mA 




lea 


X 


o 


110 


100 


80 


mA 


Standby current RAS, CAS - V IH 


! CC1 


o 


X 


7 


7 


7 


mA 


icc% 


X 


o 


40 


40 


30 


mA 


RAS only refresh current 


J CC3 


o 


X 


60 


5 


40 


mA 


CAS= K///.RAS cycling t RC = mm. 


'CC9 


X 


o 


100 


90 


70 


mA 


Page mode current RAS = V lL , 


l CCA 


o 


X 


50 


40 


35 


mA 


CAS cycling t PC ' min. 


>cc\o 


X 


o 


90 


80 


65 


mA 


CBR refresh current RAS cycling 
fK C =min. 


Ices 


o 


X 


60 


50 


40 


mA 


!CC1 1 


X 


o 


100 


90 


70 


mA 


Data transfer current 


f CC6 





X 


75 


65 


55 


mA 


RAS, CAS cycling t RC = min. 


'cc\i 


X 


o 


115 


105 


85 


mA 


















Parameter 


Symbol 


min. 


max. 


Unit 








Input leakage 


'LI 


-10 


10 


fA 








Output leakage 


Ilo 


-10 


10 


M 








Output high voltage I OH - -2 mA 


VOH 


2.4 




V 








Output low voltage I OL = 4.2 mA 


Vol 




0.4 


V 









HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 427 



HM 53462 Series 



ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING 
CONDITIONS (7a = to +70°C, V C C = 5V ± 10%, V SS = 0V)u. io). iu 



Parameter 


Symbol 


HM5 3462 
-10 


HM53462 
-12 


HM53462 
-15 


Unit 


Note 


min. 


max. 


min. 


max. 


min. 


max. 


Random Read or Write Cycle Time 


'RC 


190 


- 


220 


- 


260 


- 


ns 




Read-Modify-Write Cycle Time 


'R WC 


260 


- 


300 


- 


3S5 




ns 




Page Mode Cycle Time 


'PC 


70 


- 


85 


- 


105 


- 


ns 




Access Time from RAS 


'RAC 


- 


100 


- 


120 


- 


ISO 


ns 


2, 3 


Access Time from CAS 


'CAC 


- 


50 


- 


60 


- 


75 


ns 


3, 4 


Output Buffer Turn Off Delay referenced 
to CAS 


'OFF\ 


o 


25 


o 


30 





40 


ns 


S 


Transition Time (Rise and Fall) 


>T 


3 


50 


3 


50 


3 


so 


ns 


6 


RAS Precharge Time 


<RP 


80 




90 


— 


100 


— 


ns 




RAS Pulse Width 


'RAS 


100 


10000 


120 


10000 


150 


10000 


ns 




CAS Pulse Width 


'CAS 


50 


10000 


60 


10000 


75 


10000 


ns 




RAS to CAS Delay Time 


'RCD 


25 


50 


25 


60 


30 


75 


ns 


7 


RAS Hold Time 


'RSH 


SO 


— 


60 


— 


75 


— 


ns 




CAS Hold Time 


'CSH 


100 


— 


120 


— 


150 


— 


ns 




CAS to RAS Precharge Time 


<CRP 


10 


— 


10 


- 


10 


- 


ns 




Row Address Setup Time 


<ASR 





- 





- 





- 


ns 




Row Address Hold Time 


'RAH 


15 


- 


15 


— 


20 


— 


ns 




Column Address Setup Time 


>ASC 





- 





- 





- 


ns 




Column Address Hold Time 


'CAH 


20 


- 


20 


- 


25 


- 


ns 




Write Command Setup Time 


'WCS 

















ns 


8 


Write Command Hold Time 


'WCH 


25 




25 




30 


: 


ns 




Write Command Pulse Width 


'WP 


15 


_ 


20 


_ 


25 


_ 


ns 




^Vrite Command to RAS Lead Time 


'R WL 


35 


- 


40 


- 


45 


- 






Write Command to CAS Lead Time 


'CWL 


35 




40 




45 









Data-in Setup Time 


'DS 

















ns 


9 


Data-in Hold Time 


'DH 


25 


- 


2S 


- 


30 


- 


ns 


8, 9 


Read Command Setup Time 


'RCS 

















ns 




Read Command Hold Time 


<RCH 

















ns 




Read Command Hold Time referenced 
to RAS 


<RRH 


10 




10 




10 




ns 




Refresh Period 


'REF 


- 


4 




4 


- 


4 


ms 




RAS Pulse Width 

(Read-Modify-Write Cycle) 


'R WS 


170 


10000 


200 


10000 


245 


10000 






CAS to WE Delay 


'CWD 


85 


- 


100 


- 


125 


- 


ns 


8 


CAS Setup Time 
(CSS - before - RSS refresh) 


'CSR 


10 


- 


10 


- 


10 


- 






CAS Hold Time 

(CSS - before - RAS refresh) 


<CHR 


20 


- 


25 


- 


30 


- 


ns 




RAS Precharge to CAS Hold Time 


'RPC 


10 


- 


10 


- 


10 


- 






CAS Precharge Time 




10 




15 




20 








Access Time from OE 


'OAC 




30 




35 




40 


ns 




Output Buffer Turn-off Delay referenced 
to OE 


'OFF! 





25 





30 





40 


ns 




OE to Data-in Delay Time 


'ODD 


25 




30 




40 




ns 




OE Hold Time referenced to WE 


'OEH 


10 




15 




20 




ns 




Data-in to CAS Delay Tims 


'DZC 

















ns 




Data-in to OE Delay Time 


'DZO 

















ns 




OE to RAS Delay Time 


'ORD 


35 




40 




45 




ns 





(to be continued) 



HITACHI 

428 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 53462 Series 



Parameter 


Symbol 


HM53462 
-10 


HM53462 

-12 


HM53462 
-15 


Unit 


Note 


min. 


max. 


min. 


max. 


min. 


max. 


Serial Clock Cycle Time 


'sec 


40 




40 




60 




ns 




Access Time from SC 


'SCA 




40 




40 




60 


ns 


10 


Access Time from SOE 


'SEA 


- 


25 


- 


30 


- 


40 


ns 


10 


SC Pulse Width 




10 


- 


10 


- 


10 


- 


ns 




SC Precharge Width 


*SCP 


10 


- 


10 


- 


10 


- 


ns 




Serial Data-out Hold Time after SC High 


t SOH 


10 




10 


- 


10 


- 


ns 




Serial Output Buffer Turn-off Delay 
from SOE 


l SEZ 





25 





25 





30 


ns 




Serial Data-in Setup Time 


'SIS 





- 





- 





- 


ns 




Serial Data-in Hold Time 


'SIH 


IS 


_ 


20 


- 


25 


_ 


ns 




DT to RAS Setup Time 


' DTS 





_ 





- 





- 


ns 




DT to RAS Hold Time 
(Read Transfer Cycle) 


'RDH 


80 




QO 




1 1 rt 

1 1U 




ns 




DT to RAS Hold Time 


'DTH 


IS 


- 


15 


- 


20 


- 


ns 




DT to CAS Hold Time 


'CDH 


20 


- 


30 


- 


45 


- 


ns 




Last SC to DT Delay Time 


'SDD 


5 


- 


5 


- 


10 


- 


ns 




First SC to DT Hold Time 


'SDH 


25 


— 


25 


— 


30 


— 


ns 




DT to RAS Delay Time 


'DTR 


10 




10 




10 




ns 




WE to RAS Setup Time 


'WS 





_ 





_ 





_ 


ns 




WE to RAS Hold Time 


'WH 


15 


_ 


1 5 


_ 


20 


_ 






I/O to RAS Setup Time 


'MS 





_ 





_ 





_ 


ns 




I/O to RAS Hold Time 


'MH 


IS 


_ 


IS 


_ 


20 


_ 


ns 




Serial Output Buffer Turn off Delay 
from RAS" 


'SRZ 


.0 


50 


10 


60 


1 




ns 




SC to RAS Setup Time 


'SRS 


30 




40 


- 


45 




ns 




RAS to SC Delay Time 


'SRD 


25 





30 


- 


35 




ns 




Serial Data Input Delay Time from RAS 


'SID 


50 




60 


- 


75 


- 


ns 




Serial Data Input to DT Delay Time 


>SZD 










- 





- 


ns 




SOE to RAS Setup Time 


'ES 


| - 


- 





- 


ns 




SOE to RAS Hold Time [ t£H 


15 - 


1 S 




20 




ns 




Serial Write Enable Setup Time 


'SWS 















ns 




Serial Write Enable Hold Time 


'SWH 


35 1 - 


35 




55 




ns 




Serial Write Disable Setup Time 


'SWIS 





_ 












ns 




Serial Write Disable Hold Time 


'SWIH 


35 




35 




55 




ns 




DT to Sout in Low-Z Delay Time 


'DLZ 


5 




10 




10 




ns 






1. AC measurements assume t T = 5ns. 

2. Assumes that tR^p ^ <RCD (max). If tR CD is greater 
than the maximum recommended value shown in this 
table, r/j^c exceeds the value shown. 

3. Measured with a load circuit equivalent to 2TTL loads 
and 100 pF. 

4. Assumes that t^^Q ^ tRCD (max). 

5. tQFF (max) defines the time at which the output 
achieves the open circuit condition and is not refer- 
enced to output voltage levels. 

6. Vj H (min) and V/ L (max) are reference levels for 
measuring timing of input signals. Also, transition 
times are measured between V iff and V IL . 

7. Operation with the tRCD (max) limit insures that 
'RAC (max) can be met, f/?cD (max) is specified as a 
reference point only, if irc d is greater than the speci- 
fied t RCD (max) limit, then access time is controlled 
exclusively be tcAC- 

8. t wcs and i C WD are not restrictive operating para- 



meters. They are included in the data sheet as electri- 
cal characteristics only: if t wcs S t wcs (min), the 
cycle is an early write cycle and the data out pin will 
remain open circuit (high impedance) throughout the 
entire cycle; if tcwD = 'CWD (min), the cycle is a 
read/write and the data output will contain data read 
from the selected cell; if neither of the above sets of 
conditions is satisfied, the condition of the data out 
(at access time) is indeterminate. 
9. These parameters are referenced to CAS leading edge 
in early write cycle and to WE leading edge in delayed 
wTite or read-modify-write cycles. 

10. Measured with a load circuit equivalent to 2TTL and 
50 pF. 

11. After power-up, pause for more than lOO^s and 
execute at least 8 initialization cycles. Then execute 
at least one logic reset cycl e inc luding write mask 
reset (on the falling edge of RAS, WE = "Low" and 
1/01 — I/O = "High"), and execute one or more trans- 
port cycle for initiation of SAM port. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 53462 Series 



- WAVE FORMS 

• READ CYCLE ras 



CAS ■ 



Address 



^ '//////////// 



I'O 

(Output) 



DT OE 

• EARLY WRITE CYCLE 

RAS - 

CAS ■ 



< 



v/////// 



VALID 
lh.ul 



Y/A Do not care 



I o 

(Output! 

IUTS 

DTO-E^f 



' //////////// 



High Z 



P73 Do not care 



Note) *1 . When WE is "H" level, the all data on the I/O can be written into the cell. When WE 
is "L" level, the d ata o n the I/O are not written except for when I/O is "H" level at 
the falling edge of RAS. 



430 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 53462 Series 



• DELAYED WRITE CYCLE 

RAS 



CAS- 



Address 



tor 



If 



I/O 

(Input) . 



xzzzzzzzzzzzzzzzz 



W////////////////7 



2TZ3®C^Ii€ZZZZZ2ZZZZZ 



I/O 

(Output)" 



High Z 



1//^ Do not care 

Note) *1. When WE is "H" level, all the data on I/O 1-1/04 can be written into the memory cell. 

When WE is "L" level, the data on I/Os are not written except for when I/O " "H" at the falling edge of 



• READ MODIFY WRITE CYCLE 

RAS 



CAS- 



Address 



(Input) 7 / /X " 



10 

(Output)" 



> 



milium 



/ 



777777; 



- /rt*y. - 

-/WW 



2 ' VALID 1 1 
tottl 



-ff y////////A 



^///////// 



Do not care 

Note) * 1 . When WE is "H" level, all the data on I/O 1 -1/04 can be written into the memory cell. tLJ - u 

When WE is "L" level, the data on I/Os are not written except for when I/O " "H" at the falling edge of 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • POOO Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 431 



HM 53462 Series 

• PAGE MODE READ CYCLE 



RA5 • 



CAS- 



Address 



" , . tens . | . . ,1 \, 



WE 



mm 



I/O 

(Output)' 



I/O 

(Input) 



VALID \ 
Pout i * 



DT/OE , 



t"c tctn 



nr^i.'nrr 1 <«™ L rryn column ~3 z: P^ r 



~4- tecs - *cs 

~~w — ;w~ 



(valid\ 
DoutJf 



V7ZL 



VALID 
Dout 



tin 

'07777*. 



torn ti>yt2 



FTT7TT, 



• PAGE MODE WRITE CYCLE (Early Write) 



V/A Do not care 



RAS- 



CAS- 



Adress 



5d 



— IKSH— ^ 



I/O 

(Input I _ 

I/O 

(Output) 



. ^7777* . 



/»>H— * / Mil thS^I"! H 

- — — *-i k-^ |*-^I/)H lush 

9oeazzzzz>l 



VALID 
Din 



)S«ZZZZZfc3<ZZZS^^ZZ2ZZS 

///////A 



VALID 
Din 



5dZHZM 



High Z 



■n-w/J V// ///////////////////////////// //////, 

MIA Do not care 

Note) * 1. When WE is "H" level, all the data on 1/01-1/04 can be written into the memory cell. 

When WE is • , L' - level, the data on I/Os are not written except for when I/O = "H" at the falling edge of 
RAS. 



HITACHI 

432 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 53462 Series 



• PAGE MODE WRITE CYCLE (Delayed Write) 



RAS • 



CAS - 



7 




szzzzzseSzza&zszzzz^ 

J2 K fit'"- I— — I'"" rnl i.mv Kft-IH.-J - 



77Z7 X ^77777a f7777. ^ 71f777777777/ 



[— . f/>H - - fUrf -*4- * tUH 



High Z 



DT OK 



V/A Do not care 

Note) *1. When Wis "H" level, all the data on I/01-I/04 can be written into the memory cell. 

When WE is "L" level, the data on I/Os are not written except for when I/O = "H" at the falling edge of 
RAS. 



• RAS-ONLY REFRESH CYCLE 



RAS 



CAS 



Address 



s tiiiniiiiii, 

... AH 

^lnmiiiiiiimmininh 



'output) y// > 



I/O . 
(Input) 



WmiMIIMIIIIMIIIHL 



DT/OE 



*W vjlllllllinmilllllllTTTTT, 



UTA Do not care 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 53462 Series - 



• C7S5-BEFORE-TOS REFRESH CYCLE 



RAS 



—J inv, tarn ^ i 



"CAS 



Y 



Address 



/////////////////////////////// 



" ///7T V///////////////////7 



//////////////////////////////// 



I/O 

(OUTPUT) ' 



HIGH Z 



^ ///////////////////////////////7 



Do not care 



• HIDDEN REFRESH CYCLE 



ra5 



ca5 



Address 



[HAM 

Use 



X 



10 

(Output) 



% — 



W//////////////77777; 



.0 7 

(Input) 



-V Hi/n/iiir, 

J lw>l 



VALID 



> 



tot f 2 

M777 



High Z 



l//y| Do not care 



HITACHI 

434 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• READ TRANSFER CYCLE (1)* 1 -* 2 

RAS" 



CAS 



Address 



7K 



HM 53462 Series 



™ m ■■■ p///m//////m> //////WW, 



I/O 

(Output) 



■c, ) umii//miHi u[ i n i iih/iii/ i /i ii/ 



DT/OE 



(Output) ' 




Sl/O 
(Input) - 



High Z 



Previous 
Ron 



- New Row 



Do not care 



NOTE *1 ) In the case t hat the previous data transfer cycle was read transfer. 

•2) Assume that SOE is "Low". 

*3) CAS and SAM start Address need not be supplied every cycle, only when it is desired to change to a new SAM 
start Address. 
• READ TRANSFER CYCLE (2)* 1 * 2 



RAS 



CAS • 



WE , 



I/O 

(Output) 

I/O 
(Input) 



High Z 



DT/OE 



I /;i7 n 



sc 



SI/O 
(Output) 



Sl/O 

(Input) 



;'5 



Do not care 
| Inhibit rising transient 



NOTE *1) In the case t hat th e previous data transfer cycle was read transfer. 

*2) Assu me that SOE is "Low" 

*3) CAS and SAM start Address need not be supplied every cycle, only when it is desired to change to a new SAM 
start Address. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



435 



HM 53462 Series 

• PSEUDO TRANSFER CYCLE 

RAS 



CAS 



Address 



— \. 

tHAH tASC V 




ROW 



2p 



DT OE 



SOE 



f/>TS 

2f 



2t' 



sc 



W^. «77777777////////// 



^///////////////////////// 



■^i/iimnnmyii/wni 



SI o 

(Input) ' 



SI 

(Output) 







Do not care 
Inhibit rising transient 



*1) CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM 

start address. 
• WRITE TRANSFER CYCLE 



RAS" 



CAS 



Address 



2p 



DT/OE 



SOE 



2$: 



2C 



ts«s 



4.sc 1 1 



»Q0C^3GZZZZZZZ 



z 



■flmn/nmnmnlnm. 



jimniiiiiimi/i)//////. 



's«o Iscc 



SC 



SI/O 
(Input) 

SI/O 
(Output) 



OOGZZZZZZZZZZZZZZ»PpGZ<l' 

High-Z 



y/^ Do not care 

Inhibit rising transient 



*1) CAS and SAM start address need not be supplied every cycle, only when it is desired to change to a new SAM 
start address. 

HITACHI 

436 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 53462 Series 



• SERIAL READ CYCLE 

RAS 



-* imiiiiimii/i/TTm kzzzzzz 



f 



SOE 



/ 




ISi 'it 



\ So 



KZTm 

Do not care 



• SERIAL WRITE CYCLE 

RAS 



^ iiiiiiiiinii/iiiiiirt kzzzzzz 



SOE 



SC 



SI/O 
(Input) 



A \ 



tsis •-•] 



■ ELECTRICAL AC CHARACTERISTICS (Logic operation mode) 



777 Do not care 



Parameter 


Symbol 


HM53462-10 


HM53462-12 


HM53462-15 


Unit 


min. 


max. 


min. 


max. 


min. 


max. 


Write cycle time 


( FRC 


230 




265 




310 




ns 


RAS pulse width in write cycle 


'RFS 


140 


10000 


165 


10000 


200 


10000 


ns 


CAS pulse width in write cycle 


'CFS 


80 


10000 


95 


10000 


105 


10000 


ns 


CAS hold time in write cycle 


*FCSH 


140 




165 




200 




ns 


RAS hold time in write cycle 


'FRSH 


80 




95 




105 




ns 


Page mode cycle time (Write cycle) 


f FPC 


100 




120 




135 




ns 


CA5~hold time 

(Logic operation set/reset cycle) 


f FCHR 


90 




100 




120 




ns 


CAS hold time from RAS precharge 
(x4 -* xl set cycle) 


tpSCH 


10 




10 




10 




ns 



<§> HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • 



HM 53462 Series 



■ LOGIC CODE (FCO - 3 are AXO - AX3 in Logic Operation Set Cycle) 



FC3 


FC2 


FC1 


FCO 


LOGIC 


Symbol 


Write Data 

















Zero 











1 


AND1 


Di ' Mi 













AND2 


Di • Mi 








! 


1 


X4 -+X1 







1 







AND3 


Oi ' Ml 





1 




1 


THROUGH 


Di 





1 


! 





EOR 


TS ■ Mi + Di MT 

LSI ITU 1 ml 





1 


j 


1 


OR1 


Di+ Mi 












NOR 


Di Mi 


1 







1 


EN OR 


Di Mi+ Di Mi 












INV1 


Di 









1 


OR2 


BT+Mi 




1 







INV2 


Ml 




1 




1 


OR3 


Di + Mi 




1 







NAND 


DT+Ml 




1 




1 


1 


ONE 



SAM organization changes to 1024 x 1 
Logic operation mode reset 



Di : External Data-in 

Mi : The data of the memory cell 



• LOGIC OPERATION SET/RESET CYCLE (With CAS before RAS refresh) 



RAS 



• tRPC ICSK l 



CAS 



Address 



urn 



J tRH ^ 



tpSCH tcRP 



3r 



I/O 
(Input) 



zzzzx 



X //////////////// ZZZ 



. ////////////////////// 



W///////////////7T/ 



I/O 

(Output) 



^ ///////////////////////////////7 



•1) Logic code A0-A3 (A4-A7. don't care) 
•2) Write mask data 



Do not care 



HITACHI 

438 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 53462 Series 



■ LOGIC OPERATION MODE 
• EARLY WRITE CYCLE 

RAS 



CAS 



Address 



tH AH 



ROW 



I/O 

(Input) ' 



I/O 

(Output) " 



VALID 
Din 



HIGH Z 



»-» W W////////////7777777. 

Note) *1. When WE is 'high', the all data on the I/O can be written into the cell. 77TTA Do not care 

When WE is 'low', the data on the I/O are not written except for when I/O is 'high' 
at the falling edge of RAS. 

• DELAYED WRITE CYCLE 



RAS 



CAS u 



Address 



WE 



DT OE 



I/O 
(Input) 



X 



if 



X///////////////77 



///////////// 



U///////////////77 



i tun 

Xfr : x///////////// 



I'O 

(Output) 



NOTE 1) When WE is "H" level, all the data on 1/01-4 can be written into the memory cell. EZ3 Do not 

When WE is "L" level, the data on I/Os are not written except for when I/O = "H" at the falling edge of RAS. 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 439 



HM 53462 Series - 



• PAGE MODE WRITE CYCLE (Delayed Write) 



RAS 



CAS 



Address 



WE 



\ 



—y—mTTmr^nTTmr^jn///////// 



lf^^ KyTTTTTKfmh~\lh '/////// 

(us ,'"",1 „, s '"" (BS 

£. 7^^7iry777777fw/#y77///////A 



i o 

(Output) 



VALID 

Din 



DT OE 



Note) * 1. When WE is 'high', the all data on the I/O can be written into the cell. 

When WE is 'low', th e data on the I/O are not written except for when I/O is 'high' 
at the falling edge of RAS. 

• PAGE MODE WRITE CYCLE (Early Write) 



'minim 

V/ A Do not care 



CAS 



Address 



WE 



tASC ICAH 



~P — U-X **j COLUMN 

fezzzzSzzzzz^S 



fits fllH IHCWj lues „ . 



1/0 

(input) ; 



winning, 



-tw 

— tUH 



17777777, 



VALID 
Din 



zkzzzzzzs 



I/O 

(Output) l0TS 



— H * - fPTH 

^yir ^iiii/iiiiiiiiiiiiiiiiiiiiiiiiiiiinii, 

Note) * 1 . When WE is 'high', the all data on the I/O can be written into the cell. ZZ2 °° not c*™ 

When WE is 'low', th e data on the I/O are not written except for when I/O is 'high' 
at the falling edge of RAS. 



440 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 53462 Series 



■ DESCRIPTION 

1. LOGIC OPERATION MODE 

HM53462 has an internal logic operation unit 
which makes a process of graphics simple. The logic 
is determined in "Logic operation set/reset cycle", 
and the operation is executed in every write cycle 
succeeding to the logic operation set/reset cycle. In 
this mode the internal read-modify-write operation 
is executed and the cell data is converted into the 
new data given by the logic operation between Din 
and the old cell data. 

2. LOGIC OPERATION SET/RESET CYCLE 

A logic operation set/reset cycle is performed by 
bringing CAS and WE low when RAS falls (Fig. 1). 
The logic code and the bits to be masked are dater- 
mined respectively by AxO-3 state and 1/01-4 state 
at the falling edge of RAS. Furthermore, in this 
cycle CAS — before — RAS refresh operation is ex- 
ecuted, too. In the case of executing the conven- 
tional CAS - before - RAS refresh operation, WE 
must be high when RAS falls. 

2.1. Logic code 

The logic code is shown in Table 1 . When power 



is turned on, at least one logic reset cycle including 
write mask reset is required to initialize logic code. 
If the logic code is (Ax3, Ax2, Ax 1 , AxO) = (0, 0, 1 , 

1) , the SAM organization is changed converter (Fig. 

2) . In the case that the SAM organization is 
changed to 1,024 x 1, one data transfer cycle is 
needed to initialie the SAM selector. 

Once the SAM organization is changed to 1024 x 1, 
this code is maintained unless power is turned off. 

2.2. Write mask 

HMS3462 has two kinds of mask registers (register 
1 , 2). The register 1 is set by bringing WE low at 
the falling edge of RAS during the write cycle, and 
the mask data is available only in this cycle. The 
register 2 is set by level of I/O in the logic operation 
set/reset cycle, and the mask data is available until 
the next logic operation set/reset cycle. If the re- 
gister 1 is set during the current logic operation 
mode, the mask data of the register 1 is preferred 
(that of the register 2 is ignored) and the logic be- 
comes "THROUGH" only in this cycle (Fig. 3). 



RAS 



CAS ~\ 



Addres 



X 



I 



'V 



f 



FC0-FC3 



WE 



\ 



•L' 



X 

f 



I/O Mask Reg 2 



V/A Do not care 



Fig. 1 LOGIC OPERATION SET/RESET CYCLE 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 441 



HM53462 Series 

Table 1. LOGIC CODE (FCO - FC3 are AXO - AX3 in Logic Operation Sat Cycle) 











LOGIC 


Symbol 


Write Data 

















Zero 











1 


AND1 


Di Mi 








1 





AND2 


DT- Mi 








1 


1 


X4 -.XI 


_ 





1 








AND3 


Di Mi 





1 





1 


THROUGH 


Di 





1 


1 





EOR 


DT'Mi+ Di - Mi 





1 


1 


1 


OR1 


Di+ Mi 


1 











NOR 


DI ' Mi 


1 








1 


ENOR 


Di ■ Mi + DT • MI 







1 





INV1 


Di 







1 


1 


OR2 


DT+ Mi 




1 








INV2 


Mi 




1 





1 


OR3 


Di+ Mi 




1 


1 





NAND 


51+ Mi 




1 


1 


1 


1 


ONE 



Fin. 2 THE SHIFT WAY OF SAM DATA 

SAM Data Register 







1) By 4 mod* (SAM organization: 256 x 4) 

1st < 

SC 

si or 

SI 02^ 
SI 03~ 
SI 04" 




SAM organization changes to 1024 x 1 
Logic operation mode reset 



Di : External Data-in 
Mi : The data of the 



Serial I/O 



cell 





e ! a 




SI/01 












1 


t ; b 




SI/02 


» 










g i c 


SI 03 












1 

I 


h : d 




SI/04 





442 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



2) By 1 mod. (SAM organization: 1024 x 1) 

(sci- 



SC 

SI/01 



SI/03 
SI/04 





a X 


b X c 


X d 








High Z 










High-Z 






H,gh Z 



Fit. 3 EXAMPLE OF LOGIC OPERATION MODE 





RAS 
CAS 
WE 
I/Ol 

1/02 

1/03 
1/04 




Logic 



Logic operation 
set/reset cycle 



M ask reg.2 is set 
I 2,3 :M asked 
Assume that the 

logic is set to 

"AND1*. 



Write cycle 



•O'Write 



Masked 
Masked / — 

TWrite \. 



AND1 



Write cycle 



Masked r 



TWrite 
~\ -Q'Write 



THROUGH 



M ask reg.l is set, 
and valid only in 
this cycle. 
I 01.4:M asked 



Write cycle 



TWrite 



Masked 
Masked 



AND1 



Write cycle 



J 



~ \ " 0" Write 



Masked 



Masked 



TWrite 



AND1 



HITACHI 

Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



443 



— Preliminary 
131072-Word x 8-Bit Multiport CMOS Video RAM 

The HM538122 is a 1 -Mbit multiport video RAM equipped with a 
128-kword x 8-bit dynamic RAM and a 256-word x 8-bit SAM (serial 
access memory). 

Its RAM and SAM operate independently and asynchronously. It 
can transfer data between RAM and SAM and has a write mask 
function. 

It also provides logic operation mode to simplify its operation. In 
this mode, logic operation between memory data and input data can 
be executed by using internal logic-arithmetic unit. 

Features 

• Multiport organization 

Asynchronous and simultaneous operation of RAM and SAM 
capability 

RAM: 128-kword x 8-bit and SAM: 256-word x 8-bit 



Access time 

Cycle time 

Low power 
Active 



RAM: 100 ns/120 ns/150 ns max 
SAM: 30 ns/ 40 ns/ 50 ns max 
RAM: 190 ns/220 ns/260 ns min 
SAM: 30 ns/ 40 ns/ 60 ns min 



Standby 



RAM: 385 mW max 
SAM: 275 mW max 
40 mW max 
High-speed page mode capability 
Logic operation mode capability 

2 types of mask write mode capability 

Bidirectional data transfer cycle between RAM and SAM capability 
Real time read transfer capability 

3 variations of refresh (8 ms/512 cycles) 

RAS-only refresh 
CAS-before-RAS refresh 
Hidden refresh 
TTL compatible 



Ordering Information 



Type No. 



Access Time 



HM538122JP-10 100 ns 400-mil 
HM538122JP-12 120 ns 40-pin 
HM538122JP-15 150 ns Plastic SOJ (CP-40D) 



Pin Arrangement 



sc 

SI/OO [ 
SI/01 [ 
SI/02 [ 
SI/03 [ 
DT/OE[ 
l/OO [ 
I/01 [ 
I/02 [ 
I/03 £ 
Vcd [ 



NCf. 13 
RAS[ I" 
NC[ 15 
A8[ 16 
A6[ 17 
A5 C 18 
A4[ 19 
Vcc2[ 20 



\_y~Topvssi 

39 ] SI/07 
38 ] SI/06 
37 ] SI/05 
36 3 SI/04 
35 ]Sl 
34 ] 1/07 
33 ] 1/06 
32 ] 
31 

30 ; 



1 1/05 
] 1/04 
J V ss 2 
29 ]NC 
INC 
JCAS 
] NC 
] AO 
]A1 
]A2 
]A3 
21 ]A7 
' 



(Top View) 



Pin Description 


Pin Name 


Function 


A0-A8 


Address inputs 


I/0-V07 


RAM port data inputs/ 




outputs 


SI/O0- 


SAM port data inputs/ 


SI/07 


outputs 


RAS 


Row adress strobe 


CAS 


Column address strobe 


WE 


Write enable 


DT/OE 


Data transfer/Output 




enable 


SC 


Serial clock 


SE 


SAM port enable 


Vcc 


Power supply 


Vss 


Ground 


NC 


No connection 



This document contains information on anewproduct. Specifications and information 
contained herein are subject to change without notice. 



HITACHI 

444 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM5381 22 Series 



Block Diagram 



I/O 



WE 



SAM 



DT/OE 



255 



Dout 




Din 




Memory 


c 


Array 


i 

o 




o 


Row 





255 



A. - 



511 



o7^ 



Pointer 



| /I From 

i | Column Address 

' (SAM Start Address) 



^ Mi 



Register 



-cso 



Pin Function 

RAS (input pin): RAS is a basic RAM signal. It is 
active in low level and standby in high level. Row 
address and signals as shown in table 1 are input at the 



falling edge of RAS. The input level of those signals 
determine the operation cycle of the HM5381 22. 



Table 1. Operation Cycles of the HM538122 





Input Level at the Falling Edge of RAS 






Onpratinn Pvrlp 


CAS 


DT/OE 


WE 


SE 








H 


H 


H 


X 




RAM read/write 





H 


H 


L 


X 




Mask write 




H 


L 


H 


X 




Read transfer 




H 


L 


L 


H 




Pseudo transfer 




H 


L 


L 


L 




Write transfer 




L 


X 


H 


X 




CBR refresh 




L 


X 


L 




X 




Logic operation set/reset 




Note: x; 


Don't care. 













CAS (input pi n): Co lumn address is put into chip at the 
falling edge of CAS. CAS controls output impedance of 
I/O in RAM. 

A0-A8 (input pins): Row address is determined by 
A0-A8 level at thefalling edgeof RAS. Column address 
is de termined by A0-A7 level at the falling edge of 
CAS. In transfer cycles, row address is the address on 
the word line which transfers data with SAM data 
register, and column address is the SAM start address 
after transfer. 



WE (input pin): WE pin has two functions at the falling 
edge of RAS and after. When WE is low at the falling 
edge of RAS, the HM5381 22 turns to mask write mode. 
According to the I/O level at the time, write on each I/O 
can be masked. (WE level at the falling edge of RAS is 
don't care in read cycle.) When WE is high at the falling 
edge of RAS, a normal write cycle is executed. After 
that, WE switches read/write cycles as in a standard 
DRAM. In a transfer cycle, the direction of transfer is 
determined by WE level at the falling edge of RAS. 



<J|> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 445 



HM538122 Series 



When WE is low, data is transferred from SAM to RAM 
(data is written into RAM), and when WE is high, data 
is transferred from RAM to SAM (data is read from 
RAM). 

I/O0-I/O7 (input/output pins): I/O pins function as 
mask data at the falling edge of RAS (in mask write 
mode). Data is written only on high I/O pins. Data on 
low I/O pins are masked and internal data are retained. 
After that, they function as input/output pins as those 
of a standard DRAM. 

DT/OE (input pin): DT/OE pin functions as DT (data 
transfer) pin at the falling edge of RAS and as OE 
(output enable) pin after that. When DT is low at the 
falling edge of RAS, this cycle becomes a transfer 
cycle. WhenDTis high atthefallingedgeof RAS, RAM 
and SAM operate independently. 

SC (input pin): SC is a basic SAM clock. In a serial read 
cycle, data is output from an Sl/O pin synchronously 
with the rising edge of SC. In a serial write cycle, data 
on an Sl/O pin at the rising edge of SC is put into the 
SAM data register. 

SE (input pin): SE pin activates SAM. When SE is high, 
Sl/O is in the high impedance state in serial read cycle 
and data on Sl/O is not put into the SAM data register 
in serial write cycle. SE can be used as a mask for 
serial write because internal pointer is incremented at 
the rising edge of SC. 

SI/O0-SI/O7 (input/output pins) : Sl/Os are input/output 
pins in SAM. Direction of input/output is determined by 
the previous transfer cycle. When it was a read transfer 
cycle, Sl/O outputs data. When it was. a pseudo 
transfer cycle or write transfer cycle, Sl/O inputs data. 

Operation of HM538122 

Operation of RAM Port 

RAM Read Cycle 

(DT/OE high, CAS high, at the falling edge of RAS) 

Row address is entered at the RAS falling edge and 
column address at the CAS falling edge to the device 
as in standard DRAM. Then, when WE is high and DT/ 
OE is low while CAS is low, the selected address data 
is output through I/O pin. At the falling edge of RAS, 
DT/OE and CAS become high to distinguish RAM read 
cycle from transfer cycle and CBR refresh cycle. 



Address access time (tAA) and RAS to column address 
delay time (tRAD) specifications are added to enable 
high-speed page mode. 

RAM Write Cycle 

(Early Write, Delayed Write, Read-Modify-Write) 

(DT/OE high, CAS high at the falling edge of RAS) 

• Normal Mode Write Cycle (WE high at the falling 
edge of RAS) 



When CAS and WE are set low after RAS is set low, 
a write cycle is executed and I/O data is written at the 
selected addresses. When all 8 l/Os are written, WE 
should be high at the falling edge of RAS to distinguish 
normal mode from mask write mode. 

If WE is set low before the CAS falling edge, this cycle 
becomes an early write cycle and I/O becomes high 
impedance. Data is entered at the CAS falling edge. 

If WE is set low after the CAS falling edge, this cycle 
becomes a delayed write cycle. Data is input at the WE 
falling edge. I/O does not become high impedance in 
this cycle, so data should be entered with OE high. 

If WE is set low after tcwD (min) and tAWD (min) after 
the CAS falling edge, this cycle becomes a read-modify- 
write cycle and enables write after read to execute in the 
same address cycle. In this cycle also, to avoid I/O 
contention, data should be input after reading data and 
setting OE high. 

• Mask Write Mode (WE low at the falling edge of RAS) 

If WE is set low at the falling edge of RAS, the cycle 
becomes a mask write mode cycle which writes only to 
selected I/O. Whether or not an I/O is written depends on 
I/O level (mask data) at the falling edge of RAS. Then the 
data is written in high I/O pins and masked in low ones 
and internal data is preserved. This maskdata is effective 
during the RAS cycle. So, in high-speed page mode 
cycle, the mask data is preserved during the page 
access. 

High-Speed Page Mode Cycle 

(DT/OE high, CAS high at the falling edge of RAS) 

High-speed page mode cycle reads/writes the data 
of the same row address at high speed by toggling CAS 
while RAS is low. Its cycle time is one third of the random 
read/write cycle and is higher than the standard page 



446 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



HM538122 Series 



modecycle by 70-80%. This product is based on static 
column mode, therefore address access time (tAA), 
RAS to column address delay time (tHAo), and access 
time from CASprecharge (tACP)are added. In one RAS 
cycle, 256-word memory cells of the same row address 
can be accessed. It is necessary to specify access 
frequency within tRAs max (1 us). 

Transfer Operation 

The HM5381 22 provides the transfer cycle, pseudo 
transfer cycle, and write transfer cycle as data transfer 
cycles. These transfer cycles are set by driving DT/OE 
low at the falling edge of RAS. 

They have following functions: 

(1 ) Transfer data between row address and SAM data 
register (except for pseudo transfer cycle) 

(2) Determine direction of data transfer 

(a) Read transfer cycle: RAM -> SAM 

(b) Write transfer cycle: RAM <- SAM 

(3) Determine input or output of SAM I/O pin (Sl/O) 
Read transfer cycle: Sl/O output 
Pseudo transfer cycle, 

write transfer cycle: Sl/O input 



(4) Determine first SAM address to access (SAM start 
address) aftertransferring at column address. When 
SAM start address is not changed, neither CAS nor 
address need to be set because SAM start address 
can be latched internally. 

Read Transfer Cycle (CAS high, DT/OE low, WE high 
at the falling edge of RAS) 

This cycle becomes read transfer cycle by driving 
DT/OE low and WE high at the falling edge of RAS. The 
row address data (256 x 8 bit) determined by this cycle 
is transferred synchronously at the rising edge of DT/ 
OE. After the rising edge of DT/OE, the new address 
data outputs from SAM start address determined by 
column address. 

This cycle can access SAM serially even during 
transfer (real time read transfer). In this case, the timing 
tsoD (min) is specified between the last SAM access 
before transfer and DT/OE rising edge, and tsDH(min) 
between the first SAM access and DT/OE rising edge 
(see figure 1). 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 447 



HM5381 22 Series 



RAS 



CAS 



Address 



DT/OE 



V V V" 
j \ xi f\ Yi f \ 



Sl/O 



SAM Data Before Transfer 



Vi )( Yj + 1 



SAM Data After Transfer 



Figure 1. Real Time Read Transfer 

If read transfer cycle is executed, Sl/O becomes 
output state. When the previous transfercycle is either 
pseudo transfer cycle or write transfer cycle and Sl/O 
is in input state, uncertain data outputs after tRiz(min) 
after the RAS falling edge. Before that, input should be 
set high impedance to avoid data contention. 



Write Transfer Cycle (CAS high, DT/OE low, WE low, 
and SE low at the falling edge of RAS) 



Pseudo Transfer Cycle (CAS high, DT/OE low, WE 
low, and SE high at the falling edge of RAS) 

Pseudo transfer cycle is available for switching 
Sl/O from output state to input state because data 
in RAM isn't rewritten. This cycle starts when CAS is 
high, DT/OE low, WE low, and SE high, at the falling 
edge of RAS. The output buffer in Sl/O becomes high 
impedance within tsRz (max) from the RAS falling 
edge. Data should be input to Sl/O later than tsiD (min) 
to avoid data contention. SAM access becomes enabled 
after tsRD (min) after RAS becomes high. In this cycle, 
SAM access is inhibited during RAS low, therefore, SC 
should not be raised. 



Write transfer cycle can transfer a row of data input 
by serial write cycle to RAM. The row address of data 
transferred into RAM is determined by the address at 
the falling edge of RAS. The column address is specified 
as the first address to serial write after terminating this 
cycle. Also in this cycle, SAM access becomes enabled 
after tsRD (min) after RAS becomes high. SAM access is 
inhibited during RAS low. In this period, SC should not 
be raised. 

SAM Port Operation 

Serial Read Cycle 

SAM port is in read mode when the previous data 
transfer cycle is read transfer cycle. Access is 
synchronized with SC rising, and SAM data is output 
from Sl/O. If SE is set high Sl/O becomes high impedance 
and internal pointer is incremented at the SC rising 
edge. 



HITACHI 

448 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Serial Write Cycle 

If previous data transfer cycle is pseudo transfer 
cycle or write transfer cycle, SAM port goes into write 
mode. In this cycle, Sl/Odata is programmed into data 
register at the SC rising edge like in the serial read 
cycle. If SE is high, Sl/O data isn't input into data 
resistor. Internal pointer is incremented according to 
the SC rising edge, so SE high can mask data for SAM. 

Refresh 

RAM Refresh 

RAM, which is composed of dynamic circuits, 
requires refresh to retain data. Refresh is performed 
by accessing all 51 2 row addresses every 8 ms. There 
are three refresh cycles: (1) RAS-only refresh cycle, 
(2) CAS-before-RAS (CBR) refresh cycle, and (3) 
Hidden refresh cycle. Besides them, the cycles which 
activate RAS such as read/write cycles or transfer 
cycles can refresh the row address. Therefore, no 
refresh cycle is required for accessing all row addresses 
every 8 ms. 

RAS-Only Refresh Cycle: RAS-only refresh cycle is 
performed by activating only RAS cycle with CAS fixed 
to high by inputting the row address (= refresh address) 
from external circuits. In this cycle, output is high- 
impedance and power dissipation is less than that of 
normal read/write cycles because CAS internal circuits 
don't operate. To distinguish this cycle from data 
transfer cycle, DT/OE should be high at the falling 
edge of RAS. 

CBR Refresh Cycle: CBR refresh cycle is set by 
activating CAS before RAS. In this cycle, refresh 
address need not to be input through external circuits 
because it is input through an internal refresh counter. 
In this cycle, output is in high impedance and power 
dissipation is lowered like in RAS-only refresh cycles 
because CAS circuits don't operate. To distinguish this 
cycle from logic operation set/reset cycle, WE should 
be high at the falling edge of RAS. 

Hidden Refresh Cycle: Hidden refresh cycle 
performs refresh by reactivating RAS when DT/OE 
and CAS keep low in normal RAM read cycles. 

SAM Refresh 

SAM parts (data register, shift register, selector), 



HM538122 Series 

organized as fully static circuitry, don't require refresh. 

Logic Operation Mode 

The HM538122 supports logic operation capability 
on RAM port. It performs logic operations between the 
memory cell data and input data in logic operation 
mode cycle, and writes the result into the memory cell 
(read modify write). This function realizes high speed 
raster operations and simplifies peripheral circuits for 
raster operations. 

Logic Operation Set/Reset Cycle 

(CAS and WE Low at the falling edge of RAS) 

In logic operation set/reset cycle, the following 
operations are performed at the same time; 1 . Selection 
of logic operations and logic operation mode set/reset, 
2. Mask data programming, 3. CAS-before-RAS refresh. 

Figure 2 shows the timing for logic operation set/ 
reset cycle. This cycle starts when CAS and WE are low 
at the falling edge of RAS. In this cycle, logic operation 
codes and mask data are programmed by row address 
and I/O pin at the falling edge of RAS respectively. 
When write cycle is performed after this cycle, the logic 
operation write cycle starts. In the logic operation 
mode, the specification of cycle time is longer than that 
of normal mode because read-modify-write cycle is 
performed internally. In this cycle, logic operation codes 
and mask data programmed are available until 
reprogrammed. In normal mode, mask data is available 
only for one RAS cycle. Here, the mask data 
programmed in normal mode is named as "temporary 
mask data" and the one programmed in logic operation 
set/reset cycle is named as "mask data". 

(l)Selection of logic operations and logic operation 
mode set/reset 

Table 2 shows the logic operations. One operation 
is selected among sixteen ones by combinations of 
A0-A3 levels at the falling edge of RAS. (A4-A8 are 
Don't care.) Logic operation codes (A3, A2, A1 , AO) = 
(0,1 ,0,1 ) resets the logic operation mode. When write 
cycle is performed after that, normal write cycle starts. 
However, even in this case, mask data is still available. 
I/O should be at high level at the falling edge of RAS in 
logic operation set/reset cycle when mask data is not 
used. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



449 



HM538122 Series 



(2)Mask data programming 

High/low level of I/O at the falling edge of RAS 
functions as mask data. When I/O is high, the data is 
written in write cycle. When I/O is low, the input data is 



masked and the same memory cell data remains. 
Mask data, programmed in this cycle, is available 
until reprogrammed. It is advantageous when the 
same mask data continues. 



RAS 



I 



A0-A3 



WE 



I/O0-I/O3 



Logic Code 



/ 




Figure 2. Logic Operation Set/Reset 
Table 2. Logic Code 



Logic Code 







A3 


A2 


Al 


AO 


Symbol 


Write Data 


Notes 














Zero 










° 


o 


1 


AND1 


Di-Mi 










1 





AND2 


DT-Mi 


Logic operation mode set 








1 


1 




Mi 







1 








AND3 


Di-MT 







1 





1 


THROUGH 


Di 


Logic operation mode reset 





1 


1 





EOR 


DiMi+DiMi 







1 


1 


1 


OR1 


Di+Mi 















NOR 


Di-Mi 










1 


ENOR 


DiMi+DiMi 









1 





INV1 


Di 


Logic operation mode set 







1 


1 


OR2 


Di+Mi 






1 








INV2 


Mi 






1 





1 


OR3 


Di+Mi 






1 


1 





NAND 


Di+Mi 






1 


1 


1 


One 


1 





Notes: Di; External data-in 

Mi; The data of the memory cell 



HITACHI 

450 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538122 Series 







Logic operation 
set/reset cycle 


Write cycle 


Write cycle 


Write cycle 


Write cycle 


RAT 
CA5 
WE 

l/OO 

l/Ol 
I/02 

I/03 


\ 


\ / 


\ / 


\ 1 


\ / 


r 












-L" / 




•H"\ / 


A / 


-H" \ / 
















"H"\ 


/ 


,\ / 


\ r 






"CTWrite 










A 


Masked / 


"VWrite 


\ "0"Write 










/ 

"L" 


Masked 


■■1 "Write 


Masked 
Masked 


Masked 


Masked / 


\ "CTWrite 


/ Masked 








Masked 


"O'Write 






"H" 


\ 

'T'Write \ 


/ 

/ "1 "Write 










Log 


c 




ANDI 


THROUGH 


AND1 


ANDI 




Mask data is set. 
I/01, 2 Masked 
Assume that the 
logic is set to 
"ANDI." 




Temporary mask 
data is set, and 
valid only in this 
cycle.l/O 0, 3: 
Masked (I/04- 
1/07 are also ope- 
rated similarly.) 









Figure 3. 2 Types of Mask Write Function and Logic Operation Function 



Also, temporary maskdata is programmed by falling 

WE at the falling edge of RAS in logic operation mode 
cycleafter maskdata is programmed in logic operation 
set/reset cycle. In this case, temporary mask data is 
available only for one cycle. 

Logic operation is reset during temporary mask 
write cycle. It means that external input data is written 
into I/O when temporary mask data is set. Figure 4 
shows write mask and logicoperations.Thesefunctions 



are useful when RAM port is devided into frame buffer 
area and data area, asthey save the need to reprogram 
logic operation codes and mask data. 

Write Cycle in Logic Operation Mode 
(Early Write, Delayed Write, Page Mode) 

Write cycle after logic operation set cycle is logic 
operation mode cycle. In this cycle, the following read- 
modify-write operation is performed Internally. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 451 



HM538122 Series 



(1) Reading memory data in given address into internal memory data 

bus. (3) Writing the result of (2) into address given by (1) 

(2) Performing operation between input data and 



Read 1 -word source data 



Read 1-word destination data 

I 



Execute logic operation between source data and 
destination data 



Write the result of operation into the destination 
address 



Execute logic operation set/reset cycle 



Read 1 -word source data 



Write read data into the destination 



(a) Normal Mode (b) Logic Operation Mode 

Figure 4. Sequence of Raster Operation 



Figure 4 shows sequence of raster operation. Raster 



executed in one write cycle of logic operation mode. It 



makes raster operation faster and simplifies peripheral 
operation which needs 3 cycles (destination read, , , , 

. . .. . . , , , hardware for raster operation. 

operation, destination write in normal mode can be r 



Absolute Maximum Ratings 



Item 




Symbol 


Rating 


Unit 


Terminal voltage* 1 




Vt 


-1.0 to +7.0 


V 


Power supply voltage ' 1 




Vcc 


-0.5 to +7.0 


V 


Power dissipation 




Pt 


1.0 


w 


Operating temperature 




Topr 


to +70 


°c 


Storage temperature 




Tstg 


-55 to +125 


°c 


Note: *1. Relative to Vss. 











Recommended DC Operating Conditions (Ta 


= to +70°C) 






Item Symbol Min 


Typ 


Max 


Unit 


Supply voltage* 1 Vcc 4.5 


5.0 


5.5 


V 


Input high voltage * 1 Vm 2.4 




6.5 


v 


Input low voltage" 1 Vil -0.5* 2 




0.8 


V 



Notes: *1. All voltages referenced to Vss. 
*2. -3.0 V for pulse width < 10 ns. 



HITACHI 

452 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 



DC Characteristics (Ta = to +70°C, Vcc = 5 V ±10%, Vss = V) 





HM538122 


HM538122 


HM538122 




Test Conditions 


Item Symbol 




10 


-12 




■15 


Unit 






RAM port SAM port 




Min 


Max 


Min 


Max 


Min 


Max 




Operating Icci 




70 




60 




50 


mA 


RAS.CAS SC = Vil,SE = Vih 


current 
















cycling 


Ice? 




120 


— 


100 




80 


mA 


tRC = Min SE = Vil, SC cycling 

fez" 1 /"* — rtfliTI 
lot^U — J VI ill 


Standby current \cci 




7 




7 




7 


mA 


RAS.CAS SC = Vil, SE=Vih 
= Vm 


Ices 




sn 


— 


40 




"}ft 


mA 


SE = Vil, SC cycling 
tscc — Min 


R AS -only lea 




60 




50 




40 


mA 


RAS cycling SC = Vn.,SE = Vw 


refresh current 
















LAj — VIH 


ICC9 




1 in 

11U 


— 


90 




/o 


mA 


tRC = Min SE = Vil, SC cycling 

lot. 1. — IVUIl 


Page mode Ice* 




65 




55 




45 


mA 


CAS cycling SC = Vil, SE = Vih 


current 
















D AC _ Un 
RAo — V IL 


Iccio 




115 


— 


95 




75 


mA 


Irc = Min SE = Vil, SC cycling 
tscc — N4in 


CAS-before- Ices 




60 




50 




40 


mA 


RAS cycling SC = Vil, SE = Vw 


pit refresh 
















Irc = Min 


current Icci 1 




110 




90 




70 


mA 


SE = Vil, SC cycling 

LbCC — iviin 


Data Icc6 




90 




Oft 




90 


mA 


RAS.CAS SC = Vil,SE = Vm 


transfer 
















cycling 


current Icci 2 




125 




1 ZD 




125 


mA 


»c = Min SE = Vil, SC cycling 
tscc = Min 


Tnnut leakage Ti 1 


1ft 

— l\J 


in 


-10 


10 


1ft 


1 ft 






current 


















Output leakage Ilo 


-10 


10 


-10 


10 


-10 


10 


aA 




current 


















Output high Voh 


2.4 




2.4 




2.4 




V 


Ioh = -2 mA 


voltage 


















Output low Vol 




0.4 




0.4 




0.4 


V 


Iol = 4.2 mA 


voltage 



















Capacitance (Ta 


= 25°C, Vcc 


=5V, f = 1 MHz, Bias: Clock, I/O = 


Vcc, address = Vss) 




Item 


Symbol 


Min Typ 


Max 


Unit 


Address 


Cn 




5 


PF 


Clock 


Cl2 




5 


PF 


I/O, svo 


Cvo 




7 


PF 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 453 



HM538122 Series 



AC Characteristics (Ta = to +70°C, Vcc = 5 V ±10%, Vss = V)* 1 - 
Test Conditions 

Input rise and fall time: 5 ns 

Output load: See Figures 

Input timing reference levels: 0.8 V, 2.4 V 
Output timing reference levels: 0.4 V, 2.4 V 



I/O 



Output Load (A) 



„=-2mA 



I ot = 4.2mA 



■m 



Output Load (B) 



l 0H =-2mA 



l OL = 4.2mA 



SI/0 



T 



50pF M 



777 



Note: *1. Including scope & jig. 



Common Parameter 



Item 


Symbol 


HM538122-10 


HM538122-12 


HM538122-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Random read or write cycle ti 


ne tec 


190 




220 




260 


— 


ns 




RAS precharge time 


tep 


80 




90 




100 




ns 




RAS pulse width 


Iras 


100 


10000 


120 


10000 


150 


10000 


ns 




CAS pulse width 


tCAS 


30 


10000 


35 


10000 


40 


10000 


ns 




Row address setup time 


tASR 

















ns 




Row address hold time 


tRAII 


15 




15 




20 




ns 




Column address setup time 


tASC 

















ns 




Column address hold time 


tCAII 


20 




20 




25 




ns 




RAS to CAS delay time 


tRCD 


25 


70 


25 


85 


30 


110 


ns 


"5,-6 


RAS hold time 


tRSH 


30 




35 




40 




ns 




CAS hold time 


tCSH 


100 




120 




150 




ns 




CAS to RAS precharge time 


tCRP 


10 




10 




10 




ns 




Transition time (rise to fall) 


tr 


3 


50 


3 


50 


3 


50 


ns 


•8 


Refresh period 


tREF 




8 




8 




8 


ms 




DT to RAS setup time 


tDTS 

















ns 




DT to RAS hold time 


IDTH 


15 




15 




20 




ns 




Data-in to OE delay time 


tDZO 

















ns 




Data-in to CAS delay time 


tDZC 

















ns 





HITACHI 

454 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM5381 22 Series 



Read Cycle (RAM), Page Mode Read Cycle 



T 

Hem 


Symbol 


HM538122-10 


HM538122-12 


HM538122-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






7 : - mj, 

Access time from RAS 


tRAC 




100 




120 




150 


ns 




Access time from CAS 


tCAC 


— 


30 




35 




40 


ns 


•3. '5 


Access time from OE 


tOAC 


— 


30 




35 


— 


40 


ns 


• 3 


Address access time 


tAA 




45 




55 




70 


ns 




Output buffer turn off delay 
referenced to CAS 


torn 





25 





30 





40 


ns 


•7 


Output buffer turn off delay 
referenced to OE 


tOFF2 





25 





30 





40 


ns 


"7 


Read command setup time 


tRCS 





— 





— 





— 


ns 




Read command hold time 


UtCH 





— 





— 







— 


ns 


•12 


Read command hold time 
referenced to RAS 


tRRH 


10 


— 


10 


— 


10 


— 


ns ' n 


RAS to column address 
delay time 


DtAD 


20 


55 


20 


65 


25 


80 


ns 


•5.«6 


Page mode cycle time 


tPC 


55 




65 




80 




ns 




CAS precharge time 


tCP 


10 




15 




20 




ns 




Access time from CAS precharge 


tACP 




50 




60 




75 


ns 
























Write Cycle (RAM), Page Mode Write Cycle 


















Item 


Symbol 


HM538122-10 


HM538122-12 


HM538122-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Write command setup time 


twcs 

















ns 


•» 


Write command hold time 


twai 


25 




25 




30 




ns 




Write command pulse width 


twp 


15 




20 




25 




ns 




Write command to RAS lead time 


tRWL 


30 




35 




40 




ns 




Write command to CAS lead time 


tCWL 


30 




35 




40 




ns 




Data-in setup time 


IDS 

















ns 


■10 


Data-in hold time 


tDH 


25 




25 




30 




ns 


•10 


WE to RAS setup time 


tws 

















ns 




WE to RAS hold time 


tWH 


15 




15 




20 




ns 




Mask data to RAS setup time 


tMS 

















ns 




Mask data to RAS hold time 


tMH 


15 




15 




20 




ns 




OE hold time referenced to WE 


tOEH 


10 




15 




20 




ns 




Page mode cycle time 


tPC 


55 




65 




80 




ns 




CAS precharge time 


tCP 


10 




15 




20 




ns 





HITACHI 

Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 455 



HM538122 Series 



Read-Mod Hy-Write Cycle 



Item 




HM538122-10 


HM538122-12 


HM538122-15 


Unit 
unit 






















Rparl moHiFv wrifp rvrlp limp 


tRWC 


255 




295 




350 




ns 




P AC ni i1 cp wiHth 

IV /AO UUI>C WiULll 




165 


10000 


195 


10000 


240 


10000 






CAS to WE del av 


tCWD 


65 




75 




90 




ns 


•9 


Pnlnmti arlHrpcc tf\ A^/F HpIsiv 




80 




95 




120 






•9 


IU Udld-111 U<Jldy L1IUC 




25 




30 




40 








Access time from RAS 


tAC 




100 




120 




150 


ns 


•2.'3 


Access time from CAS 


tCAC 




30 




35 




40 


ns 


•3*5 


Arc**ss timp frnm OP 

riVA^Ad LllllV 11 Will 


tOAC 




30 




35 




40 


ns 


•3 


Address access time 


tAA 




45 




55 




70 


ns 


"3."6 


RAS to column address delay 


tRAD 


20 


55 


20 


65 


25 


80 


ns 


•5,-6 


Output buffer turn-off delay 
referenced to OE 


tOFF2 


o 


25 





30 





40 


ns 


RpaH frtrnmiiTiH cphm timp 
ACatJ v > \ l 1 J J ] a i 1 vl «7dUL> illllv 


"tecs 


o 




o 




o 


= — 


ns 




^Vntp mmmarH to RAS IpaH timp 


mwL 


30 




35 





40 




ns 




Write command to CAS lead time 


tCWL 


30 




35 




40 




hs 




^V^ilp mmmafiH nul^p wiHlh 




15 




90 




95 




ns 




L>did-iii setup LUTie 


tDS 







o 




o 




ns 


•10 


Data-in hold time 




25 


— 


25 


— 


30 


— 


ns 


•to 


WE to RAS setup time 


tws 

















ns 




WE to RAS hold time 


twn 


15 




15 




20 




ns 




Mask data to RAS setup time 


tMS 

















ns 




Mask data to RAS hold time 


tMH 


15 




15 




20 




ns 




OE hold time referenced to WE 


tOEH 


10 




15 




20 




ns 




Refresh Cycle 




















Item 


Symbol 


HM538122-10 


HM538122-12 


HM538122-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






CAS setup time 
(CAS-before-RAS refresh) 


tCSR 


10 




10 




10 




ns 




CAS hold time 
(CAS-before-RAS refresh) 


tCIIR 


20 




25 




30 




ns 






RAS precharge to CAS hold time 


terc 


10 




10 




10 


— 


ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538122 Series 



Transfer Cycle 



Item 


Symbol 


HM538122-10 


HM538122-12 


HM538122-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






WE to RAS setup time 


tws 




















ns 




WE to RAS hold time 


twn 


15 





15 





20 




ns 




SE to RAS setup time 


tES 




















ns 




SE to RAS hold time 


tEH 


15 





15 





20 


— 


ns 




RAS to SC delay time 


t-SRD 


25 


— 


30 


— 


35 


— 


ns 




SC to RAS setup time 


IRS 


30 




40 




45 




ns 




DT hold time from RAS 


tRDH 


80 





90 





110 





ns 




DT hold time from CAS 


tCDH 


20 


— 


30 


— 


45 


— 


ns 




Last SC to DT delay time 


tSDD 


5 




5 




10 




ns 




First SC to DT hold time 


tSDH 


TBD 


— 


TBD 


— 


TBD 


— 


ns 




DT to RAS lead time 


tDTL 


50 




50 




50 




ns 




DT hold time referenced to 
RAS high 


tDTlttt 


20 


— 


25 


— 


30 


— 


ns 




DT precharge time 


tDTP 


30 


— 


35 


— 


40 


— 


ns 




Serial data input delay time 
from RAS 


tSID 


50 





60 





75 





ns 




Serial data input to RAS 
delay time 


tSZR 





10 


— 


10 





10 


ns 




Serial output buffer turn-off 
delay from RAS 


tSRZ 


10 


50 


10 


60 


10 


75 


ns 




RAS to Sout (Low-Z) delay time 


tRLZ 


5 


— 


10 


— 


10 


— 


ns 




Serial clock cycle time 


tscc 


30 




40 




60 




ns 




Access time from SC 


tSCA 




30 




40 




50 


ns 


•4 


Serial data out hold time 


tSOH 


7 




7 




7 




ns 


•4 


SC pulse width 


tsc 


10 




10 




10 




ns 




SC precharge width 


tSCP 


10 




10 




10 




ns 




Serial data-in setup time 


tsis 

















ns 




Serial data-in hold time 


tSIH 


15 




20 




25 




ns 




Serial Read Cycle 




















Item 


Symbol 


HM538122-10 


HM538122-12 


HM538122-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Serial clock cycle time 


tscc 


30 




40 




60 




ns 




Access time from SC 


tSCA 




30 




40 




50 


ns 


•4 


Access time from SE 


tSEA 




25 




30 




40 


ns 


•4 


Serial data-out hold time 


tSOH 


7 




7 




7 




ns 


•4 


SC pulse width 


tsc 


10 




10 




10 




ns 




SC precharge width 


tSCP 


10 




10 




10 




ns 




Serial output buffer turn-off 
delay from SE 


tSEZ 





25 





25 





30 


ns 


•7 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 4 57 



HM538122 Series 



X 



Serial Write Cycle 



Item 




HM538122-10 


HM538122-12 


HM538122-15 Unit Note 






Min 


Max 


Min 


Max 


Min 


Max 




Serial clock cycle time 


tscc 


JU 




Aft 




Kft 




ns 


SC pulse width 


tsc 


1 a 
10 




1 A 

10 




1 a 
10 




ns 


SC prechargc width 




i a 




i a 
10 




1 A 
10 




ns 


Ckf*ria1 rlntn in cphin timp 

iJCI lal Uctld III JCIUU L111IC 



















ns 


Serial data-in hold time 


tSIH 


15 




20 




25 




ns 


Serial write enable setup time 


tsws 

















ns 


Serial write enable hold time 


tSWH 


30 




35 




50 




ns 


Serial write disable setup time 


tswis 

















ns 


Serial write disable hold time 


tSWIH 


30 




35 




50 




ns 


Logic Operation Mode 


Item 


Symbol 


HM538122-10 


HM538122-12 


HM538122-15 


Unit Note 






Min 


Max 


Min 


Max 


Min 


Max 




CAS hold time 
(logic operation set/reset cycle) 


tPCUR 


90 




100 




120 




ns 


RAS pulse width in write cycle 


tRFS 


140 


10000 


165 


10000 


200 


10000 


ns 


CAS pulse width in write cycle 


tCFS 


60 




70 




80 





ns 


CAS hold time in write cycle 


tFCSH 


140 




165 




200 




ns 


RAS hold time in write cycle 


tTRSH 


60 




70 




80 




ns 


Write cycle time 


tFRC 


230 




265 




310 




ns 


Page mode cycle time 
(write cycle) 


IFPC 


85 




100 




120 




ns 



Notes: *1. AC measurements assume tT = 5 ns. 

*2. Assume that tRCD < ircd (max) and wad < tRAD (max). 

If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC e 
*3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 
*4. Measured with a load circuit equivalent to 2 TTL loads and 50 pF. 
*5. When tRCD > tRCD (max) and irad < tRAD (max), access lime is specified by tCAC. 
*6. When tRCD < tRCD (max) and tRAD > tRAD (max), access time is specified by tAA. 

*7. lOFF(max)is defined as the time at which the output achieves the open circuit condition (VoH-200mV, Vol+ 200 mV). 
*8. Vni (min) and Vil (max) are reference levels for measuring timing of input signals. Transition times are measured between 
Vih and Vil. 

*9. When twes > twes (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 
When tAWD > tAWD (min) and tcwo > tcwo (min), the cycle is a read-modify-write cycle; the data of the selected address 
is read out fr om a data output pin and input data is written into the selected address. In this case, impedance on I/O pins is 
controlled by OE. 

*10. These parameters are referenced to CAS falling edge in early write cycles or to WE falling edge in delayed write or read- 
modify-write cycles. 

* 1 1. After power-up, pause for 100 lis ormore and execute at least 8 initialization cycles (normal memory cycles or refresh cycles), 

then start operation. 
*12. If either tRCH or irrh is satisfied, operation is guaranteed. 



HITACHI 

458 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538122 Series 



Timing Waveforms 
Read Cycle 



RAS 



CAS 



> 


t„o 




tciM 





Address 



v 



'"hH 

wzm 



Column 



I/O 
Output) 



i/o 7 

(Input) 



t..c 



DT/OT 



< 




Valid 



mmmh, mum 



Early Write Cycle 



RAS 



CAS 



'A 




I/O 
(Output) 



DT/OT 



Higri-Z 



^////////////////////7MM7a 

7/// : Don't care 



Note: *1. When WE is high level, all the data on UOs can be written into the mem ory ce ll. When WE is low level, the data on 170s are 
not written except for the case that the I/O is high at the falling edge of RAS. 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 4 59 



HM538122 Series 
Delayed Write Cycle 



RAS 



CAS 



WE 



DT/OE 



to 



s; 



I/O 
(Output) - 





2ZZZS 



! Mill i lllllll mlllliim 



High-Z 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

Read-Modify-Write Cycle 



RAS 



US 




WE 



I/O 
(Input) 



3^ 



I/O 
(Output) 



DT/OE 




/ 



QT^T tfflTM///////////// 



WZhJ 



)' Valid \ 
tZ V Pout / - 



W///////M 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

460 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Page Mode Read Cycle 



RAS 
CAS 

Address 
W 



Row 



mm. 



I/O 
(Output) 

I/O " 
(Input) 



T 




U-Jt, C! t, CH J ^J-LJt,,;,, (_t»CK U-t,„ I t.CB K- j'"" 



Valid \ 
Pout , * 



Valid J y 
\ Pout , f 



t OT S toTT |!°* C t FF2 tpiO | [tO*C ' OF F 2 'OZO I 

//F H y/f 1 ^77^ ^77^ ' 



Valid 
Dout 



> 



tOPFl 

////// 



?Z^\ '■ Don't care. 



Page Mode Write Cycle (Early Write) 



RAS 



CAS 



V 



I/O 



'.sc t„„ t>sc I cm 



'Han * 431, " n H*e*i 



Valid 
Din 



Valid 
Din 



W7777T, 



High-Z 



TO // V//////////////////////////////////// 

K^Zl : Oon't care. 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 461 



HM538122 Series 



Page Mode Write Cycle (Delayed Write) 



RA5 



CAS 



Address 



ly^ Wrrrr^ jTTTT^iT / /////// / 

t WJ t W M '* —I * CWL f- H *C*L p- t C *t I 




I/O 
(Output) 



DT/OT 



■ ^77777> , 



//////////. 



High-Z 



? *//////////, 



V////////// 

rVfra : Don't care. 



Note: *1. When WE is high level, all the data on I/Os can be written into the memory cell. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

RAS-Only Refresh Cycle 



RAS 



CAS 7 



Address 



to rn 



if 



vn ////// 



I/O 
(Output) 



I/O 
(Input) 



DT/OT 



zr 



: </////////////////////// 



<t//////////////////////, 

t DTH 

^/////////7/7/7/7/7/7/ 



: Don't care. 



HITACHI 

462 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538122 Series 



CAS-Before-RAS Refresh Cycle 



RAS 



/' % 



CAS 



v 



//////////////////// ///7777 
- V/////////////////////////, 



(Input) 

I/O 
(Output) 



High-Z 



— 7///////////////////// 

Y7A '■ Don't care. 



Hidden Refresh Cycle 



RAS 



CAS 7 




Address 



WE 



7A 



I/O . 
(Output) 



DT/OE 



t DTK 



(Input) 



W ^////////////////////A 



Valid Data Out 



> 



High-Z 



ii) '■ K^Zl : Don't care. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



463 



HM538122 Series 



Read Transfer Cycle (I)* 1 * 2 



I/O 







V/////// 

High-Z 




liiiiimmi 




////////) 


///////// 

- 




m/tin, 


V//// 


-\ , 


,i, •••• . 


la 


' \ 


f////A 




- 1 I -New Ro» 



F/y^ : Don't care 



Notes: *1. Wh en the previous data tr ansfe r cycle is a read transfer cycle, it is defined as read transfer cycle (1). 
*2. SE is in low level. (When SE is high, SI/O becomes high impedance.) 

*3. CAS and SAM start address don't need to be specified every cycle if SAM start address is not changed. 



Read Transfer Cycle (2) *' " 2 



w < 3 - 



I/O 
(Output) 



WmTTi TTTJ 



7777T7T 



^ (///////////////////////////// 



£ V/7///////////7//////////////// ZZ 



(Input) 

ton 

BT/OT J|~ 



E 



Sl/O 
(Output) 



(Input) 




== ^/////////)/7/4 a ^ 



r"///l : Don't care 

KXXI : Inhibit rising transient 



Notes: *1. When the previous dau transfer cycle is a write or pseudo transfer cycle, it is defined as read transfer cycle (2). 
*2. SEis in low level. (When 'SE is high, SI/O becomes high impedance.) 

*3. CAS and SAM start address don't need to be specified every cycle if SAM start address is not changed. 



HITACHI 

464 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 



Pseudo Transfer Cycle 



WE 



SI/0 
(Input) 



SI/0 
(Oulpul) 





'"* 








I.e. 


tniM 






t.ll 

JT 




fw \fllllll 




If 

//////////////// 




t. H 




// 




i 


*///////////////////////////////// 
, i— 1 1 




1 


'II III 1 1 If l.l ' 1 II 


////////////////// 


t 




viiiniiniiiii 


/////////////// 




{w 








:.r- 






i - 1_ 


: Don t care 

: Inhibit rising transient 



Note: *1. CAS and SAM start address don't need to be specified every cycle, il" SAM start address is not changed. 

Write Transfer Cycle 



CA5 



Address 'M Row 



BT/OT 



KZZ 



3p* 



//.'////;// '/ 



'yiIlllllllllHllll)llll)!"Wni:: 



if^iniiiiiiiiiriininnnniiirmr, 




Sl/O 
(Input) 



SI/0 
(Output) 



S / ////////////)f^ = k zZZZZK 



l/J^j : Don't care 

: Inhibit rising transient 



Note: •!. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 



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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 4 65 



HM538122 Series — 

Serial Read Cycle 



RAS 



w zzzzzzzzzzzzzzzzzzzzzzt — i llinium 



SE 



_t ce- 
rt,, 



J 



Sl/O V7T7V Valw ' \. 

(Output) Ml V S . Sout y 




:n+1)\ j' (n + Z) \ / 



Valid 
Sout 



^zzx 



Valid 
Sout 



E22 : Don't care. 



Serial Write Cycle 



RAS 

DT/OE 
SE 
SC 





■ RAS 
t DTK 


1 


t 


ummmmimmt 





: 1 — = 








>SWH-»- 

' ^ S 
a!id " £/ 


sec . 


— — isws — » 
-4 tscc , 
i 1 scp 

/ ,/V"Va 


hto r 




Sin(„-,).?V //////////. S 


tsiH 



KZ^I : Don't care. 



Notes: 1. When SE is high level in a serial write cycle, data is not written into SAM, however, the pointer is increrm 
2. Address is accessed next to address 255. 



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466 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Logic Operation Set/Reset Cycle 



ess 



I/O 
(Input) 



_/t BPC 



22 



tws 



si 



. ////////////////////////. 



I/O 
(Output) 



High-Z 



DT/OE 



/////////////////////////////////// 

: Don't care. 







Notes: 1. Logic code A0-A3 
2. Write mask data 



HM538122 Series 



Logic Operation Mode Timing Waveforms 
Early Write Cycle 



T&5 



CAS 



Address 



tftSR 




*FRC 



t 



■/ 



Column 



I/O 
(Input) 



to 



I/O 
(Output) 



CT/OT 



tot 



I///////////, 



tpH 



Valid Din 




zzzzzz 



High-Z 



W V/////////////////777777777 



: Don't care. 



Note: *1. When WE is high, all the data on I/Os can be written into the mem ory cell. When WE is low, the data on I/Os are not written 
except for the case that the I/O is high at the falling edge of RAS. 

Delayed Write Cycle 



CAS t 



4^ 



BT/OT 



(//////////////// 



:czzzz 



i/o 7 

(Input) ' 

I/O 
(Output) 



mmmnnm 



M inium 



High-Z 



fy^ l : Don't care. 



Note: * 1 . When WE is high, all the data on I/Os can be written into th e mem ory cell. When WE is low, the data on I/Os are not written 
except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

468 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538122 Series 



Page Mode Write Cycle (Delayed Write) 



RAS 



CAS 



Address 



WE 



(Input) 



I/O 
(Output) 



■ I L CFS 








DT/OE 







1 







//////;> 

Oh t os 


Ioh Us U» 


t»Wl 

7//////// 


•> 




mm 




y//////// 



High-Z 



yniiiii: 

YZA '■ Don't care. 







Note: *1. When WE is high, all the data on I/Oscan be written into the memory cell. When WE is low, the data onl/Os are not written 
except for the case that the I/O is high at the falling edge of RAS. 

Page Mode Write Cycle (Early Write) 



WE 



I/O 
(Input) 

I/O 
(Output) 





IFHC 
t BFS 

t 


-•'1 




— 

l.co 


FCSh f- 

' CF S 


1 


PC 

t C Fi 


H 1 F ASH 


tcrs 






t»H : 

Use 


tc.» 


to, y 
t.sc 


. ,1 

t C *H 


1 

t 




tarn 


T 


^| Row 




h^l III 


M ™y /////// 






i-t wes 


t WCH , 

wcs - It. 






t»c« 


h ■• 




twP 


/////} 




Up 




m 




t.H IDS] 






tosl ito» 




to- 






If Valid : 
Jt Din , 




/Y Valid V / / I 
/JLpin 1 / / 


Valid 
Din 








High-Z 


t DT3 


t TH 



DT/OE ' 



Y/A '• Don't care. 



Note: *1. When WE is high, all the data on I/Os can be written into the memory cell. When WE is low, the data onl/Os are not written 
except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 4 69 



HM538123 Series — Preliminary 

131072-Word x 8-Bit Multiport CMOS Video RAM 



The HM5381 23 is a 1 -Mbit multiport video RAM equipped with a 
128-kword x 8-bit dynamic RAM and a 256-word x 8-bit SAM (serial 
access memory). Its RAM and SAM operate independently and 
asynchronously. It can transfer data between RAM and SAM and 
has a write maskf unction. In addition, it has two newf unctions. Flash 
write clears the data of one row in one cycle in RAM. Special read 
transfer internally detects that the last address in SAM is read and 
transfers the next data of one row automatically from RAM if a 
transfer cycle has previously been executed. These functions make 
it easier to use the HM538123. 

Feautures 

• Multiport organization 

Asynchronous and simultaneous operation of RAM and SAM 
capability 

RAM: 128-kword x 8-bit and SAM: 256-word x 8-bit 

• Access time RAM: 100 ns/120 ns/150 ns max 

SAM: 30 ns/ 40 ns/ 50 ns max 

• Cycle time RAM: 1 90 ns/220 ns/260 ns min 

SAM: 30 ns/ 40 ns/ 60 ns min 

■ Low power 

Active RAM: 385 mW max 
SAM: 275 mW max 
Standby 40 mW max 

• High-speed page mode capability 

• Mask write mode capability 

• Bidirectional data transfer cycle between RAM and SAM capability 

• Special read transfer cycle capability 

• Flash write cycle capability 

• 3 variations of refresh (8 ms/512 cycles) 

RAS-only refresh 
CAS-before-RAS refresh 
Hidden refresh 

• TTL compatible 

Ordering Information 



Type No. 


Access Time 


Package 


HM538123JP-10 


100 ns 


400-mil 


HM538123JP-12 


120 ns 


40-pin 


HM538123JP-15 


150 ns 


Plastic SOJ (CP^tOD) 



Pin Arrangement 



This document con tains information on anewproduct.Specmcationsand information 
contained herein are subject to change without notice. 



sec 


1 40 


:v ss i 


si/oo r. 


2 39 


1 SI/07 


SI/01 c 


3 38 


] SI/06 


SI/02 C 


4 37 


] SI/05 


SI/03 C 


5 36 


3 SI/04 


DT/OE L 


6 35 


S SE 


l/OOC 


7 34 


] 1/07 


1/01 c 


8 33 


1 1/06 


1/02 C 


9 32 


3 1/05 


1/03 C 


10 31 


] 1/04 


Vccl C 


11 in 

1 1 JU 


] V ss 2 


WEC 


12 29 


J DSF 


NCC 


13 28 


] NC 


RASC 


14 27 


] CAS 


NCC 


15 26 


] QSF 


A8C 


16 25 


] AO 


A6t 


17 24 


] A1 


A5t 


18 23 


1A2 


A4t 


19 22 


] A3 




20 21 

1 


3A7 










(Top View) 




Pin Description 


Pin Name 


Function 


A0-A8 


Address inputs 


I/O0-I/O7 


RAM port data inputs/ 




outputs 




SI/O0- 


SAM port data inputs/ 


SI/07 


outputs 




RAS 


Row address strobe 


CAS 


Column address strobe 


WE 


Write enable 


DT/OE 


Data transfer/Output 




enable 




SC 


Serial clock 


SE 


SAM port enable 


DSF 


Special function input 




flag 




QSF 


Data register empty 




flag 




Vcc 


Power supply 


Vss 


Ground 




NC 


No connection 



HITACHI 

470 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM5381 23 Series 



Block Diagram 



RAM 



SAM 



OT/OE 



i/o 



WE 



255 



Mask 
Register 



i — O Color 
— V\ Register 



Dout 






Din 


Memory 


c 




Array 








o 

O 




Row 





— . 



OR : Data Register 



511 




Pointer 



o - 


















8 














Selector 





1 

« \ — ' 



From 

Column Address 
(SAM Start 
Address) 



-CUD 



Pin Function 

RAS (input pin): RAS is a basic RAM signal. It is active 
in low level and standby in high level. Row address and 
signals as shown in table 1 are input at the falling edge 



of RAS. The input level of those signals determine the 
operation cycle of the HM538123. 



Table 1. Operation Cycles of the HM538123 





Input Level at the Falling edge of RAS 




Operation Cycle 


CAS 


DT/OE 


WE 


SE 


DSF 




H 


H 


H 


X 


L 


RAM read/write 


H 


H 


H 


X 


H 


Color register set 


H 


H 


L 


X 


L 


Mask write 


H 


H 


L 


X 


H 


Flash write 


H 


L 


H 


X 


L 


Special read initialization 


H 


L 


H 


X 


H 


Special read transfer 


H 


L 


L 


H 


X 


Pseudo transfer 


H 


L 


L 


L 


X 


Write transfer 


L 

»» . 


X 


X 


X 


X 


CBR refresh 



CAS (input pin): Column address is put into chip at the 
falling edge of CAS. CAS controls output impedance of 
I/O in RAM. 

A0-A8 (input pins): Row address is determined by 
A0-A8 level at thefalling edge of RAS. Column address 
is de termined by A0-A7 level at the falling edge of 
CAS. In transfer cycles, row address is the address on 
the word line which transfers data with SAM data 



register, and column address is the SAM start address 
after transfer. 

WE (input pin): WE pin has two functions at the falling 
edge of RAS and after. When WE is low at the falling 
edgeof RAS, the HM5381 23turns to mask write mode. 
According to the I/O level at the time, write on each 1/ 
Ocan be masked. (WE level at the falling edge of RAS 
is don't care in read cycle.) When WE is high at the 



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589-8300 471 



HM5381 23 Series 



falling edge of RAS, a normal write cycle is executed. 
After that, WE switches read/write cycles as in a 
standard DRAM. In a transfer cycle, the direction of 
transfer is determined by WE level at the falling edge 
of RAS. When WE is low, data is transferred from SAM 
to RAM (data is written into RAM), and when WE is 
high, data is transferred from RAM to SAM (data is 
read from RAM). 

I/O0-I/O7 (input/output pins): I/O pins function as 
mask data at the falling edge of RAS (in mask write and 
flash write mode). Data is written only on high I/O pins. 
Data on low I/O pins are masked and internal data are 
retained. After that, they function as input/output pins 
as those of a standard DRAM. 

DT/OE (input pin): DT/OE pin functions as DT (data 
transfer) pin at the falling edge of RAS and as OE 
(output enable) pin after that. When DT is low at the 
falling edge of RAS, this cycle becomes a transfer 
cycle. When DT is high atthe falling edge of RAS, RAM 
and SAM operate independently. 

SC (input pin): SC is a basic SAM clock. In a serial read 
cycle, data is output from an Sl/O pin synchronously 
with the rising edge of SC. In a serial write cycle, data 
on an Sl/O pin at the rising edge of SC is put into the 
SAM data register. 

SE (input pin): SE pin activates SAM. When SE is high, 
Sl/O is in the high impedance state in serial read cycle 
and data on Sl/O is not put into the SAM data register 
in serial write cycle. SE can be used as a mask for 
serial write because internal pointer is incremented at 
the rising edge of SC. 

SI/O0-SI/O7 (input/output pins): Sl/Os are input/output 
pins in SAM. Direction of input/output is determined by 
the previous transfer cycle. When it was a special read 
transfer cycle or special read initialization cycle, Sl/O 
outputs data. When it was a pseudo transfer cycle or 
write transfer cycle, Sl/O inputs data. 

DSF (input pin): DSF is a special data input flag pin. It 
is set to high when new functions such as color register 
set, special read transfer, and flash write, are used. 

QSF (output pin): The HM5381 23 has a double buffer 
organization which includes two SAM data registers to 
relax the restriction on timings of DT/OE and SC in real 
time transfer cycle. QSF flag turns high when output 
from one of SAM data registers finished (data register 



empty flag). If the condition is detected and special 
read transfer cycle is executed, data is transferred to 
the empty register. SC (serial clock) and data transfer 
cycle can be set asynchronously because detection of 
the last address in SAM and change of data register 
are executed automatically in the chip. It makes the 
system design flexible. 

Operation of HM538123 

Operation of RAM Port 

RAM Read Cycle (DT/OE high, CAS high, DSF low at 
the falling edge of RAS) 

Row address is entered atthe RAS falling edge and 
column address at the CAS falling edge to the device 
as in standard DRAM. Then, when WE is high and DT/ 
OE is low while CAS is low, the selected address data 
is output through I/O pin. At the falling edge of RAS, 
DT/OE and CAS become high to distinguish RAM read 
cycle from transfer cycle and CBR refresh cycle. 
Address access time (tAA) and RAS to column address 
delay time (tRAD) specifications are added to enable 
high-speed page mode. 

RAM Write Cycle 

(Early Write, Dela yed Write, Read Modify Write) 

(DT/OE high, CAS high, DSF low at the falling edge of 
RAS) 

• Normal Mode Write Cycle 

(WE high at the falling edge of RAS) 

When CAS and WE are set low after driving RAS 
low, a write cycle is executed and I/O data is written in 
the selected addresses. When all 8 l/Os are written, 
WE should be high at the falling edge of RAS to 
distinguish normal mode from mask write mode. 

If WE is set low before the CAS falling edge, this 
cycle becomes an early write cycle and I/O becomes in 
high impedance. Data is entered at the CAS falling 
edge. 

If WE is set low after the CAS falling edge, this cycle 
becomes a delalyed write cycle. Data is input at the WE 
falling. I/O does not become high impedance in this 
cycle, so data should be entered with OE in high. 

If WE is set low after tcwD (min) and tAwo (min) after 
the CAS falling edge, this cycle becomes a read modify 
write cycle and enables read/write to execute in the 



472 



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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538123 Series 



same address cycle. In this cycle also, to avoid I/O 
contention, data should be input after reading data and 
driving OE high. 



• Mask Write Mode 

(WE low at the falling edge of RAS) 

If WE is set low at the falling edge of RAS, the cycle 
becomes a mask write mode cycle which writes only to 
selected I/O. Whether or not an I/O is written depends 
on I/O level (mask data) at the falling edge of RAS. 
Then the data is written in high I/O pins and masked in 
low ones and internal data is preserved. This mask 
data is effective during the RAS cycle. So, in high- 
speed page mode cycle, the mask data is preserved 
during the page access. 

High-Speed Page Mode Cycle (PT/OE high, CAS 
high, DSF low at the falling edge of RAS) 

High-speed page mode cycle reads/writes the 
data of the same row address at high speed by toggling 
CAS while RAS is low. Its cycle time is one third of the 
random read/write cycle and is higher than the standard 
page mode cycle by 70-80 %. This product is based on 
static column mode, therefore, address access time 
(tAA), RAS to column address delay time (tRAD), and 
access time from CAS precharge (tACP) are added. In 
one RAS cycle, 256-word memory cells of the same 
row address can be accessed. It is necessary to 
specify access frequency within tRAs max (10 u.s). 



Flash Write Function (See figure. 1) 

• Color Register Set Cycle (CA S-DT /OE WE high, 
DSF high at the falling edge of RAS) 



In color register set cycle, color data is set to the 
internal color register used in flash write cycle. 8 bits of 
internal color register are provided at each I/O. This 
register is composed of static circuits, so once it is set, 
it preserves the data until reset. The data set is just as 
same as in the usual write cycle except that DSF is set 
high at the falling edge of RAS, and early write and 
delayed write cycle can be executed. In this cycle, 
memory array access is not executed, so it is 
unnecessary to give row and column addresses. 

• Flash Write Cycle (CAS-DT/OE high,~WE low, DSF 
high at the falling edge of RAS) 

In a flash write cycle, a row of data (256 x 8 bit) is 
cleared to or 1 at each I/O according to the data of 
color register mentioned before. It is also possible to 
mask I/O in this cycle. When CAS DT/OE is set high , 
WE is low, and DSF is high at the falling edge of RAS, 
this cycle starts. Then, the row address to clear is given 
to row address and mask data is to I/O. Mask data is as 
same as that of a RAM write cycle. High I/O is cleared, 
low I/O is not cleared and the internal data is preserved. 
Cycle time is the same as those of RAM read/write 
cycles, so all bits can be cleared in 1/512 of the usual 
cycle time. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



473 



HM5381 23 Series 



Color Register Set Cyde 



Flash Write Cyde 



Flash Write Cyde 



RAT 



CAS 



V 



Address l 



w 



J 



\ [ 



\ f 



mu we 



7 



■ 



m uiiiimii, 



TZJUEl 



7~XL 



7 
V 



DT/OE 



I/OO 



1/01 



1/02 



1/03 



\ f 



I 



win v// a - m. 



m m .... m\ - mm ^ \m. 



7L 



ta ,. rmu vi m - mn, 



mm -r miu m 



7j "VWrite \l 1 1 



u 



xiimimin wrv 



DSF 



Set (1/03, IK32, l/OI. 
I/OO) -(1,0,0, 1)into 



Execute flash write 
into 1/02, 1/03 on row 
address Xi using color 
register. (I/OO, l/Ol 
are masked.) 



Execute (lash write 
into I/OO, 1/01,1/03 
on row address Xi 
using color register. 
(I/02 is masked.) 



(1/04 — 1/07 are also operated similarly.) 



Figure 1. Use of Flash Write 



<§► HITACHI 

474 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538123 Series 



Transfer Operation 

The HM538123 provides the special read 
initialization cycle, special read transfer cycle, pseudo 
transfer cycle, and write transfer cycle as data transfer 
cycles. These transfer cycles are set by driving DT/OE 
low at the falling edge of RAS. They have following 
functions: 

(1 ) Transfer data between row address and SAM data 
register (except for pseudo transfer cycle) 

(2) Determine direction of data transfer 

(a) Special read initialization cycle, 

Special read transfer cycle: RAM -> SAM 

(b) Write transfer cycle: RAM <- SAM 

(3) Determine input or output of SAM I/O pin (Sl/O) 
Special read initialization cycle: Sl/O output 
Pseudo transfer cycle, 

write transfer cycle: Sl/O input 

(4) Determine first SAM address to access (SAM start 
address) aftertransferring at column address. When 
SAM start address is not changed, neither CAS nor 
address need to be set because SAM start address 
can be latched internally. 



I Read Initialization Cycle (CAS high, DT/OE 
low, WE high, DSF low at the falling edge of RAS) 

If CAS is high, DT/OE is low, WE high, and DSF low 
at the falling edge of RAS, this cycle becomes a special 
read initialization cycle. Special read initialization is 
used (1 ) to start special read transfer operation and (2) 
to switch SAM input/output pin (Sl/O) set in input state 



by pseudo transfer cycle or write transfer cycle, to 
output state. 

If the clock is set as mentioned before, address of 
SAM transfer word line is set to row address and first 
SAM address to access (SAM start address) to column 
address, it becomes possible to execute SAM read 
after tsno (min) after RAS is high. In this cycle, Sl/O 
outputs uncertain data after the RAS falling edge. So 
when SAM is in input state before executing this cycle, 
it is necessary to stop input before the RAS falling 
edge. 

SAM access is inhibited while RAS is low in this 
cycle. SC should not be raised during RAS low. 

Special Read Transfer Cycle (CAS high, DT/OE low, 
WE high, DSF high at the falling edge of RAS) 

Ordinary multiport video RAM has some problems; 
(1) severe limitation on timings between processor 
clock DT/OE and CRT clock SC, (2) complicated 
external control circuit to detect SAM last address 
externally and to insert transfer cycle synchronously. 
Special read transfer cycle makes it possible to relax 
the timing limitations and to set serial clock (SC) and 
transfer cycle perfectly synchronously. 

Figure 2 shows the block diagram for a special read 
transfer. SAM double buffers are composed of two 
data registers (DR). When data is read out from DRO 
serially, special read transfer cycle transfers a row of 
RAM data, which will be read from SAM next, to DR1 . 

The end of data read from DRO is detected internally 
and data register switching circuit automatically 
switches to DR1 output. So data can be output 
continuously. 



RAM 



DT/OE | 



Memory 
Array 



SAM 



V////, 



DR : Data Register 



-A 



Selector r" 
Sout(DRO) 







Detect SAM 
Last Address 







Figure 2. Block Diagram for Special Read Transfer 



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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 475 



HM538123 Series 



Figure 3 shows special read transfer operation 
sequence. QSF flag indicates that reading out from 
data resister has finished (data register empty flag), 
and special read transfer can be executed while QSF 
is high. Atf irst, special read operation starts by executing 
an special read initialization cycle. So QSF becomes 
high, the processor gives row address and SAM start 
address, which is needed next, to the memory, and 
inserts a special read transfer cycle. Data register 



Multiport 
Video RAM 
Operation 
Cycle 



QSF 



SC 



SI/0 
(Output) 



Special read transfer cycle is set by making CAS 
high, DT/OE low, WE high, and DSF high at the falling 
edge of RAS (same as for special read initialization 
cycle except DSF). Like in other transfer cycles, the 
address of the word line to transfer into data register is 
specified by row address and SAM start is specified by 
column address. When the last SAM address data is 
output, the next data is output from the SAM start 
address specified by this RAS cycle. This transfer 
cycle can be executed asynchronously with SAM cycle. 
How ever, it is necessary to execute SAM access after 
RAS becomes high after SAM start address is specified 
by RAS cycle. (See figure. 4.) 

QSF should be high at the falling edge of RAS to 
execute a special read transfer cycle. A cycle whose 
QSF is low is neglected (refresh is executed). When 
the previous transfer cycle is a pseudo transferor write 
transfer cycle and Sl/O is in input state, special read 



becomes full after a special read transfer cycle, so 
QSF becomes low during the cycle. When the last 
SAM address is accessed, QSF becomes high and the 
data register, which outputsf rom the next SAM address, 
changes, and serial access can be executed. 

By executing these handshakes, serial clock and 
transfer cycle can be executed perfectly asynchronous- 
ly, and flexibility of the system design is improved. 



transfer cycle cannot be used (neglected). Special 
read initialization cycle is required to switch Sl/O to 
output state. 

Pseudo Transfer Cycle (CAS high, DT/OE low, WE 
low, and SE high at the falling edge of RAS) 

Pseudo transfer cycle is available for switching SI/ 
O f rom output state to input state because data in RAM 
isn't rewritten. This cycle starts when CAS is high, DT/ 
OE low, WE low, and SE high, at the falling edge of 
RAS. The output buffer in Sl/O becomes high impedance 
within tsRz (max) from the RAS falling edge. Data 
should be input to Sl/O later than tsiD (min) to avoid data 
contention . SAM access becomes enabled after tSRD 
(min) after RAS becomes high, like in the special read 
initialization cycle. In this cycle, SAM access is inhibited 
during RAS low, therefore, SC should not be raised. 



RAM 

— DRO 

Special read 
initialization 
cycle 



RAM 
- DR1 



RAM 
— DRO 



VRAM Y S P , ' cii ' 1 read V YSf»cial mad V 

A Read/Write A transfer cycle A ReatfWrite Artmler cydeA 

/ / / \ 

Column address Colu mn address 

/ - / / 1 \ 



RAM Rear 
/Write 



Y=255 Y=i i+1 i+2 



Y=255 Y=j j+1 



m -AAAAA- -nxv 



I 



Output from DRO 



I 



Output from DR1 



Figure 3. Special Read Transfer Operation Sequence 



476 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538123 Series 



(Special read 
transfer cycle) 



J 



I 



~jh , xi )(Z 



DT/OE 



DSF 



SC 



QSF 



1 
f 

r 








Ln 



| min Qns j 



(Yk) 



A f 



(Yk + l) 



Row address Xj data 



Figure 4. The Restriction of Special Read Transfer 



WriteTransfer Cycle (CAS high, DT/OE low, WE low, 
and SE low at the falling edge of RAS) 

Write transfer cycle can transfer a row of data input 
by serial write cycle to RAM. The row address of data 
transferred into RAM is determined by the address at 
thefalling edge of RAS. The column address is specified 
as the first address to serial write after terminating this 
cycle. Also in this cycle, SAM access becomes enabled 
after tsRD (min) aft er RA S becomes high. SAM access 
is inhibited during RAS low. In this period, SC should 
not be raised. 

SAM Port Operation 

Serial Read Cycle 

SAM port is in read mode when the previous data 
transfer cycle is special read initialization cycle or 
special read transfer cycle. Access is synchronized 
with SC rising, and SAM data is output from Sl/O. When 



the last address is accessed at the state of QSF low 
(data register is full), it is signaled to external circuits 
that special read transfer is enabled by making QSF 
high. Next, after SAM access, output data register is 
switched, then the row address data given by previous 
special read transfer cycle is output from the SAM start 
address. If special read transfer isn't performed (QSF 
high), the column address of the same row address 
is accessed after the last address is accessed. 

Serial Write Cycle 

If previous data transfer cycle is pseudo transfer 
cycle or write transfer cycle, SAM port goes into write 
mode. In this cycle, Sl/O data is programmed into data 
register at the SC rising edge like in the serial read 
cycle. If SE is high, Sl/O data isn't input into data 
register. Internal pointer is incremented according to 
the SC rising edge, so SE high can be used to mask 
data for SAM. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 4 77 



HM538123 Series 



Refresh 

RAM Refresh 

RAM, which is composed of dynamic circuits, 
requires refresh to retain data. Refresh is performed 
by accessing all 51 2 row addresses every 8 ms. There 
are three refresh cycles: (1) RAS-only refresh cycle, 
(2) CAS-before-RAS (CBR) refresh cycle, and (3) 
Hidden refresh cycle. Besides them, the cycles which 
activate RAS such as read/write cycles or transfer 
cycles can refresh the row address. Therefore, no 
refresh cycle is required for accessing all row addresses 
every 8 ms. 

RAS-Only Refresh Cycle: RAS-only refresh cycle 
is performed by activating only RAS cycle with CAS 
fixed to high by inputting the row address (= refresh 
address) from external circuits. In this cycle, output is 
high-impedance and power dissipation is less than 



that of normal read/write cycles because CAS internal 
circuits don't operate. To distinguish this cycle from 
data transfer cycle, DT/OE should be high at the falling 
edge of RAS. 

CBR Refresh Cycle: CBR refresh cycle is set by 
activating CAS before RAS. In this cycle, refresh 
address need not to be input through external circuits 
because it is input through an internal refresh counter. 
In this cycle, output is in high impedance and power 
dissipation is lowered like in RAS-only refresh cycles 
because CAS circuits don't operate. 

Hidden Refresh Cycle: Hidden refresh cycle 
performs refresh by reactivating RAS when DT/OE 
and CAS keep low in normal RAM read cycles. 



SAM Refresh 

SAM parts (data register, shift register, selector), 
organized as fully static circuitry, don't require refresh. 



Absolute Maximum Ratings 



Item 


Symbol 


Rating 




Unit 


Terminal voltage" 1 


Vt 


-1.0 to +7.0 




V 


Power supply voltage 


Vcc 


-0.5 to +7.0 




V 


Power dissipation 


Pr 


1.0 




w 


Operating temperature 


Topr 


to +70 




°c 


Storage temperature 


Tstg 


-55 to +125 




°c 


Note: *1. Relative to Vss. 











Recommended DC Operating Conditions (Ta = 


to +70°C) 






Item Symbol 


Min 


Typ 


Max 


Unit 


Supply voltage * 1 Vcc 


4.5 


5.0 


5.5 




V 


Input high voltage * 1 Vw 


2.4 




6.5 


V 


Input low voltage * 1 Vil 


-0.5* 2 




0.8 


V 



Notes: *1. AU voltages referenced to Vss. 
*2. -3.0 V for pulse width < 10 ns. 



HITACHI 

478 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 




DC Characteristics (Ta = to +70°C, Vcc = 5 v ± 10%, Vss = V) 



Item Symbol 


HM538123 
m 


HM538123 


HM538123 
-15 


Unit 


Test Conditions 










RAM port SAM port 






Min 


Max 


Min 


Max 


Min Max 




Operating 
current 


Icci 




70 




60 


— 50 


mA 


RAS, CAS SC =Vil, SE = Vm 
cycling 




ICC7 





120 


— 


100 


— 80 


mA 


mc = Min SE = Vil, SC cycling 
tscc = Min 


Standby current Ices 


— 


7 


— 


7 


— 7 


mA 


RAS.CAS SC =Vil, SE = Vm 
= Vm 




Ices 


— 


50 


— 


40 


— 30 


mA 


SE = Vil, SC cycling 
tscc = Min 


RAS-only 
refresh current 


lea 


— 


60 


— 


50 


— 40 


mA 


RAS cycling SC =Vil, SE = Vm 
CAS= Vm 




Iocs 


— 


110 


— 


90 


— 70 


mA 


tRC = Min SE = Vil, SC cycling 
tscc = Min 


Page mode 


Ice* 


— 


65 


— 


55 


— 45 


mA 


CAS cycling SC = Vil, SE = Vm 
RAS = Vil 




Iccio 


— 


115 


— 


95 


— 75 


mA 


tec = Min SE = Vil, SC cycling 
tscc = Min 


CAS-before- 
RAS refresh 


Ices 


— 


60 


— 


50 


— 40 


mA 


RAS cycling SC = Vil, SE = Vm 
mc=Min 


current 


Iccii 





110 





90 


— 70 


mA 


SE = Vil, SC cycling 
tscc = Min 


Data 
transfer 


ICC6 





90 





90 


— 90 


mA 


RAS, CAS SC = Vil, SE = Vm 
cycling 


current 


ICC12 


— 


125 


— 


125 


— 125 


mA 


«c = Min SE = Vil, SC cycling 
tscc = Min 


Input leakage 
current 


ILI 


-10 


10 


-10 


10 


-10 10 


U.A 




Output leakage 
current 


Ilo 


-10 


10 


-10 


10 


-10 10 


RA 




Output high 
voltage 


VOH 


2.4 




2.4 




2.4 — 


V 


IoH=-2mA 


Output low 
voltage 


Vol 




0.4 




0.4 


— 0.4 


V 


Iol = 4.2 mA 


Capacitance (Ta = 25°C, Vcc 


=5 V,f = 


: 1 MHz, Bias: Clock, I/O = 


Vcc, address = Vss) 


Item 




Symbol 




Min 




Typ 




Max Unit 


Address 




Cn 












5 pF 


Clock 




Cl2 












5 pF 


I/O, SI/O 


Cvo 












7 P F 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300 4 79 



HM538123 Series 

AC Characteristics ( Ta = to +70°C, Vcc = 5 V ± 10%, V ss = V ) *'• 

Test Conditions 

Input rise and fall time : 5 ns 

Output load : See figures 

Input timing reference levels : 0.8 V, 2.4 V 

Output timing reference levels : 0.4 V, 2.4 V 



Output Load (A) Output Load (B) 

+ 5V +5V 




Note: *1. Including scope & jig. 



Common Parameter 



Item 


Symbol 


HM538123-10 


HM538123-12 


HM538123-15 


Unit Note 






Min 


Max 


Min 


Max 


Min 


Max 






Random read or write cycle time tec 


190 




220 




260 




ns 





RAS precharge time 


tep 


80 




90 




100 




ns 




RAS pulse width 


tRAS 


100 


10000 


120 


10000 


150 


10000 


ns 




CAS - pulse width 


tCAS 


30 


10000 


35 


10000 


40 


10000 


ns 




Row address setup time 


tASR 

















ns 





Row address hold time 


tRAH 


15 




15 




20 





ns 




Column address setup time 


Use 

















ns 





Column address hold time 


tCAH 


20 




20 




25 




ns 




RAS to CAS delay time 


tecr> 


25 


70 


25 


85 


30 


110 


ns 


•5.<6 


RAS hold time 


tRSH 


30 




35 




40 




ns 




CAS hold time 


tCSH 


100 




120 




150 




ns 




CAS to RAS precharge time 


tCRP 


10 




10 




10 




ns 




Transition time (rise to fall) 


tr 


3 


50 


3 


50 


3 


50 


ns 


»8 


Refresh period 


tREF 




8 




8 




8 


ms 




DT to RAS setup time 


tDTS 

















ns 




DT to RAS hold time 


tDTH 


15 




15 




20 




ns 




DSF to RAS setup time 


tSFS 

















ns 




DSF to RAS hold time 


tSFH 


25 




25 




30 




ns 




Data-in to OE delay time 


tDZO 

















ns 




Data-in to CAS delay time 


idzc 

















ns 





HITACHI 

480 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM5381 23 Series 



Read Cycle (RAM), Page Mode Read Cycle 



Item 


Symbol 


HM538123-10 


HM538123-12 


HM538123-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Access time from RAS 


tRAC 


— 


100 


— 


120 


— 


150 


ns 


•2, "3 


Access time from CAS 


tCAC 


— 


30 


— 


35 


— 


40 


ns 


•3. '5 


Access time from OE 


tOAC 


— 


30 


— 


35 


— 


40 


ns 


•3 


Address access time 


tAA 




45 




55 


— 


70 


ns 


•3. "6 


Output buffer turn off delay 


tOFFl 





25 





30 





40 


ns 


•7 


referenced to CAS 




















Output buffer turn off delay 


tOFF2 





25 





30 





40 


ns 


•7 


referenced to OE 




















Read command setup time 


tRCS 





— 





— 





— 


ns 




Read command hold time 


men 





— 





— 





— 


ns 


"12 


Read command hold time 


tRRH 


10 




10 




10 




ns 


"12 


referenced to RAS 




















RAS to column address 


RAD 


20 


55 


20 


65 


25 


80 


ns 


•3. "6 


delay time 




















Page mode cycle time 


tPC 


55 




65 




80 




ns 




CAS precharge time 


tCP 


10 




15 




20 




ns 




Access time from CAS precharge 


tACP 




50 




60 




75 


ns 

























Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle 










Item 


Symbol 


HM538123-10 


HM538123-12 


HM538123-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Write command setup time 


twcs 

















ns 


•9 


Write command hold time 


tWCH 


25 




25 




30 




ns 




Write command pulse width 


tWP 


15 




20 




25 




ns 




Write command to RAS lead time 


tRWL 


30 




35 




40 




ns 




Write command to CAS lead lime 


tCWL 


30 




35 




40 




ns 




Data-in setup time 


tDS 

















ns 


•10 


Data-in hold time 


ton 


25 




25 




30 




ns 


•10 


WE to RAS setup time 


tws 

















ns 




WE to RAS hold time 


tWH 


15 




15 




20 




ns 




Mask data to RAS setup time 


tMS 

















ns 




Mask data to RAS hold time 


tMH 


15 




15 




20 




ns 




OE hold time referenced to WE 


toEn 


10 




15 




20 




ns 




Page mode cycle time 


tPC 


55 




65 




80 




ns 




CAS precharge time 


tCP 


10 




15 




20 




ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 481 



HM538123 Series 



Read-Modify-Wfite Cycle 



Item 




HM538123-10 


HM538123-12 


HM538123-15 


unit 


Note 






iviin 


Max 


Min 


Max 


Min 


Max 






Read -modify -write cycle time 


tRWC 


9SS 








^Sft 




ns 




D AC mile A u/irltri 
IxrSo pUJSc W1UU1 


tRWS 


1 AS 


1 noon 


1 OS 


1VA/UU 




i noon 


ns 




f AC to WP HaIsu 


tCWD 


AS 

u J 




7S 




on 




ns 


•9 


Column address to WE delay 


tAWD 


80 


— 


95 


— 


120 




ns 


•9 


OE to data-in delay time 


tODD 






JV 




4ft 




ns 




rtttCa.S LUIlc lium ivrvo 






100 




120 




150 


ns 


•2,*3 


A^pgc limp fVr\m f^A^I 






30 




35 




40 


ns 


*3."S 


Arfpcc timf* frrMTi (IP 

n^tvftS Lll 1 1C IIAJIII UL 


"tOAC 




30 




35 




40 


ns 


"3 




tAA 




45 




55 




70 


ns 


"3.'6 






20 


55 


20 


D J 


?S 


80 


ns 


•5.'6 


fnltr^llt hlifuf tll^rt rtfr nAil\/ 
WUIJJUI OUllci lUTII-Ull Ucldy 

ra far/in tr\ fit* 




n 
\j 




ft 
u 




ft 
u 


40 ns 




Read command setup time 


tRCS 


V) 




V 




ft 




ns 




Write command to RAS lead time 


tRWL 


in 




7S 




a n 




ns 




Write command to CAS lead time 


tCWL 






DJ 




4U 




ns 




Write command pulse width 


tWP 


l s 




OA 

zu 








ns 





Data-in setup time 


IDS 

















ns 


■10 


Data-in hold time 


tDH 


25 




25 




30 




ns 


•10 


WE to RAS setup time 


tws 

















ns 




WE to RAS hold time 


tWH 


15 




15 




20 


— 


ns 




Mask data to RAS setup time 


tMS 

















ns 




Mask data to RAS hold time 


LMJI 


15 




15 




20 




ns 




OE hold time referenced to WE 


tOEH 


10 




15 




20 




ns 




Refresh Cycle 


Item 


Symbol 


HM538123-10 


HM538123-12 


HM538123-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






CAS setup time 
(CAS-before-RAS refresh) 


tCSR 


10 




10 




10 




ns 




CAS hold time 
(CAS-before-RAS refresh) 


tant 


20 




25 




30 




ns 




RAS precharge to CAS hold time 


tRPC 


10 




10 




10 




ns 

























HITACHI 

482 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538123 Series 



Transfer Cycle 



Item 


Symbol 


HM538123-10 


HM538123-12 


HM538123-15 Unit 


Note 




Min 


Max 


Min 


Max 


Min 


Max 






WF to R AS setim time 


tws 

















ns 




WE to RAS hold time 


tWH 


15 




15 




20 




ns 




SF to RAS setun time 


tES 





— 





— 





— 


ns 




SE to RAS hold time 


tEH 


15 




15 




20 




ns 




RAS to SC delay time 




25 


— 


30 


— 


35 


— 


ns 




SC to RAS setup time 


tSRS 


30 




40 




45 




ns 




RAS to QSF delay time 


tRQD 




100 




120 




150 


ns 


•4 


RAS to QSF (high) delay time 


tRQH 




TBD 




TBD 




TBD 


ns 




Serial data input delay time 
from RAS 


tSID 


50 




60 




75 




ns 




Serial data input to RAS 
delay time 


tS2R 




10 




10 




10 


ns 




Serial output buffer turn-off 
delay from RAS 


tSRZ 


10 


50 


10 


60 


10 


75 


ns 


•1 


RAS to Sout (Low-Z) delay time uilz 


5 




10 




10 




ns 




Serial clock cycle time 


tscc 


30 




40 




60 




ns 




Access time from SC 


tSCA 




30 




40 




50 


ns 


•4 


Serial data out hold time 


tSOH 


7 




7 




7 




ns 


•4 


SC pulse width 


tsc 


10 




10 




10 




ns 




SC precharge width 


tSCP 


10 




10 




10 




ns 




Serial data-in setup time 


tSIS 

















ns 




Serial data-in hold time 


tSIH 


15 




20 




25 




ns 




Serial Read Cycle 





















Item 


Symbol 


HM538123-10 


HM538123-12 


HM538123-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Serial clock cycle time 


tscc 


30 




40 




60 




ns 




Access time from SC 


tSCA 




30 




40 




50 


ns 


•4 


Access time from SE 


tSEA 




25 




30 




40 


ns 


•4 


Serial data-out hold time 


tSOH 


7 




7 




7 




ns 


•4 


SC pulse width 


tsc 


10 




10 




10 




ns 




SC precharge width 


tSCP 


10 




10 




10 




ns 




Serial output buffer turn-off 
delay from SE 


tSEZ 





25 





25 





30 


ns 


•7 


Last SC to QSF delay time 


tSQD 




TBD 




TBD 




TBD 


ns 


•4 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



483 



HM538123 Series 



Serial Write Cycle 



Item 


Symbol 


HM538123-10 


HM538123-12 


HM538123-15 Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Serial clock cycle time 


tscc 


30 


— 


40 


— 


60 


— 


ns 




SC pulse width 


tsc 


10 


— 


10 




10 


— 


ns 




SC precharge width 


tscp 


10 




10 




10 




ns 




Serial data-in setup time 


tsts 


U 




u 








ns 




Serial data-in hold time 


tSIH 


15 




20 




25 




ns 




Serial write enable setup time 


tsws 

















ns 




Serial wite enable hold time 


tSWH 


30 




35 




50 




ns 




Serial write disable setup time 



















ns 




Serial write disable hold time 


tSWIH 


30 




35 




50 




ns 




Flash Write Cycle 




















Item 


Symbol 


HM538123-10 


HM538123-12 


HM538123-15 Unit 


Note 




Min 


Max 


Min 


Max 


Min 


Max 




Flash write cycle time 


tRCFW 


230 




265 




310 




ns 




RAS pulse width 


tRCSFW 


140 




165 




200 




ns 




WE to RAS setup time 


















ns 




WE to RAS hold time 


tWH 


15 




15 




20 




ns 






CAS high level hold time 
referenced to RAS 


tCHHR 


20 




25 




30 




ns 




Mask data to RAS setup time 


tMS 

















ns 




Mask data to RAS hold time 


tMH 


15 




15 




20 




ns 





Notes: *1. AC measurements assume ty = 5 ns. 

*2. Assume that ircd < tRCD (max) and bad < irad (max). 

If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 
*3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 
*4. Measured with a load circuit equivalent to 2 TTL loads and 50 pF. 
*5. When tRCD > tRCD (max) and tRAD < WAD (max), access time is specified by ICAC. 
*6. When tRCD S tRCD (max) and irad > tRAD (max), access time is specified by iaa. 

*7. tOFF (max) is defined as the time at which the output achieves the open circuit condition (Voh - 200 mV, Vol + 200 mV). 
*8. VtH (min) and Vn. (max) are reference levels for measuring timing of input signals. Transition times are measured between 
Vttt and Vil. 

*9. When twes > twes (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 
When iawd > tAWD (min) and tcwo > tcwo (min), the cycle is a read -modify-w rite cycle; the data of the selected address is 
readout from a data out pin and input data is written into the selected address. In this case, impedance on I/O pins is controlled 
byOE. 

*10. These parameters are referenced to CAS falling edge in early write cycles or to WE falling edge in delayed write or read- 
modify- write cycles. 

* 1 1 . After power-up, pause for 100 us or more and execute at least 8 initialization cycles (normal memory cycles or refresh cycles), 

then suit operation. 

* 1 2. If either tRCH or tRRH is satisfied, i 



<§> HITACHI 

484 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Timing Waveforms 
Read Cycle 



t.s. 



RAH i r A5C 



Address / M Row 



Column 



I/O 
(Output) 



1/0 mszM H 



(Input) 



I t,c r i 



Early Write Cycle 



RAS 



CAS 



Address ^[ 



mi 



I/O 
(Input) 

I/O 
(Output) 



#3 



'is. 

DSF 



- /////////////< 



yA^is/////////////// 



High-Z 



™* ^//////////////////////, 



< ///////////////////////// /// 



Y7A ■ Don't i 



Note: * 1 . When WE is high level, all the data on VOs can be written into the mem ory ce ll. When WE is low level, the data on I/Os m 
not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra P 



i-1819 • (415) 589-8300 4 85 



HM538123 Series 



Delayed Write Cycle 



RAS 



ft 



Address /X Row 



Column 



DT/OE 

I/O 
(Input) 



w ///////?/// /////m 



I/O 



(Output) 



-, ^/////////////////w/. 



K~ W//// //////////A 



High-Z 



. l JFH 

Y/X\ '■ Don't care. 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

Read-Modify-Write Cycle 



RAS 



I'."; 



Address 




I/O 
(Output) 



DT/OE" 



/ 



'///////////// < 



iff/mm 



°* m ^//////////// //////////////////m 



X//), : Don't care. 



Note: *1. When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the 
not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM5381 23 Series 



Page Mode Read Cycle 



RAS 

CSS" 

Address 
WE 



I/O 
(Output)" 



(Input) , 
DT/OT' 

DSF 















tm 


lull 

— H t«ic 


' RC D 

ten 


tp 


t C »H 1 




l CAS 

,? 

tcAH 








;^co,u 


-mi// 

( RCM-i- - 


'Colum 


■;</// 

ACS tllCH- 


m 

H " ' 


Hi?// 

Ml 


///, 

. r 


W/, 




|ucs 

t ' 


» 1 

, , *CAC —"J 


h 

OIF l 

■m— lACP ■ 


t«« 

tcAC torn 


*ACP 


J-, 

AA 

t„C 


t OFF I 


V/// 


7//j 

*DTS 


* 

tpzc 


a 3 L Valid 
1 , Dout , 


> 

*DZC 


p 1 Valid 
V Dout 


1 DIC 


5 r Dout 


'■) — 


V/ N 


t OFF2 


itpi 
'//// 




to 

//// 




////// 


tut 

2_ 


*»FM 


//////////// 


///////// 


////////////, 



: Don't care. 



Page Mode Write Cycle (Early Write) 



RAS 



CAS 



■K 



Row X Column 

tw>| k tw»| 



I/O 
(Input) 

I/O 
(Output) 



2* 



t,e J l__t.„,^ 

1 . it.. .1 , L. 1 



Valid 
Din 



l 1 ,. 



///////// 

firm, 



Valid 
Din 



UUUHL 



////////// 



////////////// 
/////////////// 



y//////////////////////////////77777 / 

\//\ '■ Don't care 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os : 
not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

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487 



HM538123 Series 



Page Mode Write Cycle (Delayed Write) 



MS 



CAS 



1«*LL I* — -H t c*i H « en ^ ' cwi 

— ryg* — — i - — h t«» L — - 




(Input) 



I/O 
(Output) 



DT/OT 



wmMMmmiimMMMm 



W////////M 



W////////////////////////^^ 

Y7A : Don't care. 



Note: *1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

RAS-Only Refresh Cycle 



CAS 



Address 



I/O 
(Output) 

I/O 
(Input) 

DT/OT 



DSF 



W///////M 



tin 



1////////////////////////////, 



{///////////////////////////A 



V///////S/////////////////////, 



Y//\ : Don't care. 



488 



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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM5381 23 Series 



CAS-Before-RAS Refresh Cycle 



RAS 



CAS 



tcHR | H 



V 



Address V/////////////////////////////^^ 

™ V//////////////////////^^ 

& '//////////////////////////////////////////, 

I/O 

(Output) 



High-Z 



y//////////////////////////////////////y 

™* y//////////////////////////////////M L 

77A ■ Don't care. 



Hidden Refresh Cycle 



RAS 



CAS 



I , 'nci 



Address ' 



WE 7 



I/O 
(Output) 



DT/OT 



I/O 
(Input) 



*CHB ^ ( 



^///////////////////A 



t OZO ' ' 



_> 



Ml 



Valid Data Out 



High-Z 



^/////////////////////////m 



Y//X '■ Don't care. 



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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538123 Series 

Special Read Initialization Cycle (1)' 







RAS 



3 



WE 



QSF 



DT/OE 



y ////////////////////////////////// 



sc J 



SI/0 
(Output) 



V////////////////////////////////////, 



Valid 
Sout 



Valid 
Sout 



''/// '■ Don't care 

/OC^ : Inhibit rising transient 

I/O : Don't care 



Notes: * 1 . When the previous data transfer cycle is a special read transfer cycle or special read initialization cycle, it is specified as special 
rea d initialization cycle (1), 
*2. SE is in low level. (When SE is high, SI/O becomes high impedance state.) 

*3, CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 

Special Read Initialization Cycle (2)' 1 ' 2 



RAS 
CAS 



WE 7" 



X 



~ W////7//////////////////////// 



V£ W/////////////////////////////7T7T7T7TT/ 

" '«» t ND I 



DT/OE 



1 



SI/O 
( Output )" 



SI/O 
(Input) 



k//////////////// 



>////////////////////m 



-.-tsRS t 



</////////////////777m . 



\f Valid \ 

1 4 fo. f 



Th ^////////////////////////////////////////////, \To 



Y 7/X '■ Don't care 

: Inhibit rising transient 
Don't care 



Notes'. *1. When the previous data transfer cycle is a write or pseudo transfer cycle, it is specified as special read initialization cycle (2). 
*2. SE is in low level. (When SE is high, SI/O becomes high impedance state.) 

*3. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 



490 



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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM5381 23 Series 



Special Read Transfer Cycle * 







CAS 
Address 

WE 

I/O 
(Output) 

I/O 
(Input) 

DT/OE 
SC 



Sl/O 
(Input) 



2f 



- 1 1"'. 



— ^1 ' 1 



H| e h ~ z 



OSF ,, 

DSF 



tots 










t SC _ \ 

J SOH 






Valid Sout 


iy// 




Valid Sout yilfcmyWI, 






High-Z 




t»o 




tlf, 


• "1 


>- t SFM 








Ullllllllllllllllllllllllllllllllllll, 



Notes : * 1 . When QSF is low level at the falling edge of RAS, the special read transfer cycle is not performed. 
*2. SE is in low level. (When SE is high, SI/O becomes high impedance state.) 

*3. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 491 



HM538123 Series 



Pseudo Transfer Cycle 



RAS 
CAS 



i.'"'. 



WE J), 

i, 

DT OE ^ 



SE ^ 



SC 

I 

Sl/O 
(Input) 

Sl/O 
(Output) 

QSF 



j 



^P///////////////////////////////A 



W//////////////////// /////////////, 



' W////////////////////////////////, 



'/// '■ Don't care 
X)0 ; Inh.bit rising 
I/O : Don't care 



Nole: *1. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 

Write Transfer Cycle 



RAS 



CAS 



WE 



DT/OE 



SC 



SAM Stan 
Address 



_t CSH— 



J lllflllllVIIIIIIIIIIII L 



T ^IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIT, 



f ^llllllllllllllllllllllllllllllllllllllL 

J- 



Sl/O 
(Input) 



Sl/O 
(Output) 



QSF 



, i^ niiininiiinnj ^^snm 



Valid Sin 



High-Z 



F777I : Don't care 

t£££i ! Inhibit rising transient 



Note: *1. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 

HITACHI 

492 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Serial Read Cycle 



HM5381 23 Series 



RAS 



« /////////////////////// Vllllllllll 



SE 



sc 



(n-1) W_ 



s| /° — V777V vSi^ \ 

(Output) HI I lf\. Sou. f 



a r 



"7 v»i'iy77"A< ' 

1(n + l)| ' | sc , (n + 2) 



: Don't care. 



Serial Write Cycle 



•l.<2 



RAS 



t 


DTS 


I RAS 
. tDTH _ 


I 


r 


iimiimmiiiiiiih 


E- 3 


Wllillllh 



, ; SCC ^ f^-t swh-*- '"** 



t SWIH S . 



(n + l) \ I 



' ' ts)M tsiS t S1 „ 



tsis t S lH 

: Don't care. 



Notes: *!. When SE is high level in a serial write cycle, data is not written into SAM, however, the pointer is incremented. 
*2. Address is accessed next to address 255. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 493 



HM538123 Series 



Serial Read Cycle (Around Address 255 in SAM) 




Note: *1. Address (i)islheSAM start address provided in the previous special read transfer cycle. When special read transfer cycle isn't 
executed (QSF remains in high level), address is accessed next to address 255. 



Color 



Set Cycle (Early Write) 





t RAS 




\ 


RAS 






tftco a 


,'MH _ 


tc*S ( I 


CAS 




r 




t wCS-»4- 


tcSH -J 

— t*CH 










—r—U 
a 'DM ^ 


p — 



DT/OE 



DSF 



Address 



2f 



L'w r 



mc 



\////////////////m 



mm 



'/////////////////////////A 



] WMSMBZMBZm 



YZA '■ Don't care. 



Note: *1. The level of address pin is don't care, but cannot be changed in this period. 



<§> HITACHI 

494 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538123 Series 



Color Register Set Cycle (Delayed Write) 



CAS 



(Input) 
DT/OE 

DSF 
Address ' 







U * -\ 


tcitP 


* BCD 


t( 


hi 




m 

'a ... 




\ 




I 

'/////////////. 




to. 

— t W 

v, - 


:l 




t WH 


t D! ii 






'II ill/Ill II IK -a^////////////////// 




t OTH 


' I. '»» - 








II/I/I/I//////I//IIIIII/IIIII1 












t HAH 






(/i/iiii/iiiiii/iiiiiii/i/ii//, 



Y7A ■■ Don't care. 



Note: *1. The level of address pin is don't care. 

Flash Write Cycle 



be changed in this period. 







RaS 



J: 



ess ^ 




(t 



Address 



WE 



V//////!//l/ll)i//////l/l)///lh 

ll I , . 



tor 



DSF 



W %/////////////////////////////////. 



Y/A '■ Don't care. 



HITACHI 

i, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534251 Series — Preliminary 

262144-Word x 4-Bit MuMport CMOS Video RAM 



The HM534251 is a 1 -Mbit multiport video RAM equipped with a 
256-kword x 4-bit dynamic RAM and a 51 2-word x 4-bit SAM (serial 
access memory). 

Its RAM and SAM operate independently and asynchronously. It 
can transfer data between RAM and SAM and has a write mask 
function. It is suitable for a graphic processing buffer memory. 

■ FEATURES 

• Multiport Organization 

Asynchronous and Simultaneous Operation of RAM 
and SAM Capability 

RAM 256-kword x 4-Bit 

SAM 512-word x 4-Bit 

• Access Time RAM: 100/1 00/1 20/1 50ns (max.) 

SAM: 30/40/40/50ns (max.) 
RAM: 190/190/220/260ns (min.) 
SAM: 30/40/40/60ns (min.) 

• Low Power 

Active RAM: 385mW (max.) 

SAM: 358mW (max.) 
Standby 40mW (max.) 

• High Speed Page Mode Capability 

• Mask Write Mode Capability 

• Bidirectional Data Transfer Cycle Between RAM and 
SAM Capability 

• Real Time Read Transfer Capability 

• 3 V ariatio ns of Refresh (8ms/512 Cycles) 

RAS -Only R efres h 
CAS-Before-RAS Refresh 
Hidden Refresh 

• TTL Compatible 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM534251JP-10 
HM534251JP-11 
HM534251JP-12 
HM534251JP-15 


100ns 
100ns 
120ns 
150ns 


400-mil 28-pin 
Plastic SOJ 
(CP-28D) 


HM534251ZP-10 
HM534251ZP-11 
HM534251ZP-12 
HM534251ZP-15 


100ns 
100ns 
120ns 
150ns 


400-mil 28-pin 
Plastic ZIP 
(ZP-28) 



This document contains information on anewproduct. Specifications and information 
contained herein are subject to change without notice. 




Pin Arrangement 



HM53425UP Scriei 
SC 



SI/00 
_SI/01 
DT/0Ec 
l/OOi 
1/01 1 



WEl 7 
NCl 8 
RASi 9 
ASt 10 
AEi 11 
A5l 12 
A4! 13 

V«I 14 



28 



V.i 

27 b SI/03 
26 I SI/02 
25 >SE 
24 >l/03 



■1/02 

"NC 

'CAS 

■NC 

■AO 

'Al 

>A2 

■A3 

■A7 



(Top View) 



1/02 2 

3E 4 

SI/03 6 
SC 8 
SI/01 10 
l/OO 12 
WE 14 
RAS 16 
AG It 
A4 20 
A7 22 
A2 24 
AO 26 
CAS 28 



HM534251ZP Scries 
1 NC 
3 1/03 
5 SI/02 



7 V„ 
9 SI/OO 

11 BT/0E 

13 1/01 

15 NC 

17 A8 

19 AS 

21 V« 

23 A3 

25 Al 

27 NC 



(Bottom View) 



Pin Description 


Pin Name 


Function 


A0-A8 


Address inputs 


I/O0-I/O3 


RAM port data inputs/ 




outputs 


SI/O0- 


SAM port data inputs/ 


SI/03 


outputs 


RAS 


Row address strobe 


CAS 


Column address strobe 


WE 


Write enable 


DT/OE 


Data transfer/Output 




enable 


SC 


Serial clock 


"SE" 


SAM port enable 


Vcc 


Power supply 


Vss 


Ground 


NC 


No connection 



HITACHI 

496 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534251 Series 



Block Diagram 



I/O (~ 



Mask 
Register 



n i — -X^ i 



DT/OE 



Dout 






Din 








Memory 


c 

I 




Array 


o 
O 










Row 





511 



A a 
h i I 



From 

Column Address 
(SAM Start Address) 



Pin Function 

RAS (input pin): RAS is a basic RAM signal. It is active of RAS. The input level of those signals determine the 
in low level and standby in high level. Row address and operation cycle of the HM534251 . 
signals as shown in table 1 are input at the falling edge 



Table 1. Operation Cycles of the HM534251 





Input level at the falling edge of RAS 






CAS 


DT/OE 


WE 


SE 


— Operation Cycle 


H 


H 


H 


X 


RAM read/write 


H 


H 


L 


X 


Mask write 


H 


L 


H 


X 


Read transfer 


H 


L 


L 


H 


Pseudo transfer 


H 


L 


L 


L 


Write transfer 


L 


X 


X 


X 


CBR refresh 



Note: 



Don't care. 



CAS (input pin): Column address is put into chip at the 
falling edge of CAS. CAS controls output impedance of 
I/O in RAM. 



A0-A8 (input pins): Row address is determined by 
A0-A8 level at thefalling edgeof RAS. Column address 
is determined by A0-A8 level at the falling edge of 
CAS. In transfer cycles, row address is the address on 
the word line which transfers data with SAM data 
register, and column address is the SAM start address 
after transfer. 



WE (input pin): WE pin has two functions at the falling 
edge of RAS and after. When WE is low at the falling 
edgeof RAS, the HM534251 turnsto mask write mode. 
According to the I/O level at the time, write on each I/O 
can be masked. (WE level at the falling edge of RAS is 
don't care in read cycle.) When WE is high at the falling 
edge of RAS, a normal write cycle is executed. After 
that, WE switches read/write cycles as in a standard 
DRAM. In a transfer cycle, the direction of transfer is 
determined by WE level at the falling edge of RAS. 
When WE is low, data is transferred from SAM to RAM 
(data is written into RAM), and when WE is high, data 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534251 Series 



is transferred from RAM to SAM (data is read from 
RAM). 

I/O0-I/O3 (input/output pins): I/O pins function as 
mask data at the falling edge of RAS (in mask write 
mode). Data is written only on high I/O pins. Data on 
tow I/O pins are masked and internal data are retained. 
After that, they function as input/output pins as those 
of a standard DRAM. 

DT/OE (input pin): DT/OE pin functions as DT (data 
transfer) pin at the falling edge of RAS and as OE 
(output enable) pin after that. When DT is low at the 
falling edge of RAS, this cycle becomes a transfer 
cycle. When DT is high at the falling edge of RAS, RAM 
and SAM operate independently. 

SC (input pin): SC is a basic SAM clock. In a serial read 
cycle, data is output from an Sl/O pin synchronously 
with the rising edge of SC. In a serial write cycle, data 
on an Sl/O pin at the rising edge of SC is put into the 
SAM data register. 

SE (input pin): SE pin activates SAM. When SE is high, 
Sl/O is in the high impedance state in serial read cycle 
and data on Sl/O is not put into the SAM data register 
in serial write cycle. "SE can be used as a mask for 
serial write because internal pointer is incremented at 
the rising edge of SC. 

SI/O0-SI/O3 (input/output pins): Sl/Os are input/output 
pins in SAM. Direction of input/output is determined by 
the previous transfer cycle. When it was a read transfer 
cycle, Sl/O outputs data. When it was a pseudo 
transfer cycle or write transfer cycle, Sl/O inputs data. 

Operation of HM534251 

Operation of RAM Port 
RAMRead C ycle 

(DT/OE high, CAS high, at the falling edge of RAS) 

Row address is entered at the RAS falling edge and 
column address at the CAS falling edge to the device 
as i n standard DRAM . Then, when WE is high and DT? 
OE is low while CAS is tow, the selected address data 
is output through I/O pin. At the falling edge of RAS, 
DT/OE and CAS become high to distinguish RAM read 
cycle from transfer cycle and CBR refresh cycle. 
Address access time (tAA) and BAS to column address 
delay time (tRAD) specifications are added to enable 
high-speed page mode. 



RAM Write Cycle 

(EarlyWrite, Delayed Write, Read-Modify- Write) 

(DT/OE high, CAS high at the falling edge of RAS) 

• Normal Mode Write Cycle 

(WE high at the falling edge of RAS) 

When CAS and WE are set low after RAS is set low, 
a write cycle is executed and I/O data is written at the 
selected addresses. When all 4 l/Os are written, WE 
should be high at the falling edge of RAS to distinguish 
normal mode from mask write mode. 

If WE is set low before the CAS falling edge, this 
cycle becomes an early write cycle and I/O becomes 
high impedance. Data is entered at the CAS falling 
edge. 

If WE is set tow after the CAS falling edge, this cycle 
becomes a delayed write cycle. Data is input at the WE 
falling edge. I/O does not become high impedance in 
this cycle, so data should be entered with OE in high. 

If WE is set low after tcwD (min) and tAwo (min) after 
the CAS falling edge, this cycle becomes a read- 
modify-write cycle and enables write after read to 
execute in the same address cycle. In this cycle also, 
to avoid I/O contention,_data should be input after 
reading data and setting OE high. 

• Mask Write Mode (WE low at the falling edge of 
RAS) 

If WE is set low at the falling edge of RAS, the cycle 
becomes a mask write mode cycle which writes only to 
selected I/O. Whether or not an I/O is written depends 
on I/O level (mask data) at the falling edge of RAS. 
Then the data is written in high I/O pins and masked in 
tow ones and internal data is preserved. This mask 
data is effective during the RAS cycle. So, in high- 
speed page mode cycle, the mask data is preserved 
during the page access. 

High-Speed Page Mode Cycle 

(DT/OE high, CAS high at the falling edge of RAS) 

High-speed page mode cycle reads/writes the data 
of the same row address at high speed by toggling CAS 
while RAS is low. Its cycle time is one third of the 
random read/write cycle and is higherthan the standard 
page mode cycle by 70-80%. This product is based on 
static column mode, therefore, address access time 



HITACHI 

498 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005 1819 • (415) 589-8300 



HM534251 Series 



(tAA), RAS to column address delay time (tRAo), and 
access time from CAS precharge (tACP) are added. In one 
RAS cycle, 512-word memory cells of the same row 
address can be accessed. It is necessary to specify 
access frequency within tRAS max (1 us). 

Transfer Operation 

The HM534251 provides the read transfer cycle, 
pseudo transfer cycle, and write transfer cycle as data 
transfercycles. These transfer cycles are set by driving 
DT/OE low at the falling edge of RAS. 

They have following functions: 

(1 ) Transfer data between row address and SAM data 
register (except for pseudo transfer cycle) 

(2) Determine direction of data transfer 

(a) Read transfer cycle: RAM -> SAM 

(b) Write transfer cycle: RAM «- SAM 

(3) Determine input or output of SAM I/O pin (Sl/O) 



Read transfer cycle: 
Pseudo transfer cycle, 
write transfer cycle: 



Sl/O output 
Sl/O input 



(4) Determine first SAM address to access (SAM start 
address) after transferring at column address. When 
SAM start address is not changed, neither CAS nor 
address need to be set because SAM start address 
can be latched internally. 

Read Transfer Cycl e (CA S high, DT/OE low, WE high 
at the falling edge of RAS) 

This cycle becomes read transfer cycle by setting 
DT/OE low and WE high at the falling edge of RAS. The 
row address data (512x4 bit) determined by this cycle 
is transferred synchronously at the rising edge of DT/ 
OE. After the rising edge of DT/OE, the new address 
data outputs from SAM start address determined by 
column address. 

This cycle can execute SAM access serially even 
during transfer (real time read transfer). In this case, 
the timing tsDD(min) is specified between the last SAM 
access before transfer and DT/OE rising edge, and 
tSDH(min) between the first SAM access and DT/OE 
rising edge (see figure 1 ). 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 4 99 



HM534251 Series 



RAS 



/ 



Address 



"A 

1 Yi )C 



z 







DT/OE 



sc 



51/0 till) 


[ Yi \ Yj + 1 


SAM Data Before Transfer 


SAM Data After Transfer 








Figure 1. Real Time Re 


ad Transfer 





K read transfer cycle is executed, Sl/O becomes 
output state. When the previous transfer cycle is either 
pseudo transfer cycle or write transfer cycle and Sl/O 
is in inp ut stat e, uncertain data outputs after tRLz(min) 
after the RAS falling edge. Before that, input should be 
set high impedance to avoid data contention. 

Pseudo Transfer Cycle (CAS high, DT/OE low, WE 
low, and SE high at the falling edge of RAS) 

Pseudo transfer cycle is available for switching 
Sl/O from output state to input state because data in 
RAM isn't rewritten. This cycle starts when CAS is 
high, "DT/OE low, WE low, and SE high, at the falling 
edge of RAS. The output buffer in Sl/O becomes high 
impedance within tsRz (max) from the RAS falling 
edge. Data should be input to Sl/O later than tsra (min) 
to avoid data contention . SAM access becomes enabled 
aftertsRD (min) after RAS bec omes high. In this cycle, 
SAM access is inhibited during RAS low, therefore, SC 
should not be raised. 



Write Transfer Cycle (CAS high , DT/O E low, WE low, 
and SE low at the falling edge of RAS) 

Write transfer cycle can transfer a row of data input 
by serial write cycle to RAM. The row address of data 
transferred into RAM is determined by the address at 
thefalling edgeof RAS. The column address is specified 
as the first address to serial write after terminating this 
cycle. Also in this cycle, SAM access becomes enabled 
after tsRD (min) after RAS becomes high. SAM access is 
inhibited during RAS low. In this period, SC should not 
be raised. 

SAM Port Operation 

Serial Read Cycle 

SAM port is in read mode when the previous data 
transfer cycle is read transfer cycle. Access is 
synchronized with SC rising, and SAM data is output 
from Sl/O. If SE is set high Sl/O becomes high impedance 
and internal pointer is incremented at the SC rising 
edge. 



500 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



nivio J4ZD i oeries 



Serial Write Cycle 

If previous data transfer cycle is pseudo transfer 
cycle or write transfer cycle, SAM port goes into write 
mode. In this cycle, Sl/Odata is programmed into data 
register at the SC rising edge like in the serial read 
cycle. If SE is high, Sl/O data isn't input into data 
resister. Internal pointer is incremented according to 
the SC rising edge, so SE high can mask data for SAM. 

Refresh 

RAM Refresh 

RAM, which is composed of dynamic circuits, 
requires refresh to retain data. Refresh is performed 
by accessing all 51 2 row addresses every 8 ms. There 
are three refresh cycles: (1) RAS-only refresh cycle, 
(2) CAS-before-RAS (CBR) refresh cycle, and (3) 
Hidden refresh cycle. Besides them, the cycles which 
activate RAS such as read/write cycles or transfer 
cycles can refresh the row address. Therefore, no 
refresh cycle is required for accessing all row addresses 
every 8 ms. 



RAS-Only Refresh Cycle: RAS-only refresh cycle is 
performed by activating only RAS cycle with CAS fixed 
to high by inputting the row address (= refresh address) 
from external circuits. In this cycle, output is high- 
impedance and power dissipation is less than that of 
normal read/write cycles because CAS internal circuits 
don't operate. To distinguish this cycle from datatransfer 
cycle, DT/OE should be high at the falling edge of RAS. 

CBR Refresh Cycle: CBR refresh cycle is set by 
activating CAS before RAS. In this cycle, refresh address 
need not to be input through external circuits because 
it is input through an internal refresh counter. In this 
cycle, output is in high impedance and power dissipation 
is lowered like in RAS-only refresh cycles because 
CAS circuits don't operate. 

Hidden Refresh Cycle: Hidden refresh cycle performs 
refresh by reactivating RAS when DT/OE and CAS 
keep low in normal RAM read cycles. 

SAM Refresh 

SAM parts (data register, shift register, selector), 
organized as fully static circuitry, don't require refresh. 



Absolute Maximum Ratings 



Item 


Symbol 


Rating 




Unit 


Terminal voltage 


Vt 


-1.0 to +7.0 




V 


Power supply voltage *' 


Vcc 


-0.5 to +7.0 




V 


Power dissipation 


Pr 


1.0 




w 


Operating temperature 


Topr 


to +70 




"C 


Storage temperature 


Tstg 


-55 to +125 




°c 


Note: *1. Relative to Vss. 










Recommended DC Operating Conditions (Ta = 


to +70°C) 






Item 


Symbol Min 


Typ 


Max 


Unit 


Supply voltage* 1 


Vcc 4.5 


5.0 


5.5 


V 


Input high voltage "' 


Vm 2.4 




6.5 


V 


Input low voltage * 1 


Vil -0.5' 2 




0.8 


V 



Notes: *1. All voltages referenced to Vss. 
*2. -3.0 V for pulse width < 10 ns. 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 501 



■ DC CHARACTERISTICS (T a = to 70°C, V cc = 5V ± 10%, V ss = 0V) 



Item 


Symbol 


Test Conditions 


HM53425I-I0 


HM534251-I1 


HM53425I-12 


HM534251-15 


Unit 


Notes 


RAM Port 


SAM Port 


Min. 


Max. 


Min. 


Max. ' 


Min. 


Max. 


Min. 


Max. 


Operating 


"cci 


RAS. CAS Cycling 


SE = V,„, SC = % 


- 


70 


- 


70 


- 


60 


- 


55 


mA 


1, 2 


Current 


J CC7 


t RC = Min. 


SE = V IL , SC Cycling t^c = Min. 


- 


120 


- 


120 




100 




85 


mA 


Standby 


lcC2 


RAS. CAS = V, H 


SE = V, H , SC = V IL 


- 


7 


- 


7 


- 


7 


- 


7 


mA 


1 


Current 


l ccs 


SE = V, L , SC Cycling i^q = Min. 


- 


65 


- 


55 


- 


55 




40 


mA 




RAS-Onh 
Refresh 


kxs 


RAS Cycling 
CAS - V m 

"IH 

I^q — Min. 


SE = V, H . SC = V IL 


- 


70 


- 


70 


- 


60 


- 


55 


mA 


2 


Current 


! CC9 


SE = V| L , SC Cycling t^p = Min. 


- 


120 


- 


120 


- 


100 




83 


mA 


Page Mode 


'cC4 


CAS Cycling 
RAS = V IL 
*RC = Min. 


SE = V 1H , SC = V IL 




80 




80 




70 




60 


mA 


1,3 


Current 


'ccio 


SE = V, L , SC Cycling t scc = Min. 


— 


130 


_ 


130 


_ 


110 


_ 


90 


mA 


CAS-Before- 
RAS Refresh 
Current 


*CCS 


RAS Cycling 


SE = V, H , SC = V, L 




60 




60 




50 




40 


mA 





*CCil 


'rc = Min. 


SE = V, L . SC Cycling t^c = Min. 


_ 


110 


_ 


110 


_ 


90 




70 


mA 




Data 

Transfer 

Current 


*CC6 


RAS, CAS 


^ = V ]H- SC 


- 


95 


- 


95 


- 


90 




85 


mA 




2 




Cycling t RC = Min. 


SE = V, L . SC Cycling tsc C = Min. 




135 




135 




125 




115 


mA 


Input 

Leakage 

Current 


»li 




-10 


10 


-10 


K) 


-K> 


10 


K) 


10 


oA 




Output 

Leakage 

Current 


'lo 




-10 


10 


-10 


10 


-10 


10 


-10 


10 


(■A 




Output High 
Voltage 


V OH 


■oh = _JmA 


2.4 




2.4 




2.4 




2.4 




V 




Output Low 
Voltage 


Vol 


'OL = 42mA 




0.4 




0.4 




0.4 




0.4 


V 





NOTES: 1 . Ice depends on output loading condition when the device is selected. Ice max. is specified at the output open condition. 

2. Address can be changed less than three times while RAS = Vil. 

3. Address can be changed once or less while CAS = Vm. 



Capacitance (Ta 


= 25°C, Vcc = 


= 5 V, f = 1MHz, Bias: Clock, I/O = 


= Vcc, address = Vss) 




Item 


Symbol 


Min Typ 


Max 


Unit 


Address 


Cn 




5 


pF 


Clock 


Cl2 




5 


pF 


I/O, siyo 


Cvo 




7 


PF 



HITACHI 

502 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



AC Characteristics ( Ta = to 70°C, Vcc = 5 V ± 10%, Vss = V ) 



HM534251 Series 



Test Conditions 

Input rise and fall time: 5 ns 

Output load: See figures 

Input timing reference levels: 0.8 V, 2.4 V 

Output timing reference levels: 0.4 V, 2.4 V 




Note: *1. Including scope & jig. 



• Common Parameter 



Parameter 


Symbol 


HM534251-10 


HM534251-11 


HM534251-12 


HM534251-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Random Read or 
Write Cycle Time 


l RC 


190 




190 




220 




260 




ns 





RAS Precharge Time 


l RP 


80 




SO 




90 




100 




ns 




RAS Pulse Width 


l RAS 


100 


10000 


100 


10000 


120 


10000 


150 


10000 


ns 




CAS Pulse Width 


tcAS 


30 


10000 


30 


10000 


35 


10000 


40 


10000 


ns 




Row Address Setup Time 


l ASR 






















ns 




Row Address Hold Time 


l RAH 


15 




15 




15 




20 




ns 




Column Address Setup Time 


Use 






















ns 




Column Address Hold Time 


tCAH 


20 




20 




20 




25 




ns 




RAS to CAS Delay Time 


l RCD 


25 


70 


25 


70 


25 


85 


30 


110 


ns 


5, 6 


RAS Hold Time 


'rsh 


30 




30 




35 




40 




ns 




CAS Hold Time 


k:SH 


100 




100 




120 




150 




ns 




CAS to RAS Precharge Time 


•CRP 


10 




10 




10 




10 




ns 




Transition Time (Rise to Fall) 


t T 


3 


50 


3 


50 


3 


50 


3 


50 


ns 


8 


Refresh Period 


l REF 




8 




8 




8 




8 


ms 




DT to RAS Setup Time 


l DTS 






















ns 




DT to RAS Hold Time 


tDTH 


15 




15 




15 




20 




ns 




Data-in to OE Delay Time 


l DZO 






















ns 




Data-in to CAS Delay Time 


'dzc 






















ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 03 



HM534251 Series 

• Read Cycle (RAM), Page Mode Read Cycle 



Parameter 


symbol 


HM534251-10 


HM534251-11 


HM534251-12 


HM534251-15 


T fan* 

unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Access Time From RAS 


*RAC 




100 


- 


100 


- 


120 


- 


150 


ns 


2,3 


Access Time From CAS 


tCAC 




30 




30 




35 




40 


ns 


3,5 


Access Time From OE 


^OAC 




30 




30 




35 




40 


ns 


3 


Address Access Time 






45 




45 




55 




70 


ns 


3, 6 


Outnut Buffer TYirn Off Delav 
Referenced to CAS 


tOFFl 





25 





25 





30 





40 


ns 


7 


Output Buffer Turn Off Delay 
Referenced to OE 


t OFF2 





25 





25 





30 





40 


ns 


7 


Read Command Setup Time 


^RCS 






















ns 




Read Command Hold Time 


^RCH 












o 




o 




ns 


12 


Read Command Hold Time 
Referenced to RAS 


l RRH 


10 





10 





10 





10 





ns 


12 


RAS to Column Address 
Delay Time 


<RAD 


20 


55 


20 


55 


20 


65 


25 


80 


ns 


5, 6 


Page Mode Cycle Time 


l PC 


55 




55 




65 




80 




ns 




CAS Precharge Time 


tcp 


10 




10 




15 




20 




ns 




Access Time From CAS 
Precharge 


l ACP 




50 




50 




60 




75 


ns 





• Write Cycle (RAM), Page Mode Write Cycle 



Parameter 


Symbol 


HM534251-10 


HM534251-U 


HM534251-12 


HM534251-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Command Setup Time 


'wcs 






















ns 


9 


Write Command Hold Time 


'WCH 


25 




25 




25 




30 




ns 




Write Command Pulse Width 


'wp 


15 




15 




20 




25 




ns 




Write Command to RAS 
Lead Time 


l RWL 


30 




30 




35 




40 




ns 




Write Command to CAS 
Lead Time 


<CWL 


30 




30 




35 




40 




ns 




Data-in Setup Time 


l DS 






















ns 


10 


Data-in Hold Time 


l DH 


25 




25 




25 




30 




ns 


10 


WE to RAS Setup Time 


l WS 






















ns 




WE to RAS Hold Time 


l WH 


15 




15 




15 




20 




ns 




Mask Data to RAS Setup Time 


*MS 






















ns 




Mask Data to RAS Hold Time 


l MH 


15 




15 




15 




20 




ns 




OE Hold Time Referenced 
to WE 


l OEH 


10 




10 




15 




20 




ns 




Page Mode Cycle Time 


tp C 


55 




55 




65 




80 




ns 




CAS Precharge Time 


tcp 


10 




10 




15 




20 




ns 





HITACHI 

504 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534251 Series 

• Read-Modify-Write Cycle 



Parameter 


Symbol 


HM534251-10 


HM534251-11 


HM534251-12 


HM534251-15 


Unit 


Notes 


Min. 


Max . 


Min. 


Max. 


Min . 


Max. 


Min. 


Max. 


ivcdu iviouny write v^ycic 11111c 


'rwc 


LDD 




9ss 

ADD 




7QS 

AjD 




^sn 

DDKJ 








ruise wiuin 


'rws 


IAS 


IfWYVt 
1UUVAJ 


IAS 




ios 

VyD 


innnn 


9/1 A 
A e W 


IIAAAJ 


ns 




r*c *~ u/c rv>lav 
v^rto iu nc i^eidy 


•CWD 


AS 

OD 




AS 
OD 




7S 

ID 




on 




ns 


Q 


Column Address to WE Delay 


•awd 


fift 




fin 




as 








ns 


Q 


\je. to uata-in ueiay lime 


tODD 


25 


- 


25 


- 


30 


- 


40 


- 


ns 




Access Time From RAS 


l RAC 




100 




100 




120 


— 


150 


ns 


2, 3 


Access Time From CAS 


tCAC 




30 




30 




35 




40 


ns 


3. 5 


Access Time From OE 


klAC 


— 


30 


— 


30 


— 


35 


— 


40 


ns 


3 


Address Access Time 


l AA 




45 




45 




55 




70 


ns 


3,6 


RAS to Column Address Delay 


l RAD 


20 


55 


20 


55 


20 


65 


25 


80 


ns 


5,6 


Output Buffer Turn-Off 
Delay Referenced to OE 


*OFF2 




25 




25 




30 




40 


ns 




Read Command Setup Time 


l RCS 





— 





— 





— 





— 


ns 




Write Command to RAS 
Lead Time 


*RWL 


30 




30 




35 




40 




ns 




Write Command to CAS 
Lcdu i lnie 


tCWL 


30 


— 


30 


— 


35 




40 


— 


ns 




Write Command Pulse Width 


<WP 


15 




15 




20 




25 




ns 




Data-in oetup lime 


l DS 





- 





- 





- 





- 


ns 


1U 


Data-in Hold Time 


l DH 


25 




25 




25 




30 




ns 


10 


WE to RAS Setup Time 


'ws 






















ns 




WE to RAS Hold Time 


l WH 


15 




15 




15 




20 




ns 




Mask Data to RAS Setup Time 


l MS 






















ns 




Mask Data to RAS Hold Time 


<MH 


15 




15 




15 




20 




ns 




OE Hold Time Referenced 
to WE 


<OEH 


10 




10 




15 




20 




ns 




• Refresh Cycle 


Parameter 


Symbol 


HM534251-10 


HM534251-U 


HM534251-12 


HM534251-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


CAS Setup Time 
(CAS-Before-RAS Refresh) 


tcsR 


10 




10 




10 




10 




ns 




CAS Hold Time 
(CAS-Before-RAS Refresh) 


tCHR 


20 




20 




25 




30 




ns 




RAS Precharge to CAS 
Hold Time 


l RPC 


10 




10 




10 




10 




ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534251 Series 



• Transfer Cycle 



Parameter 


Symbol 


HM534251-10 


HM534251-U 


HM534251-12 


HM534251-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


WE to RAS Setup Time 


'ws 


























ns 




WE to RAS Hold Time 


tWH 


15 


_ 


15 





15 





20 





ns 




SE to RAS Setup Time 


•eS 










_ 














ns 




SE to RAS Hold Time 


'eh 


15 




15 


_ 


15 


_ 


20 





ns 




RAS to SC Delay Time 


•SRD 


25 




30 




30 


_ 


35 


_ 


ns 




SC to RAS Setup Time 


t.SRS 


30 


- 


40 


- 


40 


- 


45 


- 


ns 




DT Hold Time From RAS 


l RDH 


80 




90 




90 




110 




ns 




DT Hold Time From CAS 


•cDH 


20 




30 




30 




45 




ns 




Last SC to DT Delay Time 


•SDD 


5 


- 


5 


- 


5 


- 


10 


- 


ns 




First SC to DT Hold Time 


l SDH 






Zj 












ns 




u i to kaj Leaa i tme 


l DTL 


50 


- 


50 


- 


50 


- 


50 


- 


ns 




DT Hold Time Referenced 

tn D AO Uioh 

lo nign 


•dthh 


20 


- 


25 


— 


25 


— 


30 


— 


ns 




DT Precharge Time 


l DTP 


30 




35 




35 




40 




ns 




Serial Data Input Delay 
Time from RAS 


•SID 


50 




60 




60 




75 




ns 




Serial Data Input to 

D AC PWl'ii; Timp 

tvrto ueidy lime 


l SZR 





10 





10 





10 





10 


ns 




Serial Output Butter lurn-Uft 
Delay From RAS 


l SRZ 


10 


50 


10 


60 


10 


60 


10 


75 


ns 


7 


RAS to S . (Low-Zl 
Delay Time 


l RLZ 


5 


— 


10 


— 


10 


— 


10 


— 


ns 




Serial Clock Cycle Time 


•sec 


30 




40 




40 


_ 


60 




ns 




Serial Clock Cycle Time 


l SCC2 


40 




40 




40 




60 




ns 


13 


Access Time From SC 


*SCA 




30 




40 




40 




50 


ns 


4 


Serial Data Out Hold Time 


( SOH 


7 




7 




7 




7 




ns 


4 


SC Pulse Width 


<sc 


10 




10 




10 




10 




ns 




SC Precharge Width 


l SCP 


10 




10 




10 




10 




ns 




Serial Data-in Setup Time 


•sis 






















ns 





Serial Data-in Hold Time 


l SIH 


15 




20 




20 




25 


_ 


ns 




• Serial Read Cycle 


Parameter 


Symbol 


HM534251-10 


HM534251-11 


HM534251-12 


HM534251-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Serial Clock Cycle Time 


•sec 


30 




40 




40 




60 




ns 




Access Time From SC 


l SCA 




30 




40 




40 




50 


ns 


4 


Access Time From SE 


•sea 




25 




30 




30 




40 


ns 


4 


Serial Data-Out Hold Time 


l SOH 


7 




7 




7 




7 




ns 


4 


SC Pulse Width 


l SC 


10 




10 




10 




10 




ns 




SC Precharge Width 


l SCP 


10 




10 




10 




10 




ns 




Serial Output_Buffer Turn-Off 
Delay From SE 


l SEZ 




25 




25 




25 




30 


ns 


7 



HITACHI 

506 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HMS34251 Series 

• Serial Write Cycle 



Parameter 


Symbol 


HM534251-10 


HM534251-11 


HM534251-12 


HM534251-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Serial Clock Cycle Time 


'sec 


30 




40 




40 




60 




ns 




SC Pulse Width 


^sc 


10 




10 




10 




10 




ns 




SC Precharge Width 




10 


- 


10 


- 


10 


- 


10 


- 


ns 


1 


Serial Data-in Setup Time 


l SIS 


u 




n 




\j 




ft 




ns 




C^rial Plata Tn Hr»lH Tim** 

ocridi udid-iu noiu nine 


t 

l SIH 


15 


- 


20 


— 


20 


- 


25 


- 






Serial Write Enable 
Setup Time 


l SWS 






















ns 





Serial Write Enable Hold Time 


'SWH 


30 




35 




35 




50 




ns 




Serial Write Disable 
Setup Time 


tswis 






















ns 




Serial Write Disable 
Hold Time 


tSWIH 


30 




35 




35 




50 




ns 





Notes : * 1 . AC measurements assume tT = 5 ns. 

*2. Assume that tRCD < tRCD (max) and ir ad £ irad (max). 

If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 
*3. Measured with a load circuit equivalent to 2 TIL loads and 100 pF. 
*4. Measured with a load circuit equivalent to 2 11 L loads and 50 pF. 
*5. When tRCD > tRCD (max) and tRAD < tRAD (max), access time is specified by tCAC. 
*6. When tRCD £ tRCD (max) and tRAD > tRAD (max), access time is specified by tAA. 

*7. tOFF (max) is defined as the lime at which the output achieves the open circuit condition (Voh - 2 00 m V, Vol + 200 mV). 
*8. Vm (min) and Vu. (max) are reference levels for measuring timing of input signals. Transition times are measured between 
Vk and VlL. 

•9. When twcs > twcs (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) 
condition. 

When tAWD > tAWD (min) and tcwo > tcWD (min), the cycle is a read-modify-write cycle; the data of the selected address 
is read out from a data output pin and input data is written into the selected address. In this case, impedance on I/O pins 

is controlled by OE. 

*10. These parameters are referenced to CAS falling edge in early write cycles or to WE falling edge in delayed write or read- 
modify-write cycles. 

•11. After power-up, pause for 1 00 us or more and execute at least 8 initialization cycles (normal memory cycles or refresh 

cycles), then start operation. 
*12. If either tRCH or tRRH is satisfied, operation is guaranteed. 

*13. tscc2 is defined as the last SAM cycle time before read transfer in read transfer cycle (1). 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 07 



HM534251 Series 



Timing Waveforms 
Read Cycle 







Address 



v 



WHIM 



I/O 
(Output) 



1/0 Y////////////A > 



(Input) 
T5T/0T 



7 



< 



wMML 



* mm , mm *k 



Early Write Cycle 



CX5 



Address 



1^ 



I/O 
(Input) 

I/O 
(Output) 

"DT/OT 



tm 



", <////////////////////, 



■ J////////////////, 



High-Z 



* #///////////////////////////////. 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory c ell. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at ihe falling edge of RAS. 



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Delayed Write Cycle 



HM534251 



T35S 



Address 

/K Row 



T5T/5T 



m 

In 
tori 



I DOS 



Column 



-t«H- 



. — htx _ « lun 



«r» ^KS M ~— Wllllllllllllll, 

(oitp°ut) 



High-Z 



r/^l : Don't care. 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the memory cell. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 



Read-Modlfy-Wrlte Cycle 



X 



X 



TIME 



I/O 
(Output) ' 




> 



mmmmnMM 



/ Valid \ 



W/////////, 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

<$> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 09 



HM534251 Series 

Page Mode Read Cycle 



RAS 
CAS" 

Address 



5: 



2ZZ2 



I/O . 
(Output) 



(Input) 
DT/OT 




Valid 
Dout 




t FF 



t.c, _t,c.H ,,,H 



C Valid ~\ 
Dout / 



*CAC 



Valid 
Dout 



1 Wmfk " Jzzzz 



z 



: Don't care. 



Page Mode Write Cycle (Early Write) 



RAS 



"CAS 



Address 




t.s 

■put) 



(Input) 
I/O 

(Output) , ot J , 



X 



. U7777h . 



mzzzzA 



Valid 
Din 



3= v 



Valid 
Din 



'JZZZZX. 



Valid 
Din 



High-2 



■ V7777T////////////// ///////////////// 

K^XI : Don't care. 



Note: *1. When WE is high level, all the data on I/Os can be written into the memory cell. When WE is low level, the data on I/Os are 
t for the case that the I/O is high at the falling edge of RAS. 



510 



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HM534251 Series 



Page Mode Write Cycle (Delayed Write) 



CS3 



Address 



"WE 



I/O 
(Input) 

I/O 



■ * CD CAS - .„ „ * CAS ^ . 



7A 



»i 



(Output) , 



?^)(^ Y177777) ^W777)^W / / / '/////// 




3EKZZZa^£ZZZZZJ^(ZZZSC2ZZZZZZZ 



Din"' 
Din 




High-Z 



"DT/OT 



K/ZI : Don't care. 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

RAS-Only Refresh Cycle 



RA"5 



CAS 7 



Ml/l/ll/l 



I/O 
(Output) 



I/O 
(Input) 



DT/OT 



zT 



S w//////////////////// 



t DTH 

^///////////////////// 



V7A ■ Don't < 



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511 



HMS34251 Series 



CAS-Before-RAS Refresh Cycle 



RAg 



CAS 



Address 



t.r 



///////////////////////m? 

* V////////////////////////Z 



1/0 v/////////////////////// 



(Input) 

I/O 
(Output) 

DT/OT 



High-Z 



'/////////////////////, 

Y//\ ■ Don't care. 



Hidden Refresh Cycle 



RAS 



CAS 7 




Address 



WE 



I/O . 
(Output) 



t UAH 

ift** 

*ASC 




OT/OE 



I/O 
(Input) 



v^y//// /////////////////, 



?//////////>//// 



Valid Data Out 



i. '° F " . 

P 



High-Z 



Don't ( 



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51 2 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534251 Series 



Read Transfer Cycle (1p '» 



W5 



C*S" l 
Address 7J ^ 



l/O 
(Output) 



»: •'^^7777 ///)///)//////// 



„r„ 'i////////n/n//ui/ij/i////n/i/f iR 



BT/OT 





. , 




t„„ ■ 


(7///// 









I ltM Previous Row — 1 I *■ New Row 



Sl/O 
(Input) 



Previous Row - 
Hioh-7 



'■ Don't cere. 



Notes: *1. When the previous data transfer cycle is a read transfer cycle, it is defined as read transfer cycle (1). 
*2. SE is in low level. (When SE is high, SI/O becomes high impedance.) 



Read Transfer Cycle (2)' 1 



as 



I/O 
(Output) ' 



L#ZZZZZZ£ZZZZ 



7777777 



^ (//// ////////// ///////////// 



High-Z 



(Input) V/////////////7////////////777777 



D7/0T 



Sl/O 
(Output) 



si/o \H 1 "».««■ 




y/////////Tm% Wp77. 



'■ Don't cere 
1004 I Inhibit rising transient 



Notes : * 1 . When the previous data transfer cycle is a write or pseudo transfer cycle, it is defined as read transfer cycle (2). 
*2. SE is in low level. (When SE is high, SI/O becomes high impedance.) 

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513 



HM534251 Series 

Pseudo Transfer Cycle 



WE 



a 



BT/OT 7^ 




VV SAM Slart V/ 

M Mi™. ^_ 

too 



IIIIIIIIIIIIHIIITTTTTI 



VlllllllllllllilHlllllllllllfTTTi 



iiiiiiiiinilljijiinniiiiiiii 

*skdU— » r a. 



^imiiiiiiii^sryTTm 



3 



1 



fZ/^l : Don't care 
KXX] : Inhibit rising transient 
I/O : Don't care 



Note: *1. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 

Write Transfer Cycle 




D7/0T 




V 



;^zzzzzzz 



sc 



JS, ODGZZZZZZZZZZK 



SI/0 



7 




ZZZZZ)C 



High-Z 



(Output) 



V//A ■ Don't care 

KXX : Inhibit rising transient 



Note: M. CAS and SAM start address don't need to be specified every cycle, if SAM sun address is not changed. 

HITACHI 

514 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Serial Read i 



"FftS 



™ ZZZZZZZZZZZZZZZZZZZZZZyf V////////// 



SE 



sc 



SI/0 
(Output) 



taCC- 



(n-1) 



(n) \ 



Valid 
Sout 



> 




(n+2) 



\ r 



Sout 



l«zzx 



Valid 
Sout 



(n + 2) 



Y//X '■ Don't care. 



Serial Write Cycle 



RAS 



t..s 



T5T/0T 
SE 
sc 



///////////////// nm mumm 



J. , ' , 'Jim - r 
. Ucc »f?~" * 5*H-> I'* * | ^ *"l tsw5 »- , 

C j^ZZZ)Cs3^ZZZZ 



tsiS l SiM 

Y7A ■ Don't care. 



Notes: *1. When SE is high level in a serial write cycle, data is not written into SAM, however, the pointer is incremented. 
*2. Address is accessed next to address 511. 



<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 51 5 



HM534252 Series — Preliminary 



262144-Word x 4-Bit Multiport CMOS Video RAM 

The HM534252 is a 1 -Mbit multiport video RAM equipped with a 
256-kword x 4-bit dynamic RAM and a 51 2-word x 4-bit SAM (serial 
access memory). 

Its RAM and SAM operate independently and asynchronously. It 
can transfer data between RAM and SAM and has a write mask 
function. 

It also provides logic operation mode to simplify its operation. In 
this mode, logic operation between memory data and input data can 
be executed by using internal logic-arithmetic unit. 

Features 

• Multiport organization 

Asynchronous and simultaneous operation of RAM and SAM 
capability 

RAM: 256-kword x 4-bit and SAM: 512-word x 4-bit 

• Access time RAM: 100 ns/100 ns/120 ns/150 ns max 

SAM: 30 ns/40 ns/40 ns/50 ns max 

• Cycle time RAM: 190 ns/190 ns/220 ns/260 ns max 

SAM: 30 ns/40 ns/40 ns/60 ns max 

• Low power 

Active RAM: 385 mW max 
SAM: 358 mW max 
Standby 40 mW max 

• High-speed page mode capability 

• Logic operation mode capability 

• 2 types of mask write mode capability 

• Bidirectional data transfer cycle between RAM and SAM capability 

• Real time read transfer capability 

• 3 variations of refresh (8 ms/512 cycles) 

RAS-only refresh 
CAS-before-RAS refresh 
Hidden refresh 

• TTL compatible 



Ordering Information 



Type No. 


Access Time 


Package 


HM534252JP-10 


100 ns 


400-mil 


HM534252JP-11 


100 ns 




HM534252JP-12 


120 ns 


28-pin 


HM534252JP-15 


150 ns 


Plastic SOJ (CP-28D) 


HM534252ZP-10 


100 ns 


400-mil 


HM534252ZP-11 


100 ns 




HM534252ZP-12 


120 ns 


28-pin 


HM534252ZP-15 


150 ns 


Plastic ZIP (ZP-28) 



This document contains information on a new product. Specifications and information 
contained herein are subject to change without notice. 



CP-28D 




ZP-28 



Pin Arrangement 



HM5" 
sc, 

SI/00, 
Sl/Ol , 
DT/OE, 
1/00, 
1/01 1 
WEi 
NCl 
RASl 
ASl 
A6i 
A51 
Ml 
V«l 

a 


I4252JP 

1 2S 

2 27 

3 26 

4 25 

5 24 

6 23 

7 22 

8 21 

9 20 

10 19 

11 18 

12 17 

13 16 

14 15 

op View 


Series 

1 SI/03 
1 SI/02 

>5S 

■ 1/03 
■1/02 

■CAS" 

'NC 

'AO 

■Al 

>A2 

"A3 

>A7 

) 


HM5 

1/02 2 
St 4 
SI/03 S 
SC > 
SI/01 10 

l/OO 12 
RE 14 

RAS 16 
At IS 
A4 20 
A7 22 
A2 24 
AO 26 

CA5 28 

(E 


34252ZP 
oliom V 


Series 

1 NC 
3 1/03 
5 SI/02 
7 V„ 
9 SI/OO 

II CT/0E 

13 1/01 

15 NC 

17 AS 

19 AS 

21 V cc 

23 A3 

25 Al 

27 NC 

ew) 



Pin Description 

Pin Name Function 
A0-A8 Address inputs 
I/O0-I/O3 RAM port data 
outputs 



SI/O0 - 


SAM port data inputs/ 


SI/03 


outputs 


RAS 


Row address strobe 


CAS 


Column address strobe 


WE 


Write enable 


DT/OE 


Data transfer/Output 




enable 


SC 


Serial clock 


SE 


SAM port enable 


Vcc 


Power supply 


Vss 


Ground 


NC 


No connection 




^ HITACHI 

51 6 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Block Diagram 



RAM 



1 DT/OE 



SAM 



511 



I/O 



3t 



Dout 




Din 




Memory 


c 


Array 


1 




3 


Row 







511 














Pointer 








ster 




<5 


f — 


— N 


8? 






t — 


— ^ 


cr 


H 


"5) 






to 




cr 






ra 










Q 

















511 oV> 



Column Address 
(SAM Start Address) 



*J M 



Register 



- TSH 



PinFunction 

RAS (input pin): RAS is a basic RAM signal. It is 
active in low level and standby in high level. Row 
address and signals as shown in table 1 are input atthe 



falling edge of RAS. The input level of those signals 
determine the operation cycle of the HM534252. 



Table 1. Operation Cycles of the HM534252 





Input level at the falling 


edge of RAS 




Operation Cycle 




CAS 


DT/OE 


WE 


SE 






H 


H 


H 


X 


RAM read/write 




H 


H 


L 


X 


Mask write 




H 


L 


H 


X 


Read transfer 




H 


L 


L 


H 


Pseudo transfer 




H 


L 


L 


L 


Write transfer 




L 


X 


H 


X 


CBR refresh 




L 


X 


L 


X 


Logic operation set/reset 




Note: x; 


Don't care. 











CAS (input pin): Column address is put into chip at the 
falling edge of CAS. CAS controls output impedance of 
I/O in RAM. 



A0-A8 (input pins): Row address is determined by 
A0-A8 level at thefalling edge of RAS. Column address 
is determined by A0-A8 level at the falling edge of 
CAS. In transfer cycles, row address is the address on 
the word line which transfers data with SAM data 
register, and column address is the SAM start address 
after transfer. 



WE (input pin): WE pin has two functions ; 
edge of RAS and after. When WE is low at the falling 
edge of RAS, the HM534252 turns to mask write mode. 
According to the I/O level at the time, write on each I/O 
can be masked. (WE level at the falling edge of RAS is 
don't care in read cycle.) When WE is high at the falling 
edge of RAS, a normal write cycle is executed. After 
that, WE switches read/write cycles as in a standard 
DRAM. In a transfer cycle, the direction of transfer is 
determined by WE level at the falling edge of RAS. 
When WE is low, data is transferred from SAM to RAM 



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119 • (415) 589-8300 



517 



HM534252 Series 



(data is written into RAM), and when WE is high, data 
is transferred from RAM to SAM (data is read from 
RAM). 

I/O0-I/O3 (input/output pins): I/ O pi ns function as 
mask data at the falling edge of RAS (in mask write 
mode). Data is written only on high I/O pins. Data on 
low I/O pins are masked and internal data are retained. 
After that, they function as input/output pins as those 
of a standard DRAM. 

DT/OE (input pin): DT/OE pin functions as DT (data 
transfer) pin at the falling edge of RAS and as OE 
(output enable) pin after that. When DT is low at the 
falling edge of RAS, this cycle becomes a tra nsfer 
cycle. WhenDT is high at the falling edge of RAS, RAM 
and SAM operate independently. 

SC (input pin): SC is a basic SAM clock. In a serial read 
cycle, data outputs from an Sl/O pin synchronously 
with the rising edge of SC. In a serial write cycle, data 
on an Sl/O pin at the rising edge of SC is put into the 
SAM data register. 

SE (input pin): SE pin activates SAM. When SE is high, 
Sl/O is in the high impedance state in serial read cycle 
and data on Sl/O is not put into the SAM data register 
in serial write cycle. SE can be used as a mask for 
serial write because internal pointer is incremented at 
the rising edge of SC. 

SI/O0-SI/O3 (input/output pins): Sl/Os are input/output 
pins in SAM. Direction of input/output is determined by 
the previous transfer cycle. When it was a read transfer 
cycle, Sl/O outputs data. When it was a pseudo 
transfer cycle or write transfer cycle, Sl/O inputs data. 

Operation of HM534252 

Operation of RAM Port 
RAMRead C ycle 

(DT/OE high, CAS high, at the falling edge of RAS) 

Row address is entered at the RAS falling edge and 
column address at the CAS falling edge to the device 
as in standard DRAM. Then, when WE is high and DT/ 
OE is low while CAS is low, the selected address data 
outputs t hroug h I/O pin. Atthe falling edge of RAS, DT? 
DE" and CAS become high to distinguish RAM read 
cycle from transfer cycle and CBR refresh cycle. 
Address access time (Iaa) and RAS to column address 
delay time (tflAo) specifications are added to enable 



high-speed page mode. 
RAM Write Cycle 

(EarlyWrlte, Delayed Write, Read-Modify-Write) 

(DT/OE high, CAS high at the falling edge of RAS) 

• Normal Mode Write Cycle 

(WE high at the falling edge of RAS) 

When CAS and WE are set low after RAS is set low, 
a write cycle is executed and I/O data is written at the 
selected addresses. When all 4 l/Os are written, WE 
should be high at the falling edge of RAS to distinguish 
normal mode from mask write mode. 

If WE is set low before the CAS falling edge, this cycle 
becomes an early write cycle an d I/O becomes high 
impedance. Data is entered at the CAS falling edge. 

If WE is set low after the CAS falling edge, this c ycle 
becomes a delayed write cycle. Data is input at the WE 
falling edge. I/O does not become high impedance in 
this cycle, so data should be entered with OE in high. 

If WE is set low after Icwd (min) and tAwo (min) after 
the CAS falling edge, this cycle becomes a read-modify- 
write cycle and enables write after read to execute in the 
same address cycle. In this cycle also, to avoid I/O 
contention, data should be input after reading data and 
setting OE high. 

• Mask Write Mode (WE low at the falling edge of RAS) 

If WE is set low at the falling edge of RAS, the cycle 
becomes a mask write mode cycle which writes only to 
selected I/O. Whether or not an I/O is written depends on 
I/O level (mask data) at the falling edge of RAS. Then the 
data is written in high I/O pins and masked in low ones 
and internal data is preserved . This mask data is effective 
during the RAS cycle. So, in high-speed page mode 
cycle, the mask data is preserved during the page 
access. 

High-Speed Page Mode Cycle 

(DT/OE high, CAS high at the falling edge of RAS) 

High-speed page mode cycle reads/writes the data 
of the same row address at high speed by toggling CAS 
while RAS is bw. Its cycle time is one third of the random 
read/write cycle and is higher than the standard page 
mode cycle by 70-80%. This product is based on static 
column mode, therefore address access time (tAA), RAS 



HITACHI 

518 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534252 Series 



to column address delay time (tRAD), and access time 
from CAS precharge (tACp) are added. In one RAS 
cycle, 51 2-word memory cells of the same row address 
can be accessed. It is necessary to specify access 
frequency within tRAs max (1 us). 

Transfer Operation 

The HM534252 provides the transfer cycle, pseudo 
transfer cycle, and write transfer cycle as data transfer 
cycles. These transfer cycles are set by driving DT/OE 
low at the falling edge of RAS. 

They have following functions: 

(1 ) Transfer data between row address and SAM data 
register (except for pseudo transfer cycle) 

(2) Determine direction of data transfer 

(a) Read transfer cycle: RAM -> SAM 

(b) Write transfer cycle: RAM*- SAM 

(3) Determine input or output of SAM I/O pin (Sl/O) 
Read transfer cycle: Sl/O output 
Pseudo transfer cycle, 

write transfer cycle: Sl/O input 



(4) Determine first SAM address to access (SAM start 
address) aftertransferring at column address. When 
SAM start address is not changed, neither CAS nor 
address need to be set because SAM start address 
can be latched internally. 

Read Transfer Cycl e (CA S high, DT/OE low, WE high 
at the falling edge of RAS) 

This cycle becomes read transfer cycle by driving 
DT/OE low and WE high at the falling edge of RAS. The 
row address data (512x4 bit) determined by this cycle 
is transferred synchronously at the rising edge of DT/ 
OE. After the rising edge of DT/OE, the new address 
data outputs from SAM start address determined by 
column address. 

This cycle can access SAM serially even during 
transfer (real time read transfer). In this case, the timing 
tsDD (min) is specified between the last SAM access 
before transfer and DT/OE rising edge, and tsDH(min) 
between the first SAM access and DT/OE rising edge 
(see figure 1). 



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Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 1 9 



RAS 



CAS 



V 



J 



\ 



f 



Address 





1 * X y ' )C 



DT/OE 



SC 



s >/° A A A A J 


\ Yj )( Y i + , 




SAM Data Bel 


ore Transfer 


SAM Data After Transfer 



Figure 1. Real Time Read Transfer 



If read transfer cycle is executed, Sl/O becomes 
output state. When the previous transfer cycle is either 
pseudo transfer cycle or write transfer cycle and Sl/O 
is in Input state, uncertain data outputs after tRLz(min) 
after the RAS falling edge. Before that, input should be 
set high impedance to avoid data contention. 

Pseudo Transfer Cycle (CAS high, D T/OE low, WE 
low, and SE high at the falling edge of RAS) 

Pseudo transfer cycle is available for switching 
Sl/O from output state to input state because data in 
RAM isn't rewritten. This cycle starts when CAS is 
high, DT/OE low, WE low, and'SE high, at the falling 
edge of RAS. The output buffer in Sl/O becomes high 
impedance within tsRZ (max) from the RAS falling 
edge. Data should be input to Sl/O later than tsiD (min) 
to avoid data contention. SAM access becomes enabled 
after tsRD (min) after RAS becomes high. In this cycle, 
SAM access is inhibited during RAS low, therefore, SC 
should not be raised. 



WriteTransfer Cycle (CAS high , DT/O E low, WE low, 
and SE low at the falling edge of RAS) 

Write transfer cycle can transfer a row of data input 
by serial write cycle to RAM. The row address of data 
transferred into RAM is determined by the address at 
thef ailing edge of RAS. The column address is specified 
as the first address to serial write after terminating this 
cycle. Also in this cycle, SAM access becomes enabled 
after tsRD (min) after RAS becomes high. SAM access is 
inhibited during RAS low. In this period, SC should not 
be raised. 

SAM Port Operation 

Serial Read Cycle 

SAM port is in read mode when the previous data 
transfer cycle is read transfer cycle. Access is 
synchronized with SC rising, and SAM data is output 
from Sl/O. tf SE is set high Sl/O becomes high 
impedance and internal pointer is incremented at the 



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520 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Serial Write Cycle 

If previous data transfer cycle is pseudo transfer 
cycle or write transfer cycle, SAM port goes into write 
mode. In this cycle, Sl/O data is programmed into data 
register at the SC rising edge like in the serial read 
cycle. If SE is high, Sl/O data isn't input into data 
resister. Internal pointer is incremented according to 
the SC rising edge, so SE high can mask data for SAM. 

Refresh 

RAM Refresh 

RAM, which is composed of dynamic circuits, 
requires refresh to retain data. Refresh is performed 
by accessing all 51 2 row addresses every 8 ms. There 
are three refresh cycles: (1) RAS-only refresh cycle, 
(2) CAS-before-RAS (CBR) refresh cycle, and (3) 
Hidden refresh cycle. Besides them, the cycles which 
activate RAS such as read/write cycles or transfer 
cycles can refresh the row address. Therefore, no 
refresh cycle is required for accessing all row addresses 
every 8 ms. 

RAS-Only Refresh Cycle: RAS-only refresh cycle is 
performed by activating only RAS cycle with CAS fixed 
to high by inputting the row address (= refresh address) 
from external circuits. In this cycle, output is high- 
impedance and power dissipation is less than that of 
normal read/write cycles because CAS internal circuits 
don't operate. To distinguish this cycle from data 
transfer cycle, DT/OE should be high at the falling 
edge of RAS. 

CBR Refresh Cycle: CBR refresh cycle is set by 
activating CAS before RAS. In this cycle, refresh 
address need not to be input through external circuits 
because it is input through an internal refresh counter. 
In this cycle, output is in high impedance and power 
dissipation is lowered like in RAS-only refresh cycles 
because CAS circuits don't operate. To distinguish this 
cycle from logic operation se t/rese t cycle, WE should 
be high at the falling edge of RAS. 

Hidden Refresh Cycle: Hidden refresh cycle 
performs refresh by reactivating RAS when DT/OE 
and CAS keep low in normal RAM read cycles. 

SAM Refresh 

SAM parts (data register, shift register, selector), 
organized as fully static circuitry, don't require refresh. 



Logic Operation Mode 

The HM534252 supports logic operation capability 
on RAM port, it performs logic operations between the 
memory cell data and input data in logic operation 
mode cycle, and writes the result into the memory cell 
(read modify write). This function realizes high speed 
raster operations and simplifies peripheral circuits for 
raster operations. 

Logic Operation Se t/Res et Cycle (CAS and WE Low 
at the falling edge of RAS) 

In logic operation set/reset cycle, the following 
operations are performed at the same time; 1 . Selection 
of logic operations and logic operation mode set/reset, 
2. Mask data prog ramm ing , 3. CAS-before-RAS refresh. 

Figure 2 shows the timing for logic operation set/ 
reset cycle. This cycle starts when CAS and WE are low 
at the falling edge of RAS. In this cycle, logic operation 
codes and mask data are programmed by row address 
and I/O pin at the falling edge of RAS respectively. 
When write cycle is performed after this cycle, the logic 
operation write cycle starts. In the logic operation 
mode, the specification of cycle time is longer than that 
of normal mode because read-modify-write cycle is 
performed internally. In this cycle, logic operation codes 
and mask data programmed are available until 
reprogrammed. In normal mode, maskdata is available 
only for one RAS cycle. Here, the mask data 
programmed in normal mode is named as "temporary 
mask data" and the one programmed in logic operation 
set/reset cycle is named as "mask data". 

(l)Selection of logic operations and logic operation 
mode set/reset 

Table 2 shows the logic operations. One operation 
is selected among sixteen ones by combinations of A0- 
A3 levels at the falling edge of RAS. (A4-A8 are Don't 
care.) Logic operation codes (A3, A2, A1 , AO) = (0, 1 ,0, 1 ) 
resets the logic operation mode. When write cycle is 
performed afterthat, normal write cycle starts. However, 
even in this case, mask data is still available. I/O should 
be at high level at the falling edge of RAS in logic 
operation set/reset cycle when mask data is not used. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 521 



HM534252 Series 



(2)Mask data programming 

High/tow level of I/O at the falling edge of RAS 
functions as mask data. When I/O is high, the data is 
written in write cycle. When I/O is low, the input data is 



masked and the same memory cell data remains. 
Mask data, programmed in this cycle, is available 
until reprogrammed. It is advantageous when the 
same mask data continues. 



RAS 



CAS 



\ 



I 



— 

















A0-A3 




i 

j\ Logic Code 


t 




















WE 




\ 


L 






/ 
















I/O0-I/O3 




)( Mask 


Data 


I 


















Figure 2. Logic Operation Set/Reset 
Table 2. Logic Code 








Logic Code 




— Symbol 


Write Data 


Note 


A3 


A2 


Al 


AO 
















Zero 
















1 


AND1 


Di-Mi 










1 





AND2 


Di-Mi 


Logic operation mode set 








1 


1 




Mi 







1 








AND3 


Di-Mi 







1 





1 


THROUGH 


Di 


Logic operation mode reset 





1 


1 





EOR Di • 


Mi + Di • Mi 







1 


1 


1 


OR1 


Di + Mi 















NOR 


Di-Mi 












1 


ENOR Di ■ 


Mi + Di ■ Mi 









1 





INV1 


Di 


Logic operation mode set 







1 


1 


OR2 


Di + Mi 




1 








INV2 


Mi 






1 





1 


OR3 


Di + Mi 






1 


1 





NAND 


Di + Mi 






1 


1 


1 


One 


1 





Notes: Di; External data-in 

Mi; The data of the memory cell 



522 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534252 Series 



MS 



"CAS 



WE 



l/OO 



1/01 



1/02 



1/03 



Logic 



Remarks 



Logic operation 
set/reset cycle 



Mask data is set. 
I/01, 2: Masked 
Assume that the 
logic is set to 
•AND1" 



Write cycle 



r 



"0"Write 



Masked 



Masked 



'TWrite 



Write cycle 



r 



Masked 



f 



"1 "Write 



V 



'0"Write 



Masked 



THROUGH 



Temporary mask 
data is set, and 
valid only in this 
cycle. 

I/OO, 3: Masked 



Write cycle Write cycle 



A— I 



"1 "Write 



Masked 



"(TWrite 







Masked 



/ 



Masked 



J "1 "Write 



AND) 







Figure 3. 2 Types of Mask Write Function and Logic Operation 




Also, temporary maskdata is programmed by falling 
WE at the falling edge of RAS in logic operation mode 
cycle after mask data is programmed in logic operation 
set/reset cycle. In this case, temporary mask data is 
available only for one cycle. 

Logic operation is reset during temporary mask 
write cycle. It means that external input data is written 
into I/O when temporary mask data is set. Figure 4 
shows write mask and logicoperations. Thesefunctions 



are useful when RAM port is devided into frame buffer 
area and data area, as they save the need to reprogram 
logic operation codes and mask data. 

Write Cycle In Logic Operation Mode 
(Early Write, Delayed Write, Page Mode) 

Write cycle after logic operation set cycle is logic 
operation mode cycle. In this cycle, the following read- 
modify-write operation is performed Internally. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534252 Series 



(1) Reading memory data in given address into internal (3) Writing the result ot (2) into address given by (1) 
bus. 



2) Performing operation between input data and 
memory data 









Read 1-word source data 






Read 1-word destination data 


! 






Execute logic operation between source data 
and destination data 


\ 


t 




Write the result of operation into the destination 
address 







(a) Normal Mode 



(b) Logic Operation Mode 

Figure 4. Sequence of Raster Operation 





Execute logic operation set/reset cycle 




/ 


H 




Read 1 - word source data 








Write read data into the destination address 








Figure 4 shows sequence of raster operation. Raster executed in one write cycle of logic operation mode. It 
operation which needs 3 cycles (destination read, makes raster operation faster and simplifies peripheral 
operation, destination write) in normal mode can be hardware for raster operation. 



Absolute Maximum Ratings 



Item 




Symbol 




Rating 




Unit 


Terminal voltage *' 




Vt 




-1.0 to +7.0 




V 


Power supply voltage *' 




Vcc 




-0.5 to +7.0 




V 


Power dissipation 




Pt 




1.0 




W 


Operating temperature 




Topr 




to +70 




°C 


Storage temperature 




Tstg 




-55 to +125 




°C 


Note: *1. Relative to Vss. 














Recommended DC Operating Conditions (Ta 


= to +70°C) 








Item 


Symbol 


Min 


Typ 




Max 


Unit 


Supply voltage* 1 


Vcc 


4.5 


5.0 




5.5 


V 


Input high voltage *' 


Vm 


2.4 






6.5 


V 


Input low voltage *•' 


Vn. 


-0.5* 2 






0.8 


V 



Notes: *I. All voltages referenced to Vss. 

*2. -3.0 V for pulse width < 10 ns. 



<§> HITACHI 

524 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



■ DC CHARACTERISTICS (T a = to 70°C, V cc = 5V ± 10%, V ss = 0V) 



Item 


Symbol 




Test Conditions 


HM53* 


252-10 


HM534252-I1 


HM534252-I2 


HM534252-I5 


Unit 


Notes 


RAM Port 


SAM Port 


Min. 




Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Operating 


■cci 


RAS, CAS Cycling 


SC = V IL . SE = v 1H 


- 


70 


- 


70 


- 


60 


- 


55 


mA 


1.2 


Current 


'CC7 


t RC = Min. 


SE = V, L . SC Cycling t scc = Min. 


- 


120 




120 


- 


100 


- 


85 


mA 


Standby 


r CC2 


RAS. CAS = V| H 


SC = V |L . SE = V IH 


- 


7 




7 


- 


7 


- 


7 


mA 




Current 


'CC8 


SE = V| L , SC Cycling t^c = Min. 


- 


65 




55 




55 




40 


mA 




RAS-Only 

Refresh 

Current 


■ccj 


RAS Cycling 
CAS = V| H 
'rc = Min. 


SC = V |L . SE = V IH 


- 


70 


- 


70 


- 


60 


- 


55 


mA 


2 


■cC9 


SE = V, L . SC Cycling t scc = Min. 


- 


120 




120 


— 


100 


— 


85 


mA 


Page Mode 


'CC4 


CAS Cycling 
RAS = V, L 
t RC = Min. 


SC = V IL . SE = V IH 




80 




80 




70 




60 


mA 


1. 3 


Current 


'ccio 


SE = V| L , SC Cycling t scc = Min. 


— 


130 


— 


130 


— 


110 


— 


90 


mA 


CAS-Before- 
RAS Refresh 
Current 


'cC5 


RAS Cycling 


SC = V IL . SE = V IH 




60 




60 




50 




40 


mA 




'ecu 


'RC = Min. 


SE = V, L , SC Cycling t^ = Min. 




110 


- 


110 




90 


- 


70 


mA 




Data 
Transfer 


'CC6 


RAS. CAS 


SC = V, L . SE = V, H 




95 




95 




90 




85 


mA 


2 




Cycling t RC = Min. 


SE = V| L . SC Cycling = Min. 




135 


- 


135 


- 


125 


- 


115 




Input 

Leakage 

Current 


■li 




H) 


10 


-10 


10 


-10 


10 


-10 


10 


pA 




Output 

Leakage 

Current 


'lo 




-10 


10 


-10 


10 


-10 


10 


-10 


10 


«A 




Output High 
Voltage 


V OH 


Iqh = -2mA 


2.4 




2.4 




2.4 




2.4 




V 




Output Low 
Voltage 


V OL 


I 0L = 4.2mA 




0.4 








0.4 




0.4 


V 





NOTES: 1 . Ice depends on output loading condition when the device is selected. Ice max. is specified at the output open condition. 

2. Address can be changed less than three times while RAS = Vil. 

3. Address can be changed once or less while CAS = Vi H . 



Capacitance (Ta = 


25°C, Vcc= 5 V, f = 1MHz, Bias: Clock, I/O = 


Vcc, address = Vss) 




— - 

Item 


Symbol Min Typ 


Max 


Unit 


Address 


Cn — — 


5 


pF 


Clock 


Cl2 — — 


5 


PF 


I/O, SI/O 


Cvo — — 


7 


P F 

















HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sietra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 25 



HM534252 Series 

AC Characteristics ( Ta = to +70°C, Vcc = 5 V ± 10%, Vss = V ) ''• 

Test Conditions 

Input rise and fall time: 5 ns 

Output load: See figures 

Input timing reference levels: 0.8 V, 2.4 V 

Output timing reference levels: 0.4 V, 2.4 V 

i 



Output Load (A) Output Load (B) 

+ 5V +5V 




Note: *1. Including scope & jig. 



• Common Parameter 



Parameter 


Symbol 


HM534252-10 


HM534252-11 


HM534252-12 


HM534252-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Random Read or 
Write Cycle Time 


l RC 


190 




190 




220 




260 




ns 




RAS Precharge Time 


l RP 


80 




80 




90 




100 




ns 




RAS Pulse Width 


l RAS 


100 


10000 


100 


10000 


120 


10000 


150 


10000 


ns 




CAS Pulse Width 


k;AS 


30 


10000 


30 


10000 


35 


10000 


40 


10000 


ns 




Row Address Setup Time 


l ASR 






















ns 




Row Address Hold Time 


l RAH 


15 




15 




15 




20 




ns 




Column Address Setup Time 


l ASC 






















ns 




Column Address Hold Time 


l CAH 


20 




20 




20 




25 




ns 




RAS to CAS Delay Time 


l RCD 


25 


70 


25 


70 


25 


85 


30 


110 


ns 


5, 6 


RAS Hold Time 


tRSH 


30 




30 




35 




40 




ns 




CAS Hold Time 


fcsH 


100 




100 




120 




150 




ns 




CAS to RAS Precharge Time 


tCRP 


10 




10 




10 




10 




ns 




Transition Time (Rise to Fall) 


t T 


3 


50 


3 


50 


3 


50 


3 


50 


ns 


8 


Refresh Period 


l REF 




8 




8 




8 




8 


ms 




DT to RAS Setup Time 


l DTS 






















ns 




DT to RAS Hold Time 


l DTH 


15 




15 




15 




20 




ns 




Data-in to OE Delay Time 


l DZO 






















ns 




Data-in to CAS Delay Time 


'dzc 






















ns 





HITACHI 

526 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534252 Series 



• Read Cycle (RAM), Page Mode Read Cycle 



Parameter 


Symbol 


HM534252-10 


HM534252-11 


HM534252-12 


HM534252-15 


Unit 


Notes 




Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Access Time From RAS 


'RAC 


- 


100 




100 




120 




150 


ns 


2, 3 


Access Time From CAS 














JJ 




A(\ 
4U 


ns 


3, 5 


Access Time From OE 


tOAC 




30 




30 




35 




4U 


ns 


J 


Address Access Time 


'aa 




4j 












/U 


ns 


J, o 


Output Butter lurn Utt Delay 
Referenced to CAS 


tOFFI 




25 




25 




30 




40 


ns 


1 


output Butter turn ott Delay 
Referenced to OE 


k)FF2 




25 




25 




30 




40 


ns 


7 


Read Command Setup Time 


'rCS 


U 




K) 




r\ 
U 




n 
U 




ns 




Read Command Hold Time 


( RCH 






u 




K) 




U 




ns 


Lfi 


Keau Command Hold lime 
Referenced to RAS 


'rRH 


10 




10 




10 




10 




ns 


12 


RAS to Column Address 
Delay Time 


'RAD 


20 


55 


20 


55 


20 


65 


25 


80 


ns 


5, 6 


Page Mode Cycle Time 


tp C 


55 




55 




65 




80 




ns 




CAS Precharge Time 


k;p 


10 




10 




15 




20 




ns 




Access Time From CAS 
Precharge 


l ACP 




50 




50 




60 




75 


ns 





• Write Cycle (RAM), Page Mode Write Cycle 



Parameter 


Symbol 


HM534252-10 


HM534252-11 


HM534252-12 


HM534252-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Command Setup Time 


'wcs 






















ns 


9 


Write Command Hold Time 


'WCH 


25 




25 




25 




30 




ns 




Write Command Pulse Width 


'\VP 


15 




15 




20 




25 




ns 




Write Command to RAS 
Lead Time 


'rwl 


30 




30 




35 




40 




ns 




Write Command to CAS 
Lead Time 




30 




30 




35 




40 




ns 




Data-in Setup Time 


•ds 






















ns 


10 


Data-in Hold Time 


'dh 


25 




25 




25 




30 




ns 


10 


WE to RAS Setup Time 


'ws 






















ns 




WE to RAS Hold Time 


%H 


15 




15 




15 




20 




ns 




Mask Data to RAS Setup Time 


'MS 






















ns 




Mask Data to RAS Hold Time 


l MH 


15 




15 




15 




20 




ns 




OE Hold Time Referenced 
to WE 


k)EH 


10 




10 




15 




20 




ns 




Page Mode Cycle Time 


'PC 


55 




55 




65 




80 




lis 




CAS Precharge Time 


'CP 


10 




10 




15 




20 




ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 527 



HM534252 Series 



• Read-Modify-Write Cycle 



Parameter 


Symbol 


HM534252-10 


HM534252-11 


HM534252-12 


HM534252-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Read Modify Write Cycle Time 


'rwc 


255 


_ 


255 


~ 


295 




350 




ns 




RAS Pulse Width 


l RWS 


165 


10000 


165 


10000 


195 


10000 


240 


10000 


ns 




CAS to WE Delay 


tcwD 


65 




65 


T 


75 




90 




ns 


9 


Column Address to WE Delay 


l AWD 


80 




80 




95 




120 




ns 


9 


OE to Data-in Delay Time 


k>DD 


25 


— 


25 


— 


30 


— 


40 


- 


ns 




Access Time From RAS 


l RAC 


— 


100 


— 


100 


— 


120 


— 


150 


ns 


2, 3 


Access Time From CAS 


'CAC 




30 




30 




35 




40 


ns 


3, 5 


Access Time From OE 


tOAC 





30 





30 





35 





40 


ns 


3 


Address Access Time 


t AA 




45 




45 




55 




70 


ns 


3, 6 


RAS to Column Address Delay 


l RAD 


20 


55 


20 


55 


20 


65 


25 


80 


ns 


5,6 


Output Buffer Turn-Off 
Delay Referenced to OE 


tOFF2 




25 




25 




30 




40 


ns 




Read Command Setup Time 


•rcs 





— 





— 





— 





— 


ns 




Write Command to RAS 
Lead Time 


*RWL 


30 




30 




35 




40 




ns 






Write Command to CAS 
Lead Time 


tcWL 


30 




30 




35 




40 




ns 




Write Command Pulse Width 


l WP 


15 




15 




20 




25 




ns 




j — * t ^ n-i» 

Data-in Setup Time 


l DS 





— 





— 





— 







ns 


10 


Data-in Hold Time 


l DH 


25 




25 




25 




30 




ns 


10 


WE to RAS Setup Time 


l WS 






















ns 




WE to RAS Hold Time 


l WH 


15 




15 




15 




20 




ns 




Mask Data to RAS Setup Time 


l MS 





















Mask Data to RAS Hold Time 


l MH 


15 




15 




15 




20 




ns 




OE Hold Time Referenced 
to WE 


l OEH 


10 




10 




15 




20 




ns 




• Refresh Cycle 


Parameter 


Symbol 


HM534252-10 


HM534252-11 


HM534252-12 


HM534252-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


CAS Setup Time 
(CAS-Before-RAS Refresh) 


tcSR 


10 




10 




10 




10 




ns 




CAS Hold Time 
(CAS-Before-RAS Refresh) 


'CHR 


20 




20 




25 




30 




ns 




RAS Precharge to CAS 
Hold Time 


'rpc 


10 




10 




10 




10 




ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Transfer Cycle 



Parameter 


Symbol 


HM534252-10 


HM534252-11 


HM534252-12 


HM534252-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


WE to RAS Setup Time 


tws 






















ns 




WE to RAS Hold Time 




15 




15 




15 




20 




ns 




SE to RAS Setup Time 


tgS 






















ns 




SE to RAS Hold Time 


tgj-j 


15 




15 




15 




20 




ns 




RAS to SC Delay Time 


^SRD 


25 




30 




30 




35 




ns 




SC to RAS Setup Time 


tsRS 


30 


- 


40 


- 


40 


- 


45 


- 


ns 




DT Hold Time From RAS 


l RDH 


80 




90 




90 




110 




ns 




DT Hold Time From CAS 


*CDH 










JU 




*+J 




ns 




T ast SP to DT Delav Time 

A_/CLOV kJ V_ |U L/ 1 L/wloy JLilll^ 


l SDD 


5 


- 


5 


- 


5 


- 


10 


- 







First SC to DT Hold Time 


l SDH 


20 




25 




25 




30 




ns 




DT to RAS Lead Time 


l DTL 


50 


— 


50 


— 


50 


— 


50 


— 


ns 




DT Hold Time Referenced 
to HAS High 


^DTHH 


20 


- 


25 


- 


25 


- 


30 


- 


ns 





DT Precharge Time 


'dtp 


30 




35 




35 




40 




ns 




Serial Data Input Delay 
Time from RAS 


'SID 


50 




60 




60 




75 




ns 




Serial Data Input to 
KAS Delay lime 


'SZR 




10 




10 




10 




10 


ns 




Serial Output Buffer Turn-Off 

Delav From RAS 


l SRZ 


10 


50 


10 


60 


10 


60 


10 


75 


ns 




7 


Delay Time 


l RLZ 


5 


— 


10 


— 


10 


— 


10 


- 


ns 




Serial Clock Cycle Time 


l scc 


30 




40 




40 




60 




ns 




Serial Clock Cycle Time 


'SCC2 


40 




40 




40 




60 




ns 


13 


Access Time From SC 


'SCA 




30 




40 




40 




50 


ns 


4 


Serial Data Out Hold Time 


l SOH 


7 




7 




7 




7 




ns 


4 


SC Pulse Width 


l SC 


10 




10 




10 




10 




ns 




SC Precharge Width 


tscp 


10 




10 




10 




10 




ns 




Serial Data-in Setup Time 


l SIS 






















ns 




Serial Data-in Hold Time 


£ SIH 


15 




20 




20 




25 




ns 





• Serial Read Cycle 



Parameter 


Symbol 


HM534252-10 


HM534252-11 


HM534252-12 


HM534252-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Serial Clock Cycle Time 


l SC( 




30 




40 




40 




60 




ns 




Access Time From SC 


l SCA 




30 




40 




40 




50 


ns 


4 


Access Time From SE 


l SEA 




25 




30 




30 




40 


ns 


4 


Serial Data-Out Hold Time 


t S OH 


7 




7 




7 




7 




ns 


4 


SC Pulse Width 


'sc 


10 




10 




10 




10 




ns 




SC Precharge Width 


tscp 


10 




10 




10 




10 




ns 




Serial Output Buffer Turn-Off 
Delay From SE 


l SEZ 




25 




25 




25 




30 


ns 


7 


Hitachi America, Ltd. • Hitac 


HITACHI 

hi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 529 



HM534252 Series — 
* Serial Write Cycle 



Parameter 


Symbol 


HM534252-10 


HM534252-11 


HM534252-12 


HM534252-15 


Unit 


Notes 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Serial Clock Cycle Time 


'sec 


30 




40 




40 




60 




ns 




i>L, rulse Wiutn 


l SC 


10 




10 




10 




10 




ns 




at rrecnarge wiatn 


l SCP 


10 


- 


10 


— 


10 


- 


10 


— 


ns 




Serial Data-in Setup Time 


'sis 






















ns 





Serial Data-in Hold Time 


•.SIH 


15 





20 





20 





25 


— 


ns 




Serial Write Enable 
Setup Time 























ns 




Serial Write Enable Hold Time 


l SWH 


30 




35 




35 




50 




ns 




Serial Write Disable 
Setup Time 


'swis 






















ns 




Serial Write Disable 
Hold Time 


1 SW1H 


30 




35 




35 




50 




ns 




• Logic Operation Mode 




HM534252-10 HM534252-U 


HM534252-12 


HM534252-15 


Unit 


Notes 










Max. 


Min. 


Max. 


Min. 


Max. 


CAS Hold Time (Logic 
Operation Set/Reset Cycle) 


l FCHR 


90 




90 




100 




120 




ns 




RAS Pulse Width in 
Write Cycle 


l RFS 


140 


10000 


140 


10000 


165 


10000 


200 


10000 


ns 




CAS Pulse Width in 
Write Cycle 


l CFS 


60 


10000 


60 


10000 


70 


10000 


80 


10000 


ns 




CAS Hold Time in Write Cycle 


l FCSH 


140 




140 




165 




200 




ns 




RAS Hold Time in Write Cycle 


l FRSH 


60 




60 




70 




80 




ns 




Write Cycle Time 


l FRC 


230 




230 




265 




310 




ns 




Page Mode Cycle Time 
(Write Cycle) 


l FPC 


85 




85 




100 




120 




ns 





NOTES: 1 . AC measurements assume tT = 5ns. 



2. Assume that (rcd s Ircd (max.) and Irad s tRAD (max.). If tRCD or irad is greater than the maximum 
recommended value shown in this table, tRAC exceeds that value shown. 

3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 

4. Measured with a load circuit equivalent to 2 TTL loads and 50 pF. 

5. When tRCD ^ tRCD (max.) and tRAD S tRAD (max.), access time is specified by tcAC 

6. When tRCD S Ircd (max.) and tRAD £ tRAD (max.), access time is specified by tAA. 

7. toFF (max.) is defined as the time at which the output achieves the open circuit condition (Vqh - 200mV, V l + 
200mV). 

8. Vih (min.) and Vu. (max.) are reference levels for measuring timing of input signals. Transition times are measured 
between Vih and Vn_. 

9. When twes ^ twes (min.), the cycle is an early write cycle, and I/O pins remain in an open circuit (high 
impedance) condition. When Iawd ^ iawd (min.) and tcwD 2 tcwD (min.), the cycle is a read-modify-write cycle; 
the data of the selected address is read out from a data output pin and input data is written into the selected address. 
In this case, impedance on I/O pins is controlled by OE. 

10. These parameters are referenced to CAS falling edge in early write cycles or to WE falling edge in delayed write or 
read-modify-write cycles. 

11. After power-up, pause for 100 /is or more and execute at least 8 initialization cycles (normal memory cycles or 
refresh cycles), then start operation. 

12. If either Irch or Irrh is satisfied, operation is guaranteed. 

13. tscC2 is defined as the last SAM cycle time before read transfer in read transfer cycle (1). 



530 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534252 Series 



Timing Waveforms 
Read Cycle 



RAS 



CAS — 



Address 



> 


tuCD 


a ** SM ■ 


tcSK 





Row 



Column 



W//////////M 



I/O 
(Output) 



/0 W///////////A *. 



(Input) 
DT/OT 



\ 4///////////7/////////). 



< 



r . c 



Valid 



Early Write Cycle 



RAS 



CAS 



Address ~%C 
1 



WE 



/0 M 



(Input) 



I/O 
(Output) 



DT/OE 



//// 



High-Z 



^////////////////////MMl/, 



: Don't care 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the memory cell. When WE is low level, the data on I/Os a 
not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 531 



HM534252 Series 



Delayed Write Cycle 



RAS 



TTf/OE 



^ 111111 1111111111. 



' 1 1 in 1 1 1 1 

'ilium 



^zEj^ELynnnniiinm 



I/O 
(Output)" 



High-Z 



fc'ZI : Don't care. 



Note: *1. When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

Read-Modify- Write Cycle 



RAS 



CAS 



WE 



(Input) 



I/O 
(Output) 



DT/OT ' 





1 HWC 

t RWS 

v — — r 




'lit 




\ 


/ 








Column )<^/ 


ujtmmji 


///////// 


In 


'"» tea 




t D S ( DH 


RTflr ' 

-<//, 


w/// 




v — 


{' 

t0OD - 

y- Valid 


V 


V//I/////H/, 




toio , 

^DTH 


t M V Dout 
t *c tor 


r 

2 ton* 






V, 




1 


W///////// 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

532 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Page Mode Read Cycle 







RAS 
CA5 

Address 

m 

I/O _ 
(Output) 



\ 



X 



I/O 
(Input) 



HUM 



< 



I— -jt.c, t« CH -J nJ-fH'"" I— I'"" !"■>«!■ I . '»CH t*H '"" 



Valid 
Dout 



\ / 



; L valid J ; 

\ Dout / 



4 



Valid 
Dout 



mm 

Y/A '■ Don't care. 



Page Mode Write Cycle (Early Write) 



RAS 



•a: 



I/O 
(Input) 



(Output) 



"DT/OT 



1 : 

t.«c t 



7 



Val.d 

Din 



Jl7777h . 



mzzK 



Valid 
Din 



\annL 



wlwhuzl 



High-Z 



V//////////////////////////////7 UI11 



Y/A : Don't care. 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 33 



Page Mode Write Cycle (Delayed Write) 



HAS 



1 "CO t CAS 



7K 



- TAEWZZZM 

i/o ^7v r 
(input) /yY 



I/O . 
(Output) 



«4j^ 


tos 








' *l 1 


m 


Valic 
, Din 









•• //////////. 



DT/OE 



y////////// 

Y// X '■ Don't care. 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

RAS-Only Refresh Cycle 



RAS 



Address TJj 



yiiiiiin 



5 M////////////////// 



I/O 
(Output) 



I/O 
(Input) 



DT/OE 



22* 



Hi/n/iiiii/i/ini/ii, 

V/A '■ Don't care. 



1 



HITACHI 

534 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



CAS-Before-RAS Refresh Cycle 



RAS 



CAS 



Address 



to. 



S///////////////////////Z ZZ 
V////7/////////////////77Z 
/0 '////////////////////////, 



"WE 



(Input) 

I/O 
(Output) 



High-Z 



— '////////////////////// 



Y//\ ■ Don't care. 



Hidden Refresh Cycle 



RAS 



CAS 7 



Address 




Row 



X 



WE 



7ZZS 



I/O . 
(Output) 



DT/OT 



I/O 
(Input) 



V/////////////Z 



Valid Data Out 



> 



High-Z 



Y/A : Don't care. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 535 



Read Transfer Cycle (1) 1 2 



SS5 
5S5 



I/O 
(Output) 

I/O 
(Input) 

UT/OT 



-- [////////////////////////////. 



V///////////////////////////////Z ZZZ2 



Si/O 77V — ^nT 
(Output) /A fs±. 



CZZZL 



SI/O 
(Input) 



t.,. Previous Row-" I — - - New Row 



'■ Don't care 



Notes : * 1 . When the previous data transfer cycle is a read transfer cycle, it is defined as read transfer cycle (1 ). 
*2. SE is in low level. (When SE is high, SI/O becomes high impedance.) 

*3. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 



Read Transfer Cycle (2) 



1 



Address ' /Jfl Row 



W 'J I 



(Output) ' 



n 



\mMi TTTTum m 



^- (////////ii/i/n/iiiiniiiiii, 



(Input) 



SI/O 
(Output) 



i //////////um ^r-.m 



X 



[222 '■ DO"' 1 care 

W^A '■ Inhibit rising transient 



Notes: *J, When the previous data transfer cycle is a write or pseudo transfer cycle, it is defined as read transfer cycle (2). 
*2. SE is in low level. (When SE is high, SI/O becomes high impedance.) 

*3. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 



HITACHI 

536 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534252 Series 



Pseudo Transfer Cycle 



RAS 
CAS 

Address 
WE 



X 



Us. 



dt/ot 7^ 



SE 



sc 

Sl/O 
(Input) 

Sl/O 
(Output) 



7r T 

t.sc - 



SAM Start 
Address 



;#zzzz 



tc 




z^ vhiiiiiiiiiu 



777} ■ Don't care 
gg<3 : Inhibit rising tr, 
I/O : Don't care 



Valid 
Sin 



:^zzzzk 



Note: *1. CAS and SAM sun address don't need to be specified every cycle, if SAM start address is not changed. 

Write Transfer Cycle 



ra5 

CAS 



Address 



DT/OT 



7- 



toy , i'.*¥ CH 

)0C 



SAM Stan 
Address 



^ninuiuuniiiniiiniimum 




-J 



; *v/ ///////////////////// 



7^ : Don"t care 

£3 : Inhibit rising transient 



3k A 



Sl/O / V»M0 
(Input) V S| n 



Sl/O 
(Output) 



^v2ZZZZZZZZZZ2)£^CZZZZr< 

Hijh-Z 



Note: *T. TOSandSAM start address don't need to be specified every cycle, if SAM sun address is not changed. 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534252 Series 
Serial Read Cycle 







RAS 



™r ZZZZZZZZZZZZZZZZZZZZZZyf Vllllllllll 



J 



sc 



/ (n-1) V / (n 



Valid 
Sout 



J? 



(n + l)\ 




Valid 
Sout 



< KJJJli 
17 '»» .p" 



(n+i) 

P^ZI : Don't care 



Valid 

+2) 



Serial Write Cycle 



RAS 

DT/OT 
SE 
SC 

Sl/O 
(Input) 



t 


□ rs 


Iras 

t DTK 


1 


l 


mimiimiiniiiiit 


- 


\ i h 



. t tswiS , tjwIH ^ 

7 ? a o-i r- — - 




m L scc 


' fn-1) V (n) 


— i-sws — •- 
[ t sc p 


(n + l 


:\ r 


sS-i) %///)., 

tsiS* — 


'tt«-n.W/ /////// 

' tsiH taia tsiH 





KxZI : Don't care. 



Notes: *1. When SE is high level in a serial write cycle, data is not written into SAM, however, the pointer is incremented. 
*2. Address is accessed next to address 511. 



HITACHI 



i. • t 



Logic Operation Set/Reset Cycle 



■Raj 



Cas 



Address 



t«P 



\ 



X 



ufz 



^ FCHR 



22 



I/O 
(Input) 

I/O 
(Output) 



pzzzzzzzzzzzzzzzz 



//////////////////////// 



High-Z 



™* iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiim 

T77\ ■ Don't care. 



Notes: *1. Logic code A0-A3 
*2. Write mask data 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 39 



HM534252 Series 



Logic Operation Mode Timing Waveforms 
Early Write Cycle 



R5S 




Row 



t 



to 



— tc, 



r 



illinium, 



Onput) Z flSf 



77777777 



I/O 
(Output) 



m~i/r viiiiiiiiiiiiiiiiiiiiiiin 

■ Don't care. 



Valid Din 




High-Z 



Note: *T. When WE is high, all the data on I/Os can be written into the mem ory cell. When WE is low, the data on I/Os are not 
except for the case that the I/O is high at the falling edge of RAS. 

Delayed Write Cycle 



written 



RS5 



CSS 



WE 



DT/OT , 



I/O 
(Input) 





m 1 bcd • 


?*MM * 






Us, 




tAIC 


tcFS 




,1 








Ifcsm 




'/): 


Row |) 


Column 


mil / 


twi 




tc. 








'/)■ 


•1 






1 








- t BW i 4— - 

1 tcWL- 






tan 




V//////////////// 


t«f) 








(X ^lidDataln 


VII 


II 


//// 



i/o . 

(Output) 



High-Z 



X//X '■ Don't care. 



Note: *1. When WE is high, all the data on I/Os can be written into the mem ory cell. When WE is low, the data on I/Os are not written 
except for the case that the I/O is high at the falling edge of RAS. 

<§> HITACHI 

540 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534252 Series 

Page Mode Write Cycle (Delayed Write) 



"CSS" 



Address 



I/O 
(Input) 



I/O 
(Output) 



T5T/OE ■ 



' ■ 

\ 


tfCSN 


t.. 

. trpc— 


5 




-r- — s . 


t.„ ■ 


'BCD 

Jri 


ICF3 




1 Use 

CAN 


t C FS 


r 




row 


^Column 


!///// 






umn 


iiiiiim 








Si 


- 


% ■■ 




'x Jf////;> 


W/, 


if 


-mi nil 


t.s 


ty H .to 




'dh t o 


J ^ H 








aiidV 
Din J\ 


miiii/i 






High-Z 




tor, 










\tmrm, 



Y7A ■ Don't care. 



Note: t. When WE is high, all the data on I/Os can be written into the memory cell. When WE is low, the data on I/Os are not written 
except for the case that the IAD is high at the falling edge of RAS. 

Page Mode Write Cycle (Early Write) 



Address 



3>! 




r 







^fZZZZJHZZZHZZZZZL 

t w H L«J u ' WCK . Lwj t WCH , . 



tDH f OS I I t dh "t)S 



1 \ KjihIosJ L*PH, Us I |tp H Jds t 0H 

rn rnrlr^i nn *n r 



I/O 
(Output) 



zzzzz 



High-Z 



DT/OE 



Y/A '■ Don't care. 



Note: 1. When WE is high, all the data on I/Os can be written into th e mem ory cell. When WE is low, the data on I/Os are not written 
except for the case that the I/O is high at the falling edge of RAS. 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 541 



HM534253 Series — Preliminary 



262144-Word x 4-Bit Multiport CMOS Video RAM 

The HM534253 is a 1 -Mbit multiport video RAM equipped with a 
256-kword x 4-bit dynamic RAM and a 512-word x 4-bit SAM (serial 
access memory). Its RAM and SAM operate independently and 
asynchronously. It can transfer data between RAM and SAM and 
has a write maskfunction. In addition, it has two newfunctions. Flash 
write clears the data of one row in one cycle in RAM. Special read 
transfer internally detects that the last address in SAM is read and 
transfers the next data of one row automatically from RAM if a 
transfer cycle has previously been executed. These functions make 
it easier to use the HM534253. 

Features 

• Multiport organization 

Asynchronous and simultaneous operation of RAM and SAM 
capability 

RAM: 256-kword x 4-bit and SAM: 512-word x 4-bit 

• Access time RAM: 1 00 ns/1 20 ns/1 50 ns max 

SAM: 30 ns/ 40 ns/ 50 ns max 

• Cycle time RAM: 1 90 ns/220 ns/260 ns min 

SAM: 30 ns/ 40 ns/ 60 ns min 

• Low power 

Active RAM: 385 mW max 
SAM: 275 mW max 
Standby 40 mW max 

• High-speed page mode capability 

• Mask write mode capability 

• Bidirectional data transfer cycle between RAM and SAM capability 

• Special read transfer cycle capability 

• Flash write cycle capability 

• 3 variations of refresh (8 ms/51 2 cycles) 

RAS-only refresh 
CAS-before-RAS refresh 
Hidden refresh 

• TTL compatible 

Ordering Information 



Pin Arrangement 



Type No. 


Access Time 


Package 


HM534253JP-10 


100 ns 


400-mil 


HM534253JP-12 


120 ns 


28-pin 


HM534253JP-15 


150 ns 


Plastic SOJ (CP-28D) 


HM534253ZP-10 


100 ns 


400-mil 


HM534253ZP-12 


120 ns 


28-pin 


HM534253ZP-15 


150 ns 


Plastic ZIP (ZP-28) 



This document contains information on anew product. Specifications and information 
contained herein are subject to change without notice. 







HM534253JP Series 



sc 

SI/OO 
SI/01 
DT/OE 
I/00 
1 /01 
WE 



NC< 8 
RAS" 9 
A8> 10 
A6"jl1 
A5 
A4 



"28>V, 
27 



12 
13 
414 



> SI/03 

■ SI/02 

■ 5E 
'1/03 
'1/02 
' DSF 
>CAS 
"QSF 
'AO 
'A1 
>A2 
.A3 

■ A7 



(Top View) 



HM534253ZP Series 



1/02 2 
ST 4 
SI/03 6 
SC 8 
SI/01 10 
1/00 12 
■WE 14 
RAS" 16 
A6 18 
A4 20 
A7 22 
A2 24 
AO 26 
CAS 28 



1 DSF 

31/03 

5 SI/02 

7V„ 

9 Sl/O0_ 
11 BT/Sl 
13 1/01 
15 NC 
17 A8 
19 A5 
21 V ce 
23 A3 
25 Al 
27 QSF 



(Bottom View) 



Pin Description 


Pin Name 


Function 


A0-A8 


Address inputs 


I/O0-I/O3 


RAM port data inputs/ 




outputs 


SI/OO- 


SAM port data inputs/ 


SI/03 


outputs 


RAS 


Row address strobe 


CAS 


Column address strobe 


WE 


Write enable 


DT/OE 


Data transfer/Output 




enable 


SC 


Serial clock 


SE 


SAM port enable 


DSF 


Special function input 




flag 


QSF 


Data register empty 




flag 


Vcc 


Power supply 


Vss 


Ground 


NC 


No connection 



542 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534253 Series 



Block Diagram 



RAM 



SAM 



DT/OE 



I/O 



WE 



Mask 
Register 



hi ' 



Dout 






Din 


Memory 






Array 


| 






O 

O 




Row 





I — ij Color 
1 ^ Register 



DR : Data Register 



511 



Pointer 



I Selector 



From 

Column Address 
(SAM Start 
Address) 



TP no 



Pin Function _ 

RAS (input pin): RAS is a basic RAM signal. It is active 
in low level and standby in high level. Row address and 
signals as shown in table 1 are input at the falling edge 



of RAS. The input level of those signals determine the 
operation cycle of the HM534253. 



Table 1. Operation Cycles of the HM534253 





Input level at the falling edg 


e of RAS 




Operation Cycle 


CAS 


DT/OE 


WE 


SE 


DSF 


H 


H 


H 


X 


L 


RAM read/write 


H 


H 


H 


X 


H 


Color register set 


H 


H 


L 


X 


L 


Mask write 


H 


H 


L 


X 


H 


Flash write 


H 


L 


H 


X 


L 


Special read initialization 


H 


L 


H 


X 


H 


Special read transfer 


H 


L 


L 


H 


X 


Pseudo transfer 


H 


L 


L 


L 


X 


Write transfer 


L 


X 


X 


X 


X 


CBR Refresh 


Note: x: 


Don't care. 











CAS (input pin): Column address is put into chip at the 
falling edge of CAS. CAS controls output impedance of 
I/O in RAM. 

A0-A8 (input pins): Row address is determined by A0- 
A8 level at the falling edge of RAS. Column address is 
determined by A0-A8 level at the falling edge of CAS. 
In transfer cycles, row address is the address on the 



word line which transfers data with SAM data register, 
and column address is the SAM start address after 
transfer. 

WE (input pin): WE pin has tw o fun ctions at the falling 
edge of RAS and after. When WE is low at the falling 
edge of RAS, the HM534253 turns to mask write mode. 
According to the I/O level at the time, write on each I/O 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



543 



HM534253 Series 



can be masked. (WE level at the falling edge of RAS 
Is don't care in read cycle.) When WE is high at the 
falling edge of RAS, a normal write cycle is executed. 
After that, WE switches read/write cycles as in a 
standard DRAM. In a transfer cycle, the direction of 
transfer is determined by WE level at the falling edge 
of RAS. When WE is low, data is transferred from SAM 
to RAM (data is written into RAM), and when WE is 
high, data is transferred from RAM to SAM (data is 
read from RAM). 

I/O0-I/O3 (input/output pins): I/O pins function as 
mask data at the falling edge of RAS (in mask write and 
flash write mode). Data is written only on high I/O pins. 
Data on low I/O pins are masked and internal data are 
retained. After that, they function as input/output pins 
as those of a standard DRAM. 

DT/OE (input pin): DT/OE pin functions as DT (data 
transfer) pin at the falling edge of RAS and as OE 
(output enable) pin after that. When DT is low at the 
falling edge of RAS, this cycle becomes a transfer 
cycle. When DT is high at the falling edge of RAS, RAM 
and SAM operate independently. 

SC (input pin): SC is a basic SAM clock. In a serial read 
cycle, data is output from an Sl/O pin synchronously 
with the rising edge of SC. In a serial write cycle, data 
on an Sl/O pin at the rising edge of SC is put into the 
SAM data register. 

SE (input pin): SE pin activates SAM. When SE is high, 
Sl/O is in the high impedance state in serial read cycle 
and data on Sl/O is not put into the SAM data register 
in serial write cycle. SE can be used as a mask for 
serial write because internal pointer is incremented at 
the rising edge of SC. 

SI/O0-SI/O3 (input/output pins): Sl/Os are input/output 
pins in SAM. Direction of input/output is determined by 
the previous transfer cycle. When it was a special read 
transfer cycle or special read initialization cycle, Sl/O 
outputs data. When it was a pseudo transfer cycle or 
write transfer cycle, Sl/O inputs data. 

DSF (input pin): DSF is a special data input flag pin. It 
is setto high when newfunctions such as color register 
set, special read transfer, and flash write, are used. 

QSF (output pin): The HM534253 has a double buffer 
organization which includes two SAM data registers to 
relax the restriction on timings of DT/OE~and SC in real 



time transfer cycle. QSF flag turns high when output 
from one of SAM data registers finished (data register 
empty flag). If the condition is detected and special 
read transfer cycle is executed, data is transferred to 
the empty register. SC (serial clock) and data transfer 
cycle can be set asynchronously because detection of 
the last address in SAM and change of data register 
are executed automatically in the chip. It makes the 
system design flexible. 

Operation of HM534253 

Operation of RAM Port 

RAM Read Cycle (DT/OE high, CAS high, DSF low at 
the falling edge of RAS) 

Row address is entered at the RAS falling edge and 
column address at the CAS falling edge to the device 
as in standard DRAM. Then, when WE is high and DT/ 
OE is low while CAS is low, the selected addres s data 
is output through I/O pin. At the falling edge of RAS, 
DT/OE and CAS become high to distinguish RAM read 
cycle from transfer cycle and CBR refresh cycle. 
Address access time (tAA) and RAS to column address 
delay time (tHAD) specifications are added to enable 
high-speed page mode. 

RAM Write Cycle 

(Early Write, Delayed Write, Read Modify Write) 

(DT/OE high, CAS high, DSF low at the falling edge of 
RAS) 

• Normal Mode Write Cycle (WE high at the falling 
edge of RAS) 

When CAS and WE are set low after driving RAS 
low, a write cycle is executed and I/O data is written in 
the selected addresses. When all 4 l/Os are written, 
WE should be high at the falling edge of RAS to 
distinguish normal mode from mask write mode. 

If WE is set low before the CAS falling edge, this 
cycle becomes an early write cycle and I/O becomes 
high impedance. Data is entered at the CAS falling 
edge. 



If WE is set low after the CAS falling edge, this cycle 
becomes a delayed write cycle. Data is input at the WE 
falling. I/O does not become high impedance in this 
cycle, so data should be entered with OE in high. 



HITACHI 

544 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



If WE is set low after tcwD (min) and Uwd (min) after 
the CAS falling edge, this cycle becomes a read modify 
write cycle and enables read/write to execute in the 
same address cycle. In this cycle also, to avoid I/O 
contention, data should be input after reading data and 
driving OE high. 

• Mask Write Mode (WE low at the falling edge of 
RAS) 

If WE is set low at the falling edge of RAS, the cycle 
becomes a mask write mode cycle which writes only to 
selected IAD. Whether or not an I/O is written depends 
on I/O level (mask data) at the falling edge of RAS. 
Then the data is written in high I/O pins and masked in 
low ones and internal data is pre served. This mask 
data is effective during the RAS cycle. So, in high- 
speed page mode cycle, the mask data is preserved 
during the page access. 

High-Speed Page Mode Cycle ( DT/OE high, CAS 
high, DSF low at the falling edge of RAS) 

High-speed page mode cycle reads/writes the data 
of the same row address at high speed by toggling 
CAS while RAS is low. Its cycle time is one third of the 
random read/write cycle and is higherthan the standard 
page mode cycle by 70-80 %. This product is based on 
static column mode, therefore, address access time 
(tAA), RAS to col umn a ddress delay time (tRAo), and 
access time from CAS precharge (Ucp) are added. In 
one RAS cycle, 512-word memory cells of the same 
row address can be accessed. It is necessary to 
specify access frequency within tRAs max (10 us). 



Flash Write Function (See figure 1) 

• Color Register Set Cycle (CAS-DT/OE WE high, 
DSF high at the falling edge of RAS) 

In color register set cycle, color data is set to the 
internal color register used in flash write cycle. 4 bits of 
internal color register are provided at each I/O. This 
register is composed of static circuits, so once it is set, 
it preserves the data until reset. The data set is just as 
same as in the usual write cycle except that DSF is set 
high at the falling edge of RAS, and early write and 
delayed write cycle can be executed. In this cycle, 
memory array access is not executed, so it is 
unnecessary to give row and column addresses. 

• Flash Write Cycle (CAS-DTVOE high, WE low, DSF 
high at the falling edge of RAS) 

In a flash write cycle, a row of data (512 x 4 bit) is 
cleared to or 1 at each I/O according to the data of 
color register mentioned before. It is also possible to 
mask I/O in this cycle. When CAS DT/OE is set high, 
WE is low, and DSF is high at the falling edge of RAS, 
this cycle starts. Then, the row address to clear is given 
to row address and mask data is to I/O. Mask data is as 
same as that of a RAM write cycle. High I/O is cleared, 
low I/O is not cleared and the internal data is preserved. 
Cycle time is the same as those of RAM read/write 
cycles, so all bits can be cleared in 1/512 of the usual 
cycle time. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 45 



HM534253 Series 



Color Register Set Cyde 



Flash Write Cyde 



Flash Write Cyde 



CAS 



\ 



Address i 



w 



f 



\ L 



A / 



mil mm 

TEEUUm 



'u mm 



v//////////. 



7 
V 



mm 



DT/OT 



l/OO 



1/01 



1/02 



1/03 



7 



\ f 



I 



77J A - fi 



"1 "Write \^ 



m m , m\ - fir/ // w, 



mi ....... v// a - m 



T 



u ■ wz 



27" 



V/////////// 7 



AZZ2Z 



DSF 





Execute flash write 
into l/OO. I/OI. 1/03 
on row address Xi 
using color register. 
(1/02 is masked.) 



Set (1/03, 1/02, l/OI, 
l/OO) = (1,0,0, 1)into 
color register. 



Execute flash write 
into 1/02, 1/03 on row 
address Xi using color 
register. (l/OO, 1/01 
are masked.) 



Figure 1. Use of Flash Write 



HITACHI 

546 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534253 Series 



Transfer Operation 

The HM534253 provides the special read 
initialization cycle, special read transfer cycle, pseudo- 
transfer cycle, and write transfer cycle as data transfer 
cycles. These transfer cycles are set by driving DT/OE 
low at the falling edge of RAS. They have following 
functions: 

(1 ) Transfer data between row address and SAM data 
register (except for pseudo transfer cycle) 

(2) Determine direction of data transfer 

(a) Special read initialization cycle, 
Special read transfer cycle: RAM -> SAM 

(b) Write transfer cycle: RAM <- SAM 

(3) Determine input or output of SAM I/O pin (Sl/O) 
Special read initialization cycle: Sl/O output 
Pseudo transfer cycle, write transfer cycle: 

Sl/O input 

(4) Determine first SAM address to access (SAM start 
address) aftertransferring at column address. When 
SAM start address is not changed, neither CAS nor 
address need to be set because SAM start address 
can be latched internally. 

Special Read Initialization Cycle (CAS high,DT/OE 
low, WE high, DSF low at the falling edge of RAS) 

If CAS is high, DT/OE is low, WE high, and DSF low 
at the falling edge of RAS, this cycle becomes a special 
read initialization cycle. Special read initialization is 
used (1 ) to start special read transfer operation and (2) 
to switch SAM input/output pin (Sl/O), set in input state 
by pseudo transfer cycle or write transfer cycle, to 
output state. 





If the clock is set as mentioned before, address of 
SAM transfer word line is set to row address and first 
SAM address to access (SAM start address) to column 
address, it becomes possible to execute SAM read 
after tsuo (min) after RAS is high. In this cycle, Sl/O 
outputs uncertain data after the RAS falling edge. So 
when SAM is in input state before executing this cycle, 
it is necessary to stop input before the RAS falling 
edge. 



SAM access is inhibited while RAS is low in this 
cycle. SC should not be raised during RAS low. 

Special Read Transfer Cycle (CAS high, DT/OE I 
WE high, DSF high at the falling < 



Ordinary multiport video RAM has some problems; 
(1) severe limitation on timings between processor 
clock DT/OE and CRT clock SC, (2) complicated 
external control circuit to detect SAM last address 
externally and to insert transfer cycle synchronously. 
Special read transfer cycle makes it possible to relax 
the timing limitations and to set serial clock (SC) and 
transfer cycle perfectly synchronously. 



Figure 2 shows the block diagram for a special re 
transfer. SAM double buffers are composed of two 
data registers (DR). When data is read out from DRO 
serially, special read transfer cycle transfers a row of 
RAM data, which will be read from SAM next, to DR1 . 

The end of data read from DRO is detected internally 
and data register switching circuit automatically 
switches to DR1 output. So data can be output 
continuously. 



RAM 



|dt/oe| 



SAM 



Memory 
Array 



x//y//, 



DR 



1 



Selector 
Sout(DRO) 







Detect SAM 
Last Address 



igure 2. Block Diagram for Special Read Transfer 



^HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, C 



) 589-8300 



547 



HM534253 Series 



Figure 3 shows special read transfer operation 
sequence. QSF flag indicates that reading out from 
data resister has finished (data register empty flag), 
and special read transfer can be executed while QSF 
is high. At first, special read operation starts by executing 
an special read initialization cycle. So QSF becomes 
high, the processor gives row address and SAM start 
address, which is needed next, to the memory, and 
inserts a special read transfer cycle. Data register 
becomes full after a special read transfer cycle, so 



QSF becomes low during the cycle. When the last 
SAM address is accessed, QSF becomes high and the 
data register, which outputsf rom the next SAM address, 
changes, and serial access can be executed. 

By executing these handshakes, serial clock and 
transfer cycle can be executed perfectly asyn- 
chronously, and flexibility of the system design is 
improved. 



— 



Cycle 



— DRO 

Special read 
IniSaliiaoon 
cycle 



y RAM Ready! 

&1A 



Special read 
transfer cycle 




Column address 

tl 

7T- 



V RAM Read V ! 
,A /Write Ai 

/ 



transfer cycle i 



1 



RAM Read 
/Write 



r 



Column address 

I \ 



1 



SC 



SI/0 
(Output) 



Y=51 1 Y=i i+t i+2 Y=511 Y=j j+1 

M -AAAAA- MM 



I 



Output from DRO 



Output from DR1 







Figure 3. Special Read Transfer Operation Sequence 



Special read transfer cycle is set by making CAS high, 
TJT/OE low, WE high, and DSF high at the falling edge 
of RAS (same as for special read initialization cycle 
except DSF). Like in other transfer cycles, the address 
of the word line to transfer into data register is specified 
by row address and SAM start is specified by column 
address. When the last SAM address data is output, 
the next data is output from the SAM start address 
specified by this RAS cycle. This transfer cycle can be 
executed asynchronously with SAM cycle. However, it 
is necessary to execute SAM access after RAS 
becomes high after SAM start address is specified by 
RAS cycle. (See figure 4.) 

QSF should be high at the falling edge of RAS to 
execute a special read transfer cycle. A cycle whose 
QSF is low is neglected (refresh is executed). When 
the previous transfer cycle is a pseudo transfer or write 



transfer cycle and Sl/O is in input state, special read 
transfer cycle cannot be used (neglected). Special 
read initialization cycle is required to switch Sl/O to 
output state. 

Pseudo Transfer Cycle (CAS high,T5T/OE~low, WE 
low, and SE high at the falling edge of RAS) 

Pseudo transfer cycle is available for switching Sl/O 
from output state to input state because data in RAM 
isn't rewritten. This cycle starts when CAS is high,~DT/ 
OE low, WE low, and SET high, at the falling edge of 
RAS. The output buffer in Sl/O becomes high impedance 
within tsRZ (max) from the RAS falling edge. Data 
should be input to Sl/O later than tsro (min) to avoid data 
contention. SAM access becomes enabled after tSRD 
(min) after RAS becomes high, like in the special read 



548 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



RS5~ 



CSS 
Address 

T5T/0E 



DSF 



SC 



QSF 



(Special read 
transfer cycle) 



7 



/ 



1 
f 



(510) 








(Yk) 



a r 



(Yk + 1) 



'sao t [Row address Xj data 



Figure 4. The Restriction of Special Read Transfer 



initialization cycle. In this cycle, SAM access is inhibited 
during RAS low, therefore, SC should not be raised. 

WriteTransfer Cycle (CAS high, DTTOE low, WE low, 
and SE low at the falling edge of RAS) 

Write transfer cycle can transfer a row of data input 
by serial write cycle to RAM. The row address of data 
transferred into RAM is determined by the address at 
thefalling edge of RAS. The column address is specified 
as the first address to serial write after terminating this 
cycle. Also in this cycle, SAM access becomes enabled 
after tsRD (min) after RAS becomes high. SAM access 
is inhibited during RAS low. In this period, SC should 
not be raised. 

SAM Port Operation 

Serial Read Cycle 

SAM port is in read mode when the previous data 
transfer cycle is special read initialization cycle or 



special read transfer cycle. Access is synchronized 
with SC rising, and SAM data is output from Sl/O.When 
the last address is accessed at the state of QSF low 
(data register is full), it is signaled to external circuits 
that special read transfer is enabled by making QSF 
high. Next, after SAM access, output data register is 
switched, then the row address data given by previous 
special read transfer cycle is output from the SAM start 
address. If special read transfer isnt performed (QSF 
high), the column address of the same row address 
is accessed after the last address is accessed. 

Serial Write Cycle 

If previous data transfer cycle is pseudo transfer 
cycle or write transfer cycle, SAM port goes into write 
mode. In this cycle, Sl/Odata is programmed into data 
register at the SC rising edge like in the serial read 
cycle. If SE is high, Sl/O data isn't input into data 
register. Internal pointer is incremented according to 
the SC rising edge, so "SE high can be used to mask 
data for SAM. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



HM534253 Series 



Refresh 

RAM Refresh 

RAM, which is composed of dynamic circuits, 
requires refresh to retain data. Refresh is performed 
by accessing all 51 2 row addresses every 8 ms. There 
are three refresh cycles: (1) RAS-only refresh cycle, 
(2) CAS-before-RAS (CBR) refresh cycle, and (3) 
Hidden refresh cycle. Besides them, the cycles which 
activate RAS such as read/write cycles or transfer 
cycles can refresh the row address. Therefore, no 
refresh cycle is required for accessing all row addresses 
every 8 ms. 

RAS-Only Refresh Cycle: RAS-only refresh cycle is 
performed by activating only RAS cycle with CAS fixed 
to high by inputting the row address (= refresh address) 
from external circuits. In this cycle, output is high- 
impedance and power dissipation is less than that of 
normal read/write cycles because CAS internal circuits 



don't operate. To distinguish this cycle from data 
tr ansfe r cycle, DT/OE should be high at the falling edge 
of RAS. 

CBR Refresh Cycle: CBR refresh cycle is set by 
activating CAS before RAS. In this cycle, refresh 
address need not to be input through external circuits 
because it is input through an internal refresh counter. 
In this cycle, output is in high impedance and power 
dissipation is lowered like in RAS-only refresh cycles 
because CAS circuits don't operate. 

Hidden Refresh Cycle: Hidden refresh cycle performs 
refresh by reactivating RAS when DT/OE and CAS 
keep low in normal RAM read cycles. 



SAM Refresh 

SAM parts (data register, shift register, selector), 
organized as fully static circuitry, don't require refresh. 



Absolute Maximum Ratings 



Item 




Symbol 


Rating 




Unit 


Terminal voltage *' 




Vt 


-1.0 to +7.0 




V 


Power supply voltage *' 




Vcc 


-0.5 to +7.0 




V 


Power dissipation 




Pr 


1.0 




w 


Operating temperature 




Topr 


to +70 




°c 


Storage temperature 




Tstg 


-55 to +125 




°C 


Note: *1. Relative to Vss. 












Recommended DC Operating Conditions (Ta = 


to +70°C) 






Item 


Symbol 


Min 


Typ 


Max 


Unit 


Supply voltage* 1 


Vcc 


4.5 


5.0 


5.5 


V 


Input high voltage " 1 


VlH 


2.4 




6.5 


V 


Input low voltage *' 


Vn. 


-0.5' 2 




0.8 


V 



Notes: 



*1. All voltages referenced to Vss. 
*2. -3.0 V for pulse width S 10 ns. 



HITACHI 

550 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534253 Series 



DC Characteristics (Ta = to +70°C, Vcc = 5 V ± 10%, Vss = V) 



Item Symbol 


HM534253 
-10 


HM534253 


HM534253 


Unit 


Test Conditions 








1J 




SAM port 






Min 


Max 


Min Max 


Min 


Max 




RAM port 


Operating 
current 


Icci 




70 




60 




50 


mA 


RAS.CAS 
cycling 


SC = Vil.SE = Vih 




ICC7 


— 


120 




100 


— 


80 


mA 


tRC= Min 


SE =Vil, SC cycling 
tscc=Min 


Standby current Ira 





7 




7 


— 


7 


mA 


RAS.CAS 
= Vm 


SC = Vil, SE = Vw 




IcCJ 





50 




40 


— 


30 


mA 




SE = Vil, SC cycling 
tscc = Min 


RAS-only 
refresh current 


ICO 


— 


60 




50 


— 


40 


mA 


RAS cycling 
CAS= Vm 


SC = ViL,SE = Vm 




ICC9 





110 




90 


— 


70 


mA 


mc = Min 


"SE = Vil, SC cycling 


Page mode 
current 


ICC4 





65 




55 


— 


45 


mA 


CAS cycling 
RAS = Vil 


SC,SE = Vm 




Iccio 


— 


115 




95 


— 


75 


mA 


Die = Min 


"SE = Vil, SC cycling 
tscc = Min 


CAS-before- 
RAS refresh 


Ices 


— 


60 




50 


— 


40 


mA 


RAS cycling 
tRC — Min 


SC = Vil,SE = Vih 


current 


Icai 


— 


110 




90 


— 


70 


mA 




SE = Vil, SC cycling 
tscc — Min 


Data 
transfer 


ICC6 


— 


90 




90 


— 


90 


mA 


RAS.CAS 
cycling 


SC = Vil,SE"=Vih 


current 


ICC12 


— 


125 




125 


— 


125 


mA 


Irc = Min 


SE = Vo, SC cycling 
tscc = Min 


Input leakage 
current 


Ili 


-10 


10 


-10 


10 


-10 


10 


HA 






Output leakage 
current 


Ilo 


-10 


10 


-10 


10 


-10 


10 


H.A 






Output high 
voltage 


VOH 


2.4 




2.4 




2.4 




V 


Ioh = -2 mA 


Output low 
voltage 


Vol 




0.4 




0.4 




0.4 


V 


Iol = 4.2 mA 


Capacitance (Ta = 25°C, Vcc= 5 V, f =1 MHz, Bias: Clock, I/O 


= Vcc, address = Vss) 


Item 




Symbol 




Min 






Typ 




Max 


Unit 


Address 




Cii 














5 


PF 


Clock 




Cl2 














5 


PF 


vo.sm 




Ci/o 














7 


pF 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



AC Characteristics ( Ta = to +70°C, Vcc = 5 V + 10%, Vss = V ) *V« 



Test Conditions 

Input rise and fall time: 5 ns 

Output load: See figures 

Input timing reference levels: 0.8 V, 2.4 V 

Output timing reference levels: 0.4 V, 2.4 V 



Output Load (A) 



I h= — 2mA 



I/O 



I 



-Kl- 



lOOpF" 



'Ttl 



+ 5V 



SI/0 



Output Load (B) 

+ 5V 

l »=-2mA 



l OL =4.2mA 



T 

I 



HO- 



Note: *1. Including scope & jig. 



Common Parameter 



Item 


Symbol 


HM534253-10 


HM534253-12 


HM534253-15 


Unit Note 






Min 


Max 


Min 


Max 


Min 


Max 




Random read or write cycle time 


tRC 


190 




220 




260 




ns 


RAS precharge time 


tRP 


80 




90 




100 




ns 


RAS pulse width 


tRAS 


100 


10000 


120 


10000 


150 


10000 


ns 


CAS pulse width 


tCAS 


30 


10000 


35 


10000 


40 


10000 


ns 


Row address setup time 


tASR 

















ns 


Row address hold time 


tRAH 


15 




15 




20 




ns 


Column address setup time 


use 

















ns 


Column address hold time 


tCAH 


20 




20 




25 




ns 


RAS to CAS delay time 


tRCD 


25 


70 


25 


85 


30 


110 


ns ' 5 '' 6 


RAS hold time 


tRSH 


30 




35 




40 




ns 


CAS hold time 


tCSH 


100 




120 




150 




ns 


CAS to RAS precharge time 


tCRP 


10 




10 




10 




ns 


Transition time (rise to fall) 


tr 


3 


50 


3 


50 


3 


50 


ns 


Refresh period 


tREF 




8 




8 




8 




DT to RAS setup time 


tDTS 

















ns 


DT to RAS hold time 


tDTH 


15 




15 - 




20~ 






DSF to RAS setup time 


tSPS 

















ns 


DSF to RAS hold time 


tSFH 


25 




25 




30 




ns 


Data-in to OE delay time 


tDZO 

















ns 


Data-in to CAS delay time 


tDZC 

















ns 



HITACHI 

552 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300 



Read Cycle (RAM), Page Mode Read Cycle 



Item 


Symbol 


HM534253-10 


HM534253-12 


HM534253-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Access time from RAS 


OtAC 




inn 




ion 




iju 


ns 


•2. -3 


Affpct fimp ntntfVi PA\ 






j\) 




1^ 

J J 




4U 




*3.'5 


rtCCtbS LLIIIC 11 UII1 UC 














An 
4U 


ns 


•3 


Address access time 


tAA 




45 




55 




70 


ns 


•3. -6 


Output buffer turn-off delay 
reierencea to las 


tOFFl 





25 





m 
30 


n 



An 
40 


ns 


* 


Output buffer turn-off delay 

icicicnccu lO UD 


torn 




Id 


n 
U 


in 


n 
U 


40 


ns 


•7 


Read command setup time 


tRCS 

















ns 




Read command hold tune 


tRCH 















— 


ns " 12 


Read command hold time 
referenced to RAS 


tRRH 


10 




10 




10 




ns 


•12 


RAS to column address 
delay time 


tRAD 


20 


55 


20 


65 


25 


80 


ns 


•5, -6 


Page mode cycle time 


IPC 


55 




65 




80 




ns 




CAS precharge time 


tcp 


10 




15 




20 




ns 




Access time from CAS precharge 


UCP 




50 




60 




75 


ns 




Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle 










Item 


Symbol 


HM534253-10 


HM534253-12 


HM534253-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Write command setup time 


twes 

















ns 


•9 


Write command hold time 


tWCH 


25 




25 




30 




ns 




Write command pulse width 


twp 


15 




20 




25 




ns 




Write command to RAS lead time 


tRWL 


30 




35 




40 




ns 




Write command to CAS lead time 


tCWL 


30 




35 




40 




ns 




Data-in setup time 


tDS 

















ns 


•10 


Data-in hold time 


tDH 


25 




25 




30 




ns 


•10 


WE to RAS setup time 


tws 

















ns 




WE to RAS hold time 


tWH 


15 




15 




20 




ns 




Mask data to RAS setup time 


tMS 

















ns 




Mask data to RAS hold time 


tMH 


15 




15 




20 




ns 




OE hold time referenced to WE 


tOEH 


10 




15 




20 




ns 




Page mode cycle time 


IPC 


55 




65 




80 




ns 




CAS precharge time 


tCP 


10 




15 




20 




ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 53 



HM534253 Series 



Read-Mod ify-Wrlte Cycle 



Item 


Symbol 


HM534253-10 


HM534253-12 


HM534253-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Re ad-modify -write cycle time 


tRWC 


255 




295 




350 




ns 




RAS pulse width 


tRWS 


165 


10000 


195 


10000 


240 


10000 


ns 




CAS to WE delay 


tCWD 


65 




75 




90 




ns 


•9 


Column address to WE delay 


tAWD 


80 


— 


95 


— 


120 


— 


ns 


•9 


OE to data-in delay time 


tODD 


25 




30 




40 




ns 




Access time from RAS 


tRAC 




100 




120 




150 


ns 


•2.-3 


Access time from CAS 


tCAC 




30 




35 




40 


ns 


•3,'S 


Access time from OE 


tOAC 




30 




35 




40 


ns 




Address access time 


tAA 




45 




55 




70 


ns 


•v« 


RAS to column address delay 


tR AD 


20 


55 


20 


65 


25 


80 


ns 


•5,'6 


Output buffer turn-off delay 
referenced to OE 


tOFF2 





25 





30 





40 


ns 




Read command setup time 


tRCS 







o 









ns 




Write command to RAS lead time 


tRWL 


30 




35 




40 




ns 




Write command to CAS lead time 




30 




35 




40 








Write command pulse width 


~~ i^r — 


15 




20 




25 




ns 




Data-in setup time 


tDS 










— 





— 


ns 


•10 


Data-in hold time 


tDH 


25 


— 


25 




30 




ns 


•10 


WE to RAS setup time 


tws 

















ns 




WE to RAS hold time 


tWH 


15 




15 




20 




ns 




Mask data to RAS setup time 


tMS 

















ns 




Mask data to RAS hold time 


tMH 


15 




15 




20 




ns 




OE hold time referenced to WE 


tOEH 


10 




15 




20 




ns 




Refresh Cycle 




















Item 


Symbol 


HM534253-10 


HM534253-12 


HM534253-15 


Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






CAS setup time 
(CAS-before-RAS refresh) 


tCSR 


10 




10 




10 




ns 




CAS hold time 
(CAS-before-RAS refresh) 


tCHR 


20 




25 




30 




ns 




RAS precharge to CAS hold time 


tRPC 


10 




10 




10 






ns 





HITACHI 

554 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534253 Series 



Transfer Cycle 



Item 


Symbol 


HM534253-10 


HM534253-12 


HM534253-15 Unit Note 






Min 


Max 


Min 


Max 


Min 


Max 




WE to RAS setup time 


tws 

















ns 


WE to RAS hold time 


tWH 


15 


— 


15 


— 


20 


— 


ns 


SE to RAS setup time 


tES 





— 





— 





— 


ns 


SE to RAS hold time 


t£H 


15 


— 


15 


— 


20 


— 


ns 


RAS to SC delay time 


tSRD 


25 




30 




35 




ns 


oL. to KAo setup time 


tSRS 


30 




40 




45 




ns 


RAS to QSF delay time 


tRQD 




100 




120 




150 


ns - 


RAS" to QSF (high) delay time 


tRQH 




TBD 




TBD 




TBD 


ns 


Serial data input delay time 
fromRXS 


tSID 


50 




60 




75 




ns 


Serial data input to RAS 


tSZR 




10 




10 




10 


ns 


delay time 



















Serial output buffer turn-off tsRZ 10 50 10 60 10 75 ns 

delay from RAS 



RAS to Sout (Low-Z) delay time teLZ 5 — 10 — 10 — ns 

Serial clock cycle time tscc 30 — 40 — 60 — ns 

Access time from SC tsCA — 30 — 40 — 50 ns 

Serial data out hold time tsoH 7 — 7 — 7 — ns 



SC pulse width tsc 10 — 10 — 10 — ns 



SC precharge width 


tSCP 


10 




10 




10 




ns 




Serial data-in setup time 


tSIS 

















ns 




Serial data-in hold time 


tSIH 


15 




20 




25 




ns 




Serial Read Cycle 


Item 


Symbol 


HM534253-10 


HM534253-12 


HM534253-15 Unit 


Note 






Min 


Max 


Min 


Max 


Min 


Max 






Serial clock cycle time 


tscc 


30 




40 




60 




ns 




Access time from SC 


tSCA 




30 




40 




50 


ns 


•4 


Access time from SE 


tSEA 




25 




30 




40 


ns 


•4 


Serial data-out hold time 


tSOH 


7 




7 




7 




ns 


«4 


SC pulse width 








10 




10 




ns 




SC precharge width 


tSCP 


10 




10 




10 




ns 




Serial output buffer turn-off 
delay from SE 


tSEZ 





25 





25 





30 


ns 


•7 


Last SC to QSF delay time 


tSQD 




TBD 




TBD 




TBD 


ns 


"4 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



555 



HM534253 Series 



Serial Write Cycle 



Item 


Symbol 


HM534253-10 


HM534253-12 


HM534253-15 


Unit Note 






Min 


Max 


Min 


Max 


Min 


Max 




Serial clock cycle time 


tscc 


30 




40 




fin 




ns 


SC pulse width 


tsc 


10 




10 




10 




ns 


SC precharge width 


tSCP 


10 




10 




10 




ns 


Serial data-in setup time 


tsis 

















ns 


Serial data-in hold time 


tsm 


15 




20 




25 




ns 


Serial write enable setup time 


tsws 

















ns 


Serial write enable hold time 


tSWH 


30 




35 




50 




ns 


Serial write disable setup time 


tswis 

















ns 


Serial write disable hold time 


tSWIH 


30 




35 




50 




ns 


Flash Write Cycle 


Item 


Symbol 


HM534253-10 


HM534253-12 


HM534253-15 


Unit Note 






Min 


Max 


Min 


Max 


Min 


Max 




Flash write cycle time 


tRCFW 


230 




265 




310 




ns 


RAS pulse width 


tRCSFW 


140 




165 




200 




ns 


WE to RAS setup time 


tws 

















ns 


WE to RAS hold time 


tWH 


15 




15 




20 




ns 


CAS high level hold time 
referenced to RAS 


tCHHR 


20 




25 




30 


— ns 


Mask data to RAS setup time 


tMS 


















ns 


Mask data to RAS hold time 


tMH 


15 


— 


15 




20 




ns 



Notes : * 1 . AC measurements assume tT = 5 ns. 

*2. Assume that tRCD < tRCD (max) and tRAD < irad (max). 

If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 
*3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 
*4. Measured with a load circuit equivalent to 2 TTL loads and 50 pF. 
*5. When tRCD > tRCD (max) and tRAD < irad (max), access time is specified by ICAC. 
*6. When tRCD < tRCD (max) and tRAD > tRAD (max), access time is specified by tAA. 

*7. tOFP (max) is defined as the time at which the output achieves the open circuit condition (VoH-200 mV, Vol+200 mV). 
*8. Vdi (min) and Vn, (max) are reference levels for measuring timing of input signals. Transition times are measured between 
VlH and VlL. 

*9. When twcs 2 twcs (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. 
When tAWD > tAWD (min) and tcWD > tcwD (min), the cycle is a read-modify-write cycle; the data of the selected address 
is read out from a data out pin and input data is written into the selected address. In this case, impedance on I/O pins is 
controlled by OE. 

*10. These parameters are referenced to CAS falling edge in early write cycles or to WE falling edge in de 
modify-write cycles. 

* 1 1 . After power-up, pause for 1 00 us or more and execute at least 8 initialization cycles (normal memory c 

then suit operation. 
*12. If either tRCH or tRRH is satisfied, operation is guaranteed. 




HITACHI 

556 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534253 Series 



Timing Waveforms 
Read Cycle 



"RA5 



CSS 



Address 



Row 



■A 



I/O 
(Output) 



1/0 WZMBfc 



(Input) 



■CT/OT Tffi 



< 



ICH j 



Valid 



to*C 



mm, mm 



DSF 



Don't care. 



Early Write Cycle 



RA5 



CAT 



s; 



' HAH I tjtSC 



Address ^< Row 



(Input) 

I/O 
(Output) 

"DT/OT 



J l.'"r 



' /////////////, 



5, "jf(^^^ ^//////////////f 



High-Z 



7%'- * «///////////////////////, 

^ ^//////////////////////m 



Y/A '■ Don't care. 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



557 



HM534253 Series — 
Delayed Write Cycle 



RA3~ 
CAS 

Address '/A R°« 



v 



DT/OE 



(Input) 

I/O _ 
(Output) 



W////////////////M 



C-tB*H m . *WCH ^ 




'WMMMMM 



High-Z 



DSF 1X^////////////////////////////77777ffi. 



: Don't care. 



Note: *l. When WE is high level, all the data on I/Os can be written into the memory cell. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

Read-Modify- Write Cycle 



RA5~ 
CAS 
Address ' 



X 



t«»n r | 




I/O 
(Output) 



DT/OE" 



/ 



Valid 
Din 



W///////////4 



it care. 



Note: *l. When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

558 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HMS34253 Series 



Page Mode Read Cycle 



MS 

ess 

Address 



\ 



Turn 



I/O 
(Output) - 



i/o 7 

(Input) 



77?" 



77777 ^ 



DSF 



2 



■nnl J ... S, / v ^ 



Z)Qe<ZZZZZ«ZZZZ3| 

t.CH -J 



t DTH 



Valid 
Dout 



leg 



j vaua ^ 

^ r Dout, r- - 





7//nr / 



WZL 



> 



7777777 



J.///////////////////////////////////, 



Y/A '■ Don't care. 



Page Mode Write Cycle (Early Write) 







CAS 



Ro» X Column 



fan. S . 7 , 'o. , V 



I/O 
(Input) 



I/O 
(Output) 



1... 



X 



Valid 
Din 



•A * ON "t* U »J t DH f o 5 U 



'//////// 

77777/} 



Valid 

Din 



High-Z 



7////////////////////////////7 777ZZ 
y////////////////////////////////7J77, 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory ce ll. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the failing edge of RAS. 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 559 



HM534253 Series 

Page Mode Write Cycle (Delayed Write) 




■ *l t ewe ■——•item r— — — »Jtewi 

■fc? — — H 



(i 



I/O 



(Output) t C i 
T5T/0T 



7^///////////^ 



Note: * 1 . When WE is high level, all the data on I/Os can be written into the mem ory c ell. When WE is low level, the data on I/Os are 
not written except for the case that the I/O is high at the falling edge of RAS. 

'.' , V; ' .". < ... 3 

RAS-Only Refresh Cycle 



RAS 



CAS 



5?= 



1 



I/O 
(Output) 

I/O 
(Input) 



DSF 



V//////////////////////////// 



DTm w ' ^//////////////////////////u 



J////////////////////////////M 

Y//\ '■ Don't care. 







560 



► HITACHI 

erra Point Pkwy. • Brisbane, CA 94005-1819 « 



CAS-Before-RAS Refresh Cycle 



HM534253 Series 



Up 



tcSR 



CAS 



zip 



tcHP 



"*•» V///////////////////////////////////^^ 

I/O High-Z 

(Output) 

™* W/////////////////////^^^ 

Y/A '■ Don't care. 



Hidden Refresh Cycle 



RAJ 



CAS 



l£?l I j HCO I _ 1 



■a: 



WE 



I/O 
(Output) 



I/O 
(Input) 



y ^///7///////////////////////, 



^//////////////////m 



Valid Data Out 



DSF 



High-Z 



^/////////////////////////////////, 



Y/A '■ Don't care. 











HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



561 



HM534253 Series 



Special Read Initialization Cycle (1) 



TOSS" 



QSF 
DT/OT 

SC 

Sl/O 
(Output) 





t-.s . 

t*CD I'JMM r 






t.», , 


tc*s 

• 3 

"& |t.sc r Ml 




P 


>H Row 




///// 


///////////////A 




V////////////////A 


■ 




"I/////////////// 


///// 


'///////////////// 






tsRD 


t,c 


1 1 1 II 1 1 1 1 /III 








tscc 
- — tsc* 


— j * t S QH 

\ ' Valid V 


Mb— 


A Sout 

^^////////////////////////, 


>///////////// 



777), : Don't t 



: rising transient 
care 



Notes : * 1 . When the previous data transfer cycle is a special read transfer cycle or special read initialization cycle, it is specified as special 

read initialization cycle (1). 

*2. SE is in low level. (When SE is high, SI/O becomes high impedance state.) 

*3. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 

Special Read Initialization Cycle (2) 1 ° 2 





R7\3~ 
US 

Address ^oVW 



X 



>////////////////////////////// 



SC 



Sl/O 
(Output)" 



Sl/O 
(Input) 



i.lz i r "i (- »j .| |. 



777X : Don't care 

ai " w/////////////////////////////////m777777. a £;rr~ 



Notes: *1. When the previous data transfer cycle is a write or pseudo transfer cycle, it is specified as special read initialization cycle (2). 
*2. SE is in low level. (When SE is high, SI/O becomes high impedance state.) 

*3. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 

<§> HITACHI 

562 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM534253 Series 



Special Read Transfer Cycle ' 



CAS 

Address 'Jtf^ 



oH" 




I/O 
(Output) 



SAM Start 
Address 



2 



■ </////////////////////////////////////, 



High-Z 



(,::, i //fi//i////ii////i//iiiii/iii//ii////iiih 



DT7CT 



SI/0 
(Output) 

SI/0 
(Input) 



% ^jllllllllllllllllllllllllllllllllllllll, 



QSF t„, 
DSF 



High-Z 



Y7A : Don't care. 



Notes: *!. When QSF is low level at the falling edge of RAS, the special read transfer cycle is not performed. 
•2. SEis in low level. (When SE is high, SI/O becomes high impedance state.) 

*3. CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 




HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 563 



HM534253 Series 



Pseudo Transfer Cycle 



RAS 



CAS ' 



tRAH f ; 



BT/OT 2! 



SAM Start Address 



)////)/////////////////, 



sc 

SI/0 
(Input) 

SI/0 
(Output) 



QSF 





x 



Y//i ■ Don't care 
fvVj : Inhibit rising transient 
I/O : Don't care 



Note: * 1 . CAS and SAM sun address don't need to be specified every cycle, if SAM sun address is not changed. 

Write Transfer Cycle 



CAS 
Address 

WE 

DT/OT 

SE 
SC 

tn 

SI/0 
(Input) 

SI/0 
(Output) 

QSF 





* 1 *CD •-+-• 1 BSH-— 


t„ 

t 


CUP 






t..c 


tCAS 

i-l 






t.s 


Row 
^ t„. 


<y •air :(//// 

tr,« 


lllll^llllllllllllll, 


ft 

ft 


Wltlllllllllllllll 

^uiiiiniMinih 


liiimiiniiiiiiiii. 
mnmmmmiih 


i 




iiiiiiiniiiiiiiiiiii 




limuiuiiuiiiu uiii 

- 1 t»»o| ^ — 

sc i(w\aaaaaaaaaaamI n 


iiimmmmi 

tjcc ■» 


It ' 


\AAAAAAAAAAAAAA/tT - 

T .tsis t 


tlH 






High-Z 






•»«» 

\ 





TTT1\ '■ Don't care 

ESS : Inhibit rising transient 



Note: *1. CAS and SAM start address don't need to be specified every cycle, if SAM sun address is not c 

HITACHI 

564 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 



Serial Read Cycle 



™* /////////////////////// vmmiiii 



(Output) 



51/0 Z3CZZX 



t so 

— ' — 



(n-1) 



[n+1) 



a r 



"l (n+ 1 ) I 1 t s „ (n + 2) 



: Don't care. 



Serial Write Cycle 



RAS 



DT/6T 



SE 



SC 



(Input) 



t 


vn 


t HAS 
^ t D TM 


J 




////////////////////// 


l 


wimnii, 



A lm 





i sec 




/. .u. ' ic : 


(n + 1) \ / 


— 'I (n ?) r 


(n-l) V ^ 


fpTnl if 


SWn-2) XV / /X'Sfl"-')^/ /////// /). V s!n d („ + ,).^/ / /X 
tsisJ N«. H K — - 



Y//\ : Don't care. 



Notes: *1. When~S~E is high level in a serial write cycle, data is not written into SAM, however, the pointer is incremented. 
*2. Address is accessed next to address 511. 



<g> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 565 



HM534253 Series 



Serial Read Cycle (Around Address 511 in SAM) 




Note * 1 . Address (i) is the SAM slart address provided in the previous special read transfer cycle. When special read transfer cycle isn't 
executed (QSF remains in high level), address is accessed next to address 511. 



Color Register Set Cycle (Early Write) 



CS5 



"WE" 



(Input) 



|te 



ET/OT 



DSF 



Address 



tpTS _ ,tpTH 



7L 



I 'Ml- 



tw 



////////////> 



_t w , — . — j\ 



7MMZZMMMM 



Y//X ■ Don't care. 



Note: *1. The level of address pin is don't care, but cannot be changed in this period. 



HITACHI 

566 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Color Register Set Cycle (Delayed Write) 



HM534253 Series 



CAS 



WE 



3t 



i/o 7 

(Input) 



r 



r _ T f///////////// 



I _ f OH ~ 



DT/OE 



* %///////////////////////////// 



Address 



[7771 - n <-.„•♦ 



: Don't care. 



Note: *1. The level of address pin is don't care, but cannot be changed in this period. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 67 



HM534253 Series 
Flash Write Cycle 



CAS 



Address 



WE 



(Input) 



DSF 











v r ... ■ 






7//// 


t RAH 


J It 1 1 )})}}}}}} I ) H ) 1 1 ) I ))))}))} I 

W////////////////////////////// 






/////A' 

//Mr 


Row 

Address. 


WHumtmmmmmi. 




- , twH 




////A 
////A 




.mmmmmimiim. 




t MH 




MA' 


/ask Data 


W///////////////////////////, 


ttlTS 


, Jo™ 




'////> 




////////////////////////////////, 


, t S FS_ 


tsFHj 



{/////////////////////////MM,. 

Y/A ■ Don't care. 



HITACHI 

568 Hitachi America, Ltd. . Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM53812UP/ZP-10/12/15-Preliminary 

131,072 x 8-Bit Multiport CMOS Video Random Access Memory 

■ DESCRIPTION 

The HM538121 is a 1-Mbit multiport video RAM equipped with a 
128-kword x 8-bit dynamic RAM and a 256-word x 8-bit SAM (serial 
access memory). Its RAM and SAM operate independently and 
asynchronously. It can transfer data between RAM and SAM and has 
a write mask function. It is suitable for a graphic processing buffer 
memory. 

■ FEATURES 

• Multiport Organization 

Asynchronous and Simultaneous Operation of RAM 
and SAM Capability 

RAM 128-kword x 8-Bit 

SAM 256-word x 8-Bit 



100/1 20/1 50ns (max.) 
30/40/50ns (max.) 
190/220/260ns (min.) 



: 385mW (max.) 
: 275mW (max.) 
40mW (max.) 



• Access Time RAM 

SAM 

• Cycle Time RAM 

SAM: 30/40/60ns (min.) 

• Low Power 

Active RAM 

SAM 

Standby 

• High Speed Page Mode Capability 

• Mask Write Mode Capability 

• Bidirectional Data Transfer Cycle Between RAM and 
SAM Capability 

• Real Time Read Transfer Capability 

• 3 V ariatio ns of Refresh (8ms/51 2 Cycles) 

RAS-Only R efres h 
CAS-Before-RAS Refresh 
Hidden Refresh 

• TTL Compatible 

■ ORDERING INFORMATION 



Part No. 


Access 


Package 


HM538121JP-10 


100ns 


400-mil 40-pin 


HM538121JP-12 


120ns 


Plastic SOJ 


HM53812UP-15 


150ns 


(CP-40D) 




■ PIN ARRANGEMENT 



sc □ 




40 


Zl VSS1 


Si/On □ 


2 


39 


□ SI/07 


Sl/Oi □ 


3 


38 


Zl Si/Oe 


SI/O2 □ 


4 


37 


Zl si/05 


si/03 (Z 


5 


36 


□ SI/04 


DT/OE L 


6 


35 


□ SE 


l/Oo C 




34 


Z 1/07 


l/Oi C 


8 


33 


Z u °e 


I/O2 □ 


9 


32 


Z 1/O5 


i/o 3 c 


10 


31 


□ I/O4 


VCC1 C 


11 


30 


Z V SS2 


WE □ 


12 


29 


□ NC 


NC □ 


13 


28 


□ NC 


RAS □ 


14 


27 


□ CAS 


NC □ 


15 


26 


□ NC 


A 8 C 


16 


25 


□ Ao 


A 6 □ 


17 


24 


□ A1 


A 6 C 


18 


23 


□ A 2 


A 4 C 


19 


22 


□ A3 


VCC2 C 


20 


21 


□ A7 



(Top View) 



PIN DESCRIPTION 



Pin Name 


Function 


A<r A 8 


Address Inputs 


I/O -l/O 7 


RAM Port Data 
Inputs/Outputs 


SI/O -SI/O 7 


SAM Port Data 
Inputs/Outputs 


RAS 


Row Address Strobe 


CAS 


Column Address Strobe 


WE 


Write Enable 


DT/OE 


Data Transfer/ 
Output Enable 


SC 


Serial Clock 


SE 


SAM Port Enable 


Vcc 


Power Supply 


Vss 


Ground 


NC 


Non Connection 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 < 



569 



HM538121JP/ZP-10/12/15 
■ BLOCK DIAGRAM 



SAM 



DT/OE 



I/O (~ 



511 



^5 



Dout 






Din 








Memory 
Array 


1 

8 




Row 





J BO 
I 0> 



511 



From 

Column Address 
(SAM Start Address) 



A Mask 
Register 



- ren 



Pin Function 

RAS (input pin): RAS is a basic RAM signal. It is 
active in low level and standby in high level. Row 
address and signa ls as shown in table 1 are input at 
the falling edge of RAS. The input level of those sig- 
nalsdetermine the operation cycleof the HM538121. 

Table 1. Operation Cycles of the HM538121 



Input Level at the Falling 
Edge of RAS 


Operation Cycle 


CAS 


DT/OE 


WE 


SE 




H 


H 


H 


X 


RAM Read/Write 


H 


H 


L 


X 


Mask Write 


H 


L 


H 


X 


Read Transfer 


H 


L 


L 


H 


Pseudo Transfer 


H 


L 


L 


L 


Write Transfer 


L 


X 


X 


X 


CBR Refresh 



NOTE: 



Don't care. 



CAS (input pin): Col umn addres s is put into chip 
at the falling edge of CAS. CAS controls output 
impedance of I/O in RAM. 

Ao-A 8 (input pins): Row address is de termined 
by Aq-As level at the falling edge of RAS. Column 
addres s is de termined by A -A 7 level at the falling 
edge of CAS. In transfer cycles, row address is the 
address on the word line which transfers data with 
SAM data register, and column address is the SAM 
start address after transfer. 

WE (input pin): WE pin has two functions at the 
falling edge of RAS and after. When WE is low at 



the falling edge of RAS, the HM538121 turns to 
mask write mode. According to the I/O leve l at the 
time, write on eac h I/O c an be masked. (WE level at 
the falling edge of RAS is don't care in rea d cycl e.) 
When WE is high at the falling edge of RAS, a 
normal write cycle is executed. After that, WE 
switches read/write cycles as in a standard DRAM. 
In a transfer cycle, the direction of trans fer is 
determined by WE level at the falling edge of RAS. 
When WE is low, data is transferred from S AM to 
RAM (data is written into RAM), and when WE is 
high, data is transferred from RAM to SAM (data is 
read from RAM). 

l/O -l/O 7 (input/output pins): I/O pins function 
as mask data at the falling edge of RAS (in mask 
write mode). Data is written only on high I/O pins. 
Data on low I/O pins are masked and internal data 
are retained. After that, they function as 
input/output pins as those of a standard DRAM. 

DT/OE (input pin): DT/OE pin func tions as DT 
(data transfer) pin at the falling edge of RAS and as 
OE (output enable) pin after that. When DT is low 
at the falling edge of RAS, this cycle becomes a 
tr ansfe r cycle. When DT is high at the falling edge 
of RAS, RAM and SAM operate independently. 

SC (input pin): SC is a basic SAM clock. In a 
serial read cycle, data is output from an Sl/O pin 
synchronously with the rising edge of SC. In a 
serial write cycle, data on an Sl/O pin at the rising 
edge of SC is put into the SAM data register. 

SE (input pin): SE pin activates SAM. When SE 
is high, Sl/O is in the high impedance state in serial 
read cycle and data on Sl/O is not put into the SAM 
data register in serial write cycle. SE can be used 
as a mask for serial write because internal pointer 
is incremented at the rising edge of SC. 



HITACHI 

570 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538121JP/ZP-10/12/15 



SI/O -SI/O 7 (input/output pins): Sl/Os are input/ 
output pins in SAM. Direction of input/output is de- 
termined by the previous transfer cycle. When it was 
a read transfer cycle, Sl/O outputs data. When it was 
a pseudo transfer cycle or write transfer cycle, Sl/O 
inputs data. 

OPERATION OF HM538121 
Operation of RAM Port 

RAM Read cycle (DT/OE high, CAS high, at the fall- 
ing edge of RAS) 

Row address is entered at th e RAS falling edge 
and column address at the CAS falling edge to the 
devi ce as in standard DRA M. T hen, when WE is high 
and DT/OE is low while CAS is low, the selected 
addres s data is outp ut th rough I/O pin. At the falling 
edge of RAS, DT/OE and CAS become high to distin- 
guish RAM read cycle from transfer cycle an d CB R 
refresh cycle. Address access time (tAA) and RAS to 
column address delay time (t RA D) specifications are 
added to enable high-speed page mode. 

RAM Write Cycle (Early Write, Dela yed Write, 
Read-Modify-Write) (DT/OE high, CAS high at the 
falling edge of RAS) 

• Normal Mode Write Cycle (WE high at the falling 
edge of RAS) 

When CAS and WE are set low after RAS is set 
low, a write cycle is executed and I/O data is written 
at the selected addresses. When all 8 l/Os a re wr it- 
ten, WE should be high at the falling edge of RAS to 
distinguish normal mode from mask write mode. 

If WE is set low before the CAS falling edge, this 
cycle becomes an early write cycle and I/ O be comes 
high impedance. Data is entered at the CAS falling 
edge. 

If WE is set low after the CAS falling edge, this 
cycle becomes a delayed write cycle. Data is input at 
the WE falling edge. I/O does not become high impe- 
dance in this cycle, so data should be entered with 
OE in high. 

If WE i s set low after tcwD (min.) and t AW o (min.) 
after the CAS falling edge, this cycle becomes a 
read-modify-write cycle and enables write after read 
to execute in the same address cycle. In this cycle 
also, to avoid I/O contention, dat a should be input 
after reading data and setting OE high. 

• Mask Write Mode (WE low at the falling edge of 
RAS 

If WE is set low at the falling edge of RAS, the 
cycle becomes a mask write mode cycle which 
writes only to selected I/O. Whether or not an I/O is 
written depe nds on I/O level (mask data) at the falling 
edge of RAS. Then the data is written in high I/O pins 
and masked in low ones and internal data is pre- 



served. This mask data is effective during the RAS 
cycle. So, in high-speed page mode cycle, the mask 
data is preserved during the page access. 

High-Speed Page Mode Cycl e (DT/OE high, CAS 
high at the falling edge of RAS) 

High-speed page mode cycle reads/writes the data 
of the same row address at high speed by toggling CAS 
while RAS is low. Its cycle time is one third of the ran- 
dom read/write cycle and is higher than the standard 
page mode cycle by 70-80%. This product is based on 
static colu mn mode, therefore, address access time 
(WO, RAS to col umn address delay time (t RA D). and 
acc ess ti me from CAS precharge (Wjp) are added. In 
one RAS cycle, 256-word memory cells of the same row 
address can be accessed. It is necessary to specify 
access frequency within t RAS max. (10 us). 

• Transfer Operation 

HM538121 provides the read transfer cycle, 
pseudo transfer cycle, and write transfer cycle as 
data tra nsfer cy cles. These transfer cycl es are set by 
driving DT/OE low at the falling edge of RAS. 
They have following functions: 

(1) Transfer data between row address and SAM 
data register (except for pseudo transfer 
cycle) 

(2) Determine direction of data transfer 

(a) Read transfer cycle: RAM -» SAM 

(b) Write transfer cycle: RAM «- SAM 

(3) Determine input or output of SAM I/O pin (Sl/O) 

Read transfer cycle: Sl/O output 
Pseudo transfer cycle, write transfer cy- 
cle: Sl/O input 

(4) Determine first SAM address to access (SAM 
start address) after transferring at column ad- 
dress. When S AM start address is not 
changed, neither CAS nor address need to be 
set because SAM start address can be latched 
internally. 

Read Transfer Cycle (CAS high, DT/OE low, WE 
high at the falling edge of RAS) 

This cycle becomes read transfer cycle by s etting 
DT/OE low and WE high at the falling edge of RAS. 
The row address data (256 x 8 bit) determined by 
thi s cycle is transferred synchrono usly at the rising 
of DT/OE. After the rising edge of DT/OE, the new 
address data outputs from SAM start address de- 
cided by column address. 

This cycle can execute SAM access serially even 
during transfer (real time read transfer). In this case, 
the timing t SDD (min.) is specified between the last 
SAM access before transfer and DT/OE rising edge, 
andJspH (min.) between the first SAM access and 
DT/OE rising edge (see figure 1). 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 571 



HM538121JP/ZP-10/12/15 



RAS 



CAS 



Address 



OT/OE 



SC 



Sl/O 



V 



/ 



" X xi X Yi X" 







SAM Data Before Transfer 



SAM Data After Transfer 







J 



Figure 1. Real Time Read Transfer 



HITACHI 

572 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538121JP/ZP-10/12/15 



If read transfer cycle is executed, SI/0 becomes 
output state. When the previous transfer cycle is ei- 
ther pseudo transfer cycle or write transfer cycle and 
Sl/O is in input state , unc ertain data is output after 
t.Ri_z (min.) after the RAS falling edge. Before that, 
input should be set high impedance to avoid data 
contention. 



Pseudo Transfer Cycle (CAS high, DT/OE low, WE 
low, and SE high at the falling edge of RAS) 

Pseudo transfer cycle is available for switching 
Sl/O from output state to input state because data in 
RAM isn ' t re writt en. This cycle starts when CAS is 
high, DT /OE l ow, WE low, and SE high, at the falling 
edge of RAS. The output buffer in Sl/O becom es 
high impedance within t SRZ (max.) from the RAS fall- 
ing edge. Data should be input to Sl/O later than t S | D 
(min.) to avoid data contention. SA M ac cess be- 
comes enabled after t SRD (min.) after RAS becomes 
high . In this cycle, SAM access is inhibited during 
RAS low, therefore, SC should not be raised. 

Write Transfer Cycle (CAS high, DT/OE low, WE 
low, and SE low at the falling edge of RAS) 

Write transfer cycle can transfer a row of data 
input by serial write cycle to RAM. The row address 
of data transferred into RAM is de termined by the 
address at the falling edge of RAS. The column ad- 
dress is specified as the first address to serial write 
after terminating this cycle. Also in this cycle, SAM 
access becomes enabled after tsRD (min.) after RAS 
becomes high. SAM access is inhibited during RAS 
low. In this period, SC should not be raised. 

■ SAM PORT OPERATION 
• Serial Read Cycle 

SAM port is in read mode when the previous data 
transfer cycle is read transfer cycle. Access is syn- 
chronized with SC rising, and SAM data is output 
from Sl/O. If SE is set high Sl/O becomes high impe- 
dance and internal pointer is incremented at the SC 
rising edge. 



• Serial Write Cycle 

If previous data transfer cycle is pseudo transfer 
cycle or write transfer cycle, SAM port goes into write 
mode. In this cycle, Sl/O data is programmed into data 
register at_ the SC rising edge like in the serial read 
cycle. If SE is high, Sl/O data isn't input into data regis- 
ter. Internal pointer is incremented according to the SC 
rising edge, so SE high can mask data for SAM. 

■ REFRESH 

• RAM Refresh 

RAM, which is composed of dynamic circuits, re- 
quires refresh to retain data. Refresh is performed by 
accessing all 512 row addre sses every 8 ms. There 
ar e thre e refre sh cy cles: (1) RAS-only refresh cycle, 
(2) CAS-before RAS (CBR) refresh cycle, and (3) Hid- 
den refr esh c ycle. Besides them, the cycles which 
activate RAS such as read/write cycles or transfer 
cycles can refresh the row address. Therefore, no 
refresh cycle is required for accessing all row ad- 
dresses every 8 ms. 

RAS-Only Refresh Cy cle: R AS-only cy cle is per- 
formed by activating only RAS cycle with CAS fixed 
to high by inputting the row address ( = refresh ad- 
dress) from external circuits. In this cycle, output is 
high-impedance and power dissipation i s less than 
that of normal read/write cycles because CAS inter- 
nal circuits don't operate. To distinguish this cycle 
from data transfer cycle , DT/OE should be high at 
the falling edge of RAS. 

CBR R efres h Cycl e: CB R refresh cycle is set by 
activating CAS before RAS. In this cycle, refresh ad- 
dress need not to be input through external circuits 
because it is input through an internal refresh 
counter. In this cycle, output is in high i mped ance 
and power dissipation is low ered like in RAS-only 
refresh cycles because CAS circuits don't operate.. 

Hidden Refresh Cycle: Hi dden refresh cycle per- 
forms refresh by reactivating RAS when DT/OE and 
CAS keep low in normal RAM read cycles. 



• SAM Refresh 

SAM parts (data register, shift register, selector), or- 
ganized as fully static circuitry, don't require refresh. 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 73 



HM538121JP/ZP-10/12/15 

■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Terminal Voltage* >> 


V T 


-1.0 to +7.0 


V 


Power Supply Voltage* 


Vcc 


-0.5 to +7.0 


V 


Power Dissipation 


P T 


1.0 


w 


Operating Temperature 


T 

1 opr 


to +70 


°c 


Storage Temperature 


T stg 


-55 to + 125 


°c 



NOTE: 1. Relative to V S s- 

■ RECOMMENDED DC OPERATING CONDITIONS (T a = to 70°C) 



Parameter 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Supply Voltage* 1 ) 


Vcc 


4.5 


5.0 


5.5 


V 


Input High Voltage") 


V,H 


2.4 




6.5 


V 


Input Low Voltage* ') 


V,L 


-0.5*2) 




0.8 


V 



NOTES: 1. All voltages referenced to Vss. 

2. -3.0V for pulse width < 10ns. 



■ DC CHARACTERISTICS (T a = Oto 70°C, V cc = 5V ± 10%, V ss = 0V) 



Item 


Symbol 


Test Conditions 


HM538121-IO 


HM538I21-12 


HM538I21-15 


Unit 


RAM Port 


SAM Port 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Operating Current 


k:CI 


RAS, CAS Cycling 
t RC = Min. 


SC, SE = V IH 




70 




60 




50 


m A 


^CC7 


SE = V, L , SC Cycling 
'sec = Mi"- 




120 




100 




80 


mA 


Standby Current 


Ice: 




SC, SE = V iH 




7 




7 




7 


mA 


Ices 


RAS, CAS = V IH 


SE = V 1L , SC Cycling 
'sec = Min. 




50 




40 




30 


mA 


RAS-Only Refresh 
Current 


lcC3 


RAS Cycling 


SC, SE = V IH 




w 




50 




40 


mA 


*CC9 


CAS = V 1H 
t RC - Min. 


SE = V, L , SC Cycling 
'sec = Mm - 




110 




90 




70 


mA 


Page Mode Current 


led 


CAS Cycling 


SC, SE = V IH 




65 




55 




45 


mA 


IcCK) 


RAS = V IL t RC = 
Min. 


SE = V, L , SC Cycling 
'sec = Min. 




115 




95 




75 


mA 


CAS Before-RAS Refresh 
Current 


lcC5 


RAS Cycling 
t RC = Min. 


SC, SE = V IH 




60 




50 




40 


mA 


Ljcii 


SE = V IL , SC Cycling 
'sec = Min 




110 




90 




70 


mA 


Data Transfer Current 


•cc6 


RAS, CAS Cycling 
t RC = Min. 


SC, SE = V IH 




90 




90 




90 


mA 


kxtt 


SE = V, L , SC Cycling 
•sec = Min - 




125 




125 




125 


mA 


Input Leakage Current 



•li 




-10 


10 


-10 


10 


-10 


10 


M 


Output Leakage Current 


Ilo 




-10 


10 


-10 


10 


-10 


10 


fA 


Output High Voltage 


V OH 


■oH = " 2mA 


2.4 




2.4 




2.4 




V 


Output Low Voltage 


Vol 


I OL = 4.2mA 




0.4 




0.4 




0.4 


V 



HITACHI 

574 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538121JP/ZP-10/12/15 

■ CAPACITANCE (T a = 25°C, V cc = 5V, f = 1MHz, Bias: Clock, I/O = V cc , address = V ss ) 



Parameter 


Symbol 


Min. 


Typ. 


Max. 


Unit 


Address 


Ch 






5 


pF 


Clocks 








5 


pF 


I/O, SI/O 








7 


pF 



■ AC CHARACTERISTICS (T a = to 70°C, V cc = 5V ± 10%, V ss = 0V) (')• <»> 
• Test Conditions 

• Input Rise and Fall Time: 5ns • Input Timing Reference Levels: 0.8V, 2.4V 

• Output Load: See Figures • Output Timing Reference Levels: 0.4V, 2.4V 

+ 5V +SV 




•Including scope and jig. 



• Common Parameter 



Parameter 


Symbol 


HM538121-10 


HM538121-12 


HM538121-15 


Unit 


Note 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Random Read or Write Cycle Time 


l RC 


190 




220 




260 




ns 




RAS Precharge Time 


<rp 


80 




90 




100 




ns 




RAS Pulse Width 


'ras 


100 


10000 


120 


10000 


150 


10000 


ns 




CAS Pulse Width 


l CAS 


30 


10000 


35 


10000 


40 


10000 


ns 




Row Address Setup Time 


l ASR 

















ns 




Row Address Hold Time 


'rah 


15 




15 




20 




ns 




Column Address Setup Time 


l ASC 

















ns 




Column Address Hold Time 


tCAH 


20 




20 




25 




ns 




RAS to CAS Delay Time 


<RCD 


25 


70 


25 


85 


30 


110 


ns 


5. 6 


RAS Hold Time 


<rsh 


30 




35 




40 




ns 




CAS Hold Time 


f CSH 


100 




120 




150 




ns 




CAS to RAS Precharge Time 


<CRP 


10 




10 




10 




ns 




Transition Time (Rise to Fall) 


t T 


3 


50 


3 


50 


3 


50 


ns 


8 


Refresh Period 


l REF 




8 




8 




8 


ms 




DT to RAS Setup Time 


l DTS 

















ns 




DT to RAS Hold Time 


'dth 


15 




15 




20 




ns 




Data-in to OE Delay Time 


'dzo 

















ns 




Data-in to CAS Delay Time 


'dzc 

















ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 75 



HM538121JP/ZP-10/12/15 

• Read Cycle (RAM), Page Mode Read Cycle 



Parameter 


Symbol 


HM538121-10 


HM538121-12 


HM538121-15 


I Tnif 

unn 


Note 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Access Time From RAS 


l RAC 


- 


100 


- 


120 


- 


150 


ns 


2, 3 


Access Time From CAS 


'CAC 




30 




35 




40 


ns 


3, 5 


Access Time From OE 


•OAC 




30 




35 




40 


ns 


3 


Address Access Time 


l AA 




45 




55 




70 




3 6 


f"liirnnt RulT^r- Turn (~1(Y Fftoloir 

output DUirer lurn <jit ueiay 
Referenced to CAS 


l OFFI 





25 





30 





40 


ns 


7 


wuiput Duller iurn kjii ueiay 
Referenced to OE 


<OFF2 





25 





30 





40 


ns 


7 


Read Command Setup Time 


*RCS 




















ns 




Read Command Hold Time 


'rch 





_ 





_ 








ns 


12 


Read Command Hold Time 


Referenced to RAS 


l RRH 


10 


- 


10 


- 


10 


- 


ns 


12 


RAS to Column Address Delay Time 


l RAD 


20 


55 


20 


65 


25 


80 


ns 


5, 6 


Page Mode Cycle Time 


'pc 


55 




65 




80 




ns 





CAS Precharge Time 


t CP 


10 




15 




20 




ns 




Access Time From CAS Precharge 


l ACP 




50 




60 




75 


ns 




• Write Cycle (RAM), Page Mode Write Cycle 
















Parameter 


Symbol 


HM538121-10 


HM538121-12 


HM538121-15 


unit 


Note 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Write Command Setup Time 


'wcs 

















ns 


9 


Write Command Hold Time 


( WCH 


25 




25 




30 




ns 




Write Command Pulse Width 


l WP 


15 




20 




25 




ns 




Write Command to RAS Lead Time 


[ RWL 


30 




35 




40 




ns 




Write Command to CAS Lead Time 


<CWL 


30 




35 




40 




ns 




Data-in Setup Time 


'ds 

















ns 


10 


Data-in Hold Time 


( DH 


25 




25 




30 




ns 


10 


WE to RAS Setup Time 


tws 

















ns 




WE to RAS Hold Time 


'WH 


15 




15 




20 




ns 




Mask Data to RAS Setup Time 


'MS 

















ns 




Mask Data to RAS Hold Time 


l MH 


15 




15 




20 




ns 




OE Hold Time 
Referenced to WE 


l OEH 


10 




15 




20 




ns 




Page Mode Cycle Time 


t PC 


55 




65 




80 




ns 




CAS Precharge Time 


'CP 


10 




15 




20 




ns 






HITACHI 

576 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538121JP/ZP-10/12/15 



• Read-Modify-Write Cycle 



rdlalllLIC) 


Svmhnl 


HM538121-10 


HM538121-12 


HM538121-15 


Unit 


Note 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Read Modify Write Cycle Time 


<RWC 


255 


— 


295 


— 


350 


— 


ns 




RAS Pulse Width 


l RWS 


165 


100(X1 


195 


10000 


240 


10000 


ns 




CAS to WE Delay 


<CWD 


65 


— 


75 


— 


90 


— 


ns 


9 


Column Address to WE Delay 


l AWD 


80 


— 


95 


— 


120 


- 


ns 


9 


OE to Data-in Delay Time 


l ODD 


25 




30 




40 




ns 




Access time from RAS 


<RAC 




100 




120 




150 


ns 


2, 3 


Access Time from CAS 


k;AC 





30 


— 


35 


— 


40 


ns 


3, 5 


Access Time from OE 


tOAC 





30 





35 





40 


ns 


3 


Address Access Time 


l AA 





45 


— 


55 


— 


70 


ns 


3, 6 


RAS to Column Address Delay 


l RAD 


20 


55 


20 


65 


25 


80 


ns 


5,6 


Output Buffer Turn-Off Delay 
Referenced to OE 


l OFF2 


U 




U 




U 


An 
4U 


ns 




Read Command Setup Time 


l RCS 





— 





— 





— 


ns 




Write Command to RAS Lead Time 


'rwl 


30 


— 


35 


— 


40 


— 


ns 




Write Command to CAS Lead Time 




30 


- 


35 


- 


40 


- 


ns 




Write Command Pulse Width 


l WP 


15 


- 


20 


- 


25 


- 


ns 




Data-in Setup Time 


l DS 





— 





— 





— 


ns 


10 


Data-in Hold Time 


l DH 


25 




25 




30 




ns 


10 


WE to RAS Setup Time 


l WS 

















ns 




WE to RAS Hold Time 


l WH | '5 








20 




ns 




Mask Data to RAS Setup Time 


l MS 

















ns 




Mask Data to RAS Hold Time 


l MH 


15 




15 




20 




ns 




OE Hold Time Referenced to WE 


l OEH 


10 




15 




20 




ns 





• Refresh Cycle 



Parameter 


Symbol 


HM538121-10 


HM538121-12 


HM538121-15 


Unit 


Note 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


CAS Setup Time (CAS-Before-RAS Refresh) 


k;sR 


10 




10 




10 




ns 




CAS Hold Time (CAS-Before-RAS Refresh) 


km 


20 




25 




30 




ns 




RAS Precharge to CAS Hold Time 


l RPC 


10 




10 




10 




ns 





HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 77 



HM538121JP/ZP-10/12/15 
• Transfer Cycle 



Psrsmctcr 


Symbol 


HM538121-10 


HM538121-12 


HM538121-15 


Unit 


Note 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


WE to RAS Setup Time 


'ws 





— 





— 





— 


ns 




WE to RAS Hold Time 




15 


— 


15 


— 


20 


— 


ns 




SE to RAS Setup Time 


'es 





— 





— 





— 


ns 




SE to RAS Hold Time 


tfiH 


15 


— 


15 


— 


20 


— 


ns 




RAS to SC Delay Time 


'SRD 


25 


— 


30 


— 


35 


— 


ns 




SC to RAS Setup Time 


'SRS 


30 


— 


40 


— 


45 


— 


ns 




f5T Hold Time from RAS 


'RDH 


TBD 


— 


TBD 


— 


TBD 


— 


ns 




DT Hold Time from CAS 


'CDH 


20 


— 


30 


— 


45 


— 


ns 




Last SC to DT Delay Time 


'SDD 


5 


— 


5 


— 


10 


— 


ns 




First SC to DT Hold Time 


'SDH 


TBD 


— 


TBD 


— 


TBD 


— 


ns 




DT to RAS Lead Time 


'DTL 


50 


— 


50 


— 


50 


— 


ns 




DT Hold Time Referenced to RAS High 


'dthh 


20 


— 


25 


— 


30 


— 


ns 




DT Precharge Time 


'dtp 


30 


— 


35 


— 


40 


— 


ns 




Serial Data Input Delay Time from RAS 


'SID 


50 


— 


60 


— 


75 


— 


ns 




Serial Data Input to RAS Delay Time 


'SZR 


— 


10 


— 


10 


— 


10 


ns 




Serial Output Buffer Turn-Off Delay from RAS 


'SRZ 


10 


50 


10 


60 


10 


75 


ns 


7 


RAS to S out (Low Z) Delay Time 


•rlz 


5 


— 


10 


— 


10 




ns 




Serial Clock Cycle Time 


'sec 


30 


— 


40 


— 


60 


— 


ns 




Access Time from SC 


( SCA 




30 




40 




50 


ns 


4 


Serial Data Out Hold Time 


'sOH 


7 




7 




7 




ns 


4 


SC Pulse Width 


'sc 


10 




10 




10 




ns 




SC Precharge Width 


'SCP 


10 




10 




10 




ns 




Serial Data-in Setup Time 


'SIS 

















ns 




Serial Data-in Hold Time 


'SIH 


15 




20 




25 




ns 




• Serial Read Cycle 





Parameter 


Symbol 


HM538121-10 


HM538121-12 


HM538121-15 


Unit 


Note 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Serial Clock Cycle Time 


'sec 


30 




40 




60 




ns 




Access Time from SC 


'SCA 




30 




40 




50 


ns 


4 


Access Time from SE 


l SEA 




25 




30 




40 


ns 


4 


Serial Data-Out Hold Time 


'SOH 


7 




7 




7 




ns 


4 


SC Pulse Width 


'sc 


10 




10 




10 




ns 




SC Precharge Width 


'scp 


10 




10 




10 




ns 




Serial Output Buffer Turn-Off Delay from SE 


'SEZ 





25 





25 





30 


ns 


7 



HITACHI 

578 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538121JP/ZP-10/12/15 



• Serial Write Cycle 



Parameter 


Symbol 


HM538121-10 


HM538121-12 


HM538121-15 


Unit 


Note 


Min. 


Max. 


Min. 


Max. 


Min. 


Max. 


Serial Clock Cycle Time 


'sec 






An 




f>fi 
OU 




ns 




ot riiise wiatn 


l sc 


in 




in 




in 

1U 




ns 




frecnarge Width 


l SCP 


in 

1U 




in 




in 

1U 




ns 




oenai Data-in oetup lime 


l SIS 


o 




o 




o 




ns 




^prial T^afn-ln HnlH Tim** 
OCl Idl UaUX in nuiu 1 IIHL 


r SIH 


15 




20 




25 








Serial Write Enable Setup Time 


l SWS 

















ns 




Serial Write Enable Hold Time 


l SWH 


30 




35 




50 




ns 




Serial Write Disable Setup Time 


l SWIS 

















ns 




Serial Write Disable Hold Time 


<SWIH 


30 




35 




50 




ns 





NOTES: 



> greater than the maximum 



2. Assumes that t R cD S tRCD (max) and t RA D £ Irad (max). If tRCD or tRAD i 
recommended value shown in this table, tR A c exceeds the value shown. 

3. Measured with a load circuit equivalent to 2 TTL loads and lOOpF. 

4. Measured with a load circuit equivalent to 2 TTL loads and 50pF. 

5. When tRCD a tRCD (max) and tRAD s tRAD (max), access time is specified by tcAC 

6. When Ircd S tRCD (max) and (rad 2: tRAD (max), access time is specified by Iaa- 

7. toFF (max) is defined as the time at which the output achieves the open circuit condition (Voh - 200mV, Vol + 
200m V). 

8. Vjh (min) and Vil (max) are reference levels for measuring timing of input signals. Transition times are measured 
between Vih and Vil. 

9. When twcs a twcs (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) 
condition. When tAWD a tAWD (min) and tcwD ^ tcwD (min), the cycle is a read-modify-write cycle; the data of the 
selected address is read out from a data output pin and input data is written into the selected address. In this case, 
impedance on I/O pins is controlled by OE. 

These parameters are referenced to CAS falling edge in early write cycles or to WE falling edge in delayed write or 
read-modify-write cycles. 

After power-up. pause for 100 (is or more and execute at least 8 initialization cycles (normal memory cycles or 
refresh cycles), then start operation. 
12. If either tRCH or (krh is satisfied, operation is guaranteed. 



10 



I I 



Hitachi America, Ltd. • Hitachi Plaza • 




CA 94005-1819 • (415) 589-8300 5 79 



HM538121JP/ZP-10/12/15 

■ TIMING WAVEFORMS 
• Read Cycle 



RA5 



JSC. 



L 1 


tna 


. Urn... 


to. 





Address 



2xf_ 



WE . 7, 



I/O 
(Output) 



'r 

w 



1/0 Wl /Wllf fa 



(Input) 



15T/0T 



< 




W/// / /M 



Valid 



Early Write Cycle 



Address 



I/O 
(Input) 



I/O 
(Output) 



"5T/0T 



C f///ff//l 



High-Z 



Y//X '■ Don't care. 



NOTE: 



580 



. When WE is high level, all the data on I/Os can be written into the memory cell. Whe n WE is low level, the data on 
I/Os are not written except for the case that the I/O is high at the falling edge of RAS. 



HITACHI 

, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA ! 



■ (415) 589-8300 



HM538121JP/ZP-10/12/15 



Delayed Write Cycle 



RAS 



n 



7- 



K 



■•— t C AK »J 



"DT/OT 



(Input) 



I/O 
(Output) ■ 



*1 




Valid Data In 



High-Z 



£22 : Don't care. 



NOTE: 1 . When WE is high level, all the data on I/Os can be written into the memory cell. Whe n WE is low level, the data on 
I/Os are not written except for the case that the I/O is high at the falling edge of RAS. 

• Read-Modify-Write Cycle 



"CAS 



Address 



I/O 
(Input) 



Row 



tc*H 



I/O 
(Output) 



"DT/OT 




Valid 



" ^/////////// 



Y//X '■ Don't care. 



NOTE: I . When WE is high level, all the data on I/Os can be written into the memory cell. When WE is low level, the data on 
I/Os are not written except for the case that the I/O is high at the falling edge of RAS. 



% HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. . Brisbane, CA 94005-1819 • (415) 589-8300 581 



HM538121JP/ZP-10/12/15 
• Page Mode Read Cycle 



RAS 



CAS 



t.c 



,c llJaui,! ! c • -I ,c 



-m 



mm. 



I/O . 
(Output) 



(Input) 

USA 



< 



t DZO 




' i h-it,., t.„-| -fHt K , Ut,c» h:lm. I t.c.H '" H 



Valid 
Dout 



/ Valid v 
\ Dout 



$777%' 



OAC I OF Fl 



Valid 
Dout 



Z 



Y/A ■ Don't care. 



• Page Mode Write Cycle (Early Write) 



£as 



Address 



a: 



K 



24 



I/O 
(Input) 

I/O 

(Output) , , 

lOU t BT 



T5T/0T 



8 



dry ^izy 



Valid 
Din 



Valid 
Din 



Valid 
Din 



WZMIl 



High-Z 



V///////////////////////////////77777 

! Don't care. 



NOTE: 1 . When WE is high level, all the data on I/Os can be written into the memory cell. When WE is low level, the data on 
I/Os are not written except for the case that the I/O is high at the falling edge of RAS. 

<§► HITACHI 

582 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• Page Mode Write Cycle (Delayed Write) 



HM538121JP/ZP-10/12/15 



HAS 



-tc»M- 



/ 



■ * _lr" n * *»s * *»c * CAN 

t AIC -••I "» — I H — *m- E 4H 

— ?^Y=^m77^(77777) ^////////^ 

[twh. f" H '"I I 1 ■ I '«L p J tcwi I 



I/O 
(Inpi 



I/O 
(Output) 

T5T/OT 



i^mr m Yttttt%. \nny\ /////////. 

till t MH t ) t H tflS ton tpg ^QH I 

i 3Q®@(^Azzz^^zzzzz; 



High-Z 



Y7A ■ Don't care. 



NOTE: I . When WE is high level, all the data on I/Os can be written into the memory cell. When WE is low level, the data on 
I/Os are not written except for the case that the I/O is high at the falling edge of RAS. 



• RAS-Only Refresh Cycle 



rS5 



Address 



2>: 



if 



t,,c 



i/o 7/ 

(Output) 



I/O 
(Input) 



"DT/OT 



vii nun 
ft fiiiiiiiiiiiiiimiim 



TF 



viiiiiiiiiiiiiuiiii/i, 

t(>TH 

^ i/i/miimiiii/ii/h 



77A : Don't care. 



Hitachi America, Ltd. 1 



>-1819 • (415) 589-8300 



583 



HM538121 JP/ZP-10/12/15 



• CAS-Before-RAS Refresh Cycle 



RAS 



CAS 



7 



v 



— //////////////////////////? 

* V////////////////////////Z 



z, v///////////////////////; 



I/O 
(Output) 

"DT/OT 



High-2 



V//////////////////// 2 

'■ Don't care. 



• Hidden Refresh Cycle 







RAS 




Address 



X 



Column 



WE 



I/O . 
(Output) 



DT/OE 



i/o ztx 

:m P ut) J_L<r 



y///////////////77777, 



*<///////////////, 



t».c 



Valid Data Out 



High-Z 



K/ZI : Don't care. 



HITACHI 

584 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538121JP/ZP-10/12/15 



• Read Transfer Cycle (1) <*> 



EI5 l» 
address ~Q 



ft 



I/O . 
(Output) 

I/O 
(Input) 



J=5 



yniiimiiiiiiirrrri 



^ iiiiiiiiiiiiiTWjii/iiiiii 

Hiffh-Z ~ 'I 



z 



///7///////////////////////////////// / 



[ZZZZ5 




£23 : Don't care. 



NOTES: 1 . When the previous data transfer cycle is a read transfer cycle, it is defined as read transfer cycle (1). 

2. SE is in low level. (When SE is high, SI/O becomes high impedance). 

3. CAS and SAM start address don't need to be specified every cycle if SAM start address is not changed. 

• Read Transfer Cycle (2) 0). (2) 



Addrej* '/OB Row 



I/O 
(Output) * 



^ (77777777/ 7777 



7777777 



- illlllllllllllllllllllllllllli 



:,::„ v//////////////7///!///////////g z 



(Input) 
BT/SF 



SC 



SI/0 
(Output) 



Milium 



- *—j - — X /\/ X X X X /\ / N/- ■ 

t t,c ' 

II :/)/////// 


- ij ' 

'7///H v... 


- \_ 

tfO* 

rV/v/ 


r *■ j 





I7ZI : Oon t < 



NOTES: 1 . When the previous data transfer cycle is a write or pseudo transfer cycle, it is defined as read transfer cycle (2). 

2. SE is in low level. (When SE is high, SI/O becomes high impedance). 

3. CAS and SAM start address don't need to be specified every cycle if SAM start address is not changed. 

HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 . (415) 589-8300 5 85 



HM538121JP/ZP-10/12/15 
• Pseudo Transfer Cycle 



T«s" 
Ca5~ 

Address 
WE 



i 



D7/ST A 



SC 

Si/O 
(Input) 

SI/O 
(Output) 



3)i 



7 



//// // iiiiiHium m 



uiiiiiiiiiniiiiiimiiinih 



^lllllllllllllillllllllllllTJUTT 



%l jiiiiiiiiii jjm 



■'"*'.» . 1 '..sK- ll!!L 



77777777 



X 



3///////////) T^i gzzzxz: 



i 



: Don't care 
KXXi ■ Inhibit rising transient 
I/O : Don't care 



NOTE: 1 . CAS and SAM start address don't need to be specified every cycle, if SAM start address is not 

• Write Transfer Cycle 



CAS 
Address 

TJf/OT 




X 



1 



V 



L .ll, *™ n _ i 




si/o 

(Input) 

SI/0 
(Output) 



• til" 



^ZZZZK 



High-Z 



V//A '■ Don't care 

j)QO<] I Inhibit rising transient 



NOTE: l . CAS and SAM start address don't need to be specified every cycle, if SAM start address is not changed. 



HITACHI 

586 Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM538121JP/ZP-10/12/15 



• Serial Read Cycle 



OT/OE 



sc 



iniiniimmmmir viiiiiitttt 



Sl/O 
(Output) 



_t cc- 



J 



Valid 
Sout 



i 



(n + l)\ 



7 Valic 
^ Soul 
"1 (n+l) 



(n + 2) 



\ r 



Valid 
Sout 



(n+2) 



y/Xi '■ Don't care. 



• Serial Write Cycle 



"ESS 

OT/OE 
5E 
sc 



1 


OTS 


tttl 

t0TH 

T 


■ 


1 


////////////////////// 


- 


VIUIIIIII, 



X 



y. t.c '»" . hi - '»c , V.I t m . i TtTT / M t.c ; r t, c ; / 

a jSS)czzH33czzzzzzzz>es 



till tsiH 

Y//\ '■ Don't care. 



NOTES: 1 . When SE is high level in a serial write cycle, data is not written into SAM, however, the pointer is incremented. 
2. Address is accessed next to address 255. 

<§> HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 587 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



Section 5 
MOS Dynamic RAM 



HITACHI 



HMS0464 Series 



65536-word x 4-bit Dynamic Random Access Memory 

■ FEATURES 

• Page mode capability 

• Single 5 V (±10%) 

• On chip substrate bias generator 

• Low power: 350 rnW active, 20 mW standby 

• High speed: Access Time 120ns/150ns/200ns 

• Output data controlled by CAS or OE 

• TTL compatible 

• 256 refresh cycles 4 ms 

• 3 variations of refresh RAS only refresh 

CAS before RAS refresh 
Hidden refresh 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM50464P-12 
HM50464P-15 
HM50464P-20 


120ns 
150ns 
200ns 


300 mil 18 pin 
Plastic DIP 


HM50464CP-12 


120ns 




HM50464CP-15 


150ns 


18 pin PLCC 


HM50464CP-20 


200ns 





HM50464P Series 



(DP-18B) 



HM50464CP Series 



(CP-18) 



PIN ARRANGEMENT 

• HM50464P Series 



■ BLOCK DIAGRAM 



I/O I/O I/OI/O 
12 3 4 




• HM50464CP Series 



Index Corner 




OE[T 


Tj] Vss 


I/OlU 


TT] 1/04 


1/02(7 


T|j CAS 


wr [7 


Tj] 1/03 


RASH 


TJ] Ac 


A. (J 


TJJ A> 


A 2 [7 


Tj] A2 


A3[? 


TT) A3 


VccH 


To] A? 



(Top View) 



(Top View! 



Ao-A, 


Address Inputs 


CAS 


Column Address Strobe 


1/01 - 
1/04 


Data In/Data Out 


OE 


Output Enable 


RAS 


Row Address Strobe 


WE 


Read/Write Input 


Vcc 


Power (+5V) 




Ground 


A ~ A 7 
(Row) 


Refresh Address Inputs 



590 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM50464 Series 



■ ABSOLUTE MAXIMUM RATINGS 



Item 


Symbol 


Rating 


Unit 


Voltage on any pin relative to V s g 


V T 


-lto +7 


V 


Supply Voltage relative to Vgg 


Vcc 


-1 to +7 


V 


Operating Temperature (Ambient) 


Topr 


Oto +70 


•c 


Storage Temperature (Ambient) 


Tstg 


-55 to +125 


°c 


Power Dissipation 


P T 


1.0 


w 


Short Circuit Output Current 


lout 


50 


mA 



■ RECOMMENDED DC OPERATING CONDITION (Ta = to +70°C) 



Parameter 


Symbol 


min. 


typ. 


max. 


unit 


Supply Voltage 


v C c 


4.5 


5.0 


5.5 


V 


Input High Voltage 




2.4 




6.5 


V 


Input Low Voltage 


VlL 


-1.0 




0.8 


V 



Note) All voltage referenced to Vgg. 



■ DC ELECTRICAL CHARACTERISTICS (Vcc = 5V + 10%, Vss = 0V, Ta = to +70°C) 



Parameter 


Symbol 


HM 50464- 12 


HM 50464-1 5 


HM 50464-20 


Unit 


Note 


min. 


max. 


min. 


max. 


min 


max. 


Operating Current (tRc = min.) 


'cci 




'83 




70 




55 


mA 


1 


Standby Current (RAS ■ V m , Dout ■ Disable) 


'CC2 




4.5 




4.5 




4.5 


mA 




Refresh Current (RAS only refresh. i R q = min.) 


'CC3 




62 




53 




42 


mA 




Standby Current (RAS - V IH . Dout - Enable) 


'ccs 




10 




10 




10 


mA 




Refresh Curreni (CAS before RAS refresh, i RC = min.) 


'CC6 




69 




58 




45 


mA 




Operating Current (Page mode. ( pc = min.) 


'CC7 




57 




48 




37 


mA 




Input Leakage Current (0 < Vin < 7V) 


'LI 


-10 


10 


-10 


10 


- 10 


10 


«A 




Output Leakage Current (0 < I'out < 7V. Dout - Disable) 














Output High Voltage (/our = -5 mA) 










>CC 










Output Low Voltage (/our " 4.2 mA) 


Vol 


• 


0.4 




0.4 





0.4 







Note) 1 . I cc depends on output loading condition when the device is selected, I cc max. is specified at the output open 
condition. 



■ CAPACITANCE (K cc = 5V ± 10%, Ta = 25°C) 



Parameter 


Symbol 


typ. 


max. 


Unit 


Note 


Input Capacitance 


Address 


C/l 




5 


PF 


1 


RAS.CAS.TSl.OE 


cn 




10 


PF 


1 


Output Capacitance 


Data In/Data Out 


ClIO 




10 


PF 


1,2 



Notes) 1. Capa citance measured with Boonton Meter or effective capacitance measuring method. 
2. CAS = V IH to disable Dout. 

■ ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS 

{Vcc = 5V + 10%, Vss = 0V, Ta = to +70°C) 



Parameter 


Symbol 


HM50464-I2 


HM50464-I5 


HM 50464-20 


Unit 


Note 


min. 


max. 


min. 


max. 


min. 


max. 


Access Time from RAS 


<RAC 




1 20 




150 




200 


ns 


2.3 


Access Time from CAS 


'CAC 




60 




75 




100 


ns 


3.4 


Output Buffer Turn-off Delay referenced to CAS 


'OFFl 




30 




40 




50 


ns 


5 


Transition Time (Rise and Fall) 


>T 


3 


50 


3 


50 


3 


50 


ns 


6 


Random Read or Write Cycle Time 


•rc 


220 




260 




330 




ns 




RAS Precharge Time 


Irp 


90 




100 




120 




ns 




RAS Pulse Width 


'RAS 


120 


10000 


150 


10000 


200 


10000 


ns 




CAS Pulse Width 


'CAS 


60 


10000 


75 


10000 


100 


10000 


ns 




R~A"5 to CAS Delay Time 


<RCD 


2f 


60 


25 


75 


30 


100 


ns 


7 


RAS Hold Time 


IRSH 


60 




75 




100 




ns 




CAS Hold Time 


'CSH 


120 




150 




200 




ns 




CAS lo RAS Precharge Time 


'CRP 


10 




10 




10 




ns 




Row Address Set-up Time 


'ASR 

















ns 




Row Address Hold Time 


>RAH 


15 




15 




20 




ns 





(to be continued) 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 591 



Parameter 


Symbol 


HM50464-I2 


HM 50464-1 5 


HM 50464-20 


Unit 


Note 














Column Address Set-up Time 


l ASC 


o 




o 




o 








Column Address Hold Time 


*CAH 


20 








30 








Column Address Hold Time referenced to RAS 


' AR 


80 




100 




1 30 








Write Command Set-up Time 




o 




o 




q 






'8 


Write Command Hold Time 


' WCH 


40 




45 




55 




ns 




Write Command Hold Time referenced to RAS 


' WCR 


100 




1 20 




1 55 








Write Command Pulse Width 


' wp 


40 




45 




55 








write Lommana to KAa Lea a lime 


IRWL 


40 


- 


45 


- 


55 


- 


i ,i 
ns 




Write Command to CAS Lead Time 


'CWL 


40 


- 


45 


- 


55 




ns 




Data-in Set-up Time 


>ds 





- 










- 


ns 


9 


Data-in Hold Time 


<dh 


40 


- 


45 




55 


- 


ns 


9 


Data-in Hold Time referenced to RAS 


<dhr 


100 


- 


120 


- 


155 


- 


ns 




Read Command Set-up Time 


<RCS 























'RCH 





Z 
















Read Command Hold Time referenced to RAS 


tRRH 


10 




10 




10 




ns 




Refresh Period 


IREF 




4 




4 




4 


ms 






IRWC 


305 




360 




450 




ns 




r*C *n WF TVIsv Tim* 


'CWD 


100 




125 




160 


— 


ns 


g 


KAo to wt. Delay lime 


IRWD 


160 


— 


200 




260 




ns 


8 


c'Aa' Precharge Tune 


'CPU 


50 


- 


60 


- 


80 


- 


ns 




t^Aa aet-up lime (CAa oeiore KAa retresn) 


'CSR 


10 




10 


- 


10 


- 


ns 




^" A P UnU Ti«ma ITAC luf.u n a A 1 

tAa nolo lime (CAa oeiore KAa reiresn) 


'CHR 


120 




150 




'200 




ns 




D AC Dr*f>harM PiC U n |H Tim* 

KAa iTccnirge 10 las hoio lime 


'RPC 















— 


ns 




Access Tune from 0E" 


'OAC 




30 




35 




45 


ns 




Output Buffer Turn-off Delay referenced to 0E 


'OFF1 




30 




40 




50 






(5E to Data-in Delay Time 


'ODD 


30 




40 




50 




ns 




0E Hold Time referenced to WE 


'OEH 


25 




30 




40 




ns 




Page Mode Cycle Time 


'PC 


120 




145 




190 




ns 




CAS Precharge Time (for Page-mode Cycle Only) 


'CP 


50 




60 




80 




ns 




CX5 Read-modify-write Cycle Time (Page-mode) 


'PCM 


205 




245 




310 




ns 





Notes) 

1. AC measurements assume f j- = 5ns. 

2. Assume that t RCD g t RC D (max). If t RCD is 
greater than the maximum recommended value 
shown in this table, t R ^c exceeds the value shown. 

3. Measured with a load circuit equivalent to 2TTL 
loads and lOOpF. 

4. Assumes that t R cD - 'RCD (max). 

5. toFF (max) is defined as the time at which the 
output achieves the open circuit condition and is not 
referenced to output voltage levels. 

6. Vnf (min) and Vjl (max) are reference levels for 
measuring timing of input signals. Also, transition 
times are measured between Vjfj and Vj^. 
Operation with the t R cD (max) limit insures that 
'RAC (max) can be met,- t R cD (max) is specified as 
a reference point only, if t R £D is greater than the 
specified t RCD (max) limit, then access time is 
controlled exclusively be t CAC . 



7. 



9. 

10. 
11, 
12. 



'WCS< 'CWD and t R wQ are not restrictive operating 
parameters. They are included in the data sheet as 
electrical characteristics only : if twcS-'wcs (min), 
the cycle is an early write cycle and the data out pin 
will remain open circuit (high impedance) through- 
out the entire cycle; if t^WD ^ 'CWD (min) and 
'r wd - l R WD (min), the cycle is a read/write and 
the data output will contain data read from the 
selected cell; if neither of the above sets of condi- 
tions is satisfied, the condition of the data out (at 
access time) is indeterminate. 

These parameters are referenced to CAS leading edge 

in early write cycles and to WE leading edge in 

delayed write or read-modify-write cycles. 

An initial pause of 100 *is is required after power-up 

followed by a minim um of 8 init ialization of cycles. 

Minimum of 8 CAS before RAS refresh is required 

before using internal refresh counter. 

In delayed write or read-modify-write cycles, OE 

must disable output buffers prior to applying data to 

the device. 



HITACHI 

592 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



-HM50464 Series 



■ TIMING WAVEFORMS 
• READ CYCLE 



RX5- 



CAS- 



-titc ll- 



\ 



Address 2) . ROW (////////) ( 



WIT 



I/O- 



J kn \ 



-wzzz 



High-Z 



iii/iiiiin/)h. 1 t/nim/h 



Note) IZB '■ Don't care 



• EARLY WRITE CYCLE 

KA3- 



CAS- 



Address 



w 777777A 



-lUSH- 



-/c,ts- 



ft'SH- 



t WL S 



/( fr/' ^ 



~tcr\- 



tCAH 



•—.'/llllllllllll, 



° ii ii num . vau- i nput %, •urn 1 1 mi, 



vi 



Notes) 1. CTE : Don't care 
2. ZZS : Don't care 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



593 



HM50464 Seriea 



• DELAYED WRITE CYCLE 

R~A~5- 



CA5- 



-IrC- 



-tRAS- 



-tRCD- 



• Iran 



Address?^ ROW {Qj COLUMN (/ / / / /" 



-IRSH- 



-ICAS- 



-IwCR 



J .1 ICPN -\ 



tCAH 



WE"/ 



1 1 I I I 1 1 1 l\ l/ll/l///, 



™> i/ll/l //AyAiipiNPuft777777777 



-/civi. — 



■IWCH- 



-/IW- 
-tDH- 



-ICRP- 



(OS 



>-tODD 



- LI II III !' 

• READ MODIFY WRITE CYCLE 

RA3- 



via ii inn 

Note)£ZZ) : Don't «re 



CX5- 



-Iff/tS- 



\ 



-IRSH- 



-tCAS- 



-tcsH- 



™ /i / Ills 



IRCS 



»tcAH~ 

— tcWD- 



OPEN 

uoTzn 



t R WO- - 

-* — U-/c/»c 
tRAC HVALID-^ 



CWL 



JUL 



tOAC- 



* 'l Illlh ^J 




v- - hi 1111/ 



— - (DW — 



INPUT 



Villi Ih 




//in, 



# HITACHI N ° te ra: Don't c.r, 
594 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



• RAS ONLY REFRESH CYCLE 



^ '«« 



V//////A 



V/////////////// 



^ Tjrim . : »qw : <///////////////////, 



I/O- 



High-Z 



Notes) 1. DE. WE : Don't care 
2- r7Zi : Don't care 



HIDDEN REFRESH CYCLE 

RAS 



CAS- 



\ 



Address 



MSff fff^H (.4SC fC.4/V| 

^0og ^//// D on'; W//Z ZZZZZL 



1/0- 



High-Z 



BE 



VALID OUTPUT 



ZZZL 



Note) K//J : Don't care 



HITACHI 

Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 595 



HM50464 Series - 



• CAS BEFORE RAS REFRESH CYCLE 

KX3 



css- 



iRPC 



tCSft 



Address 



mmzzmzm uzzZhzzizzzil 



• COUNTER TEST 



CAS- 



REFRESH) ( READ WRITE) /~ 



tape less 



Address/^ 
WE 



TZZZZZZZZZZZK^^YZZZL 



at 



Notes ) 1. Dotted-line Means Read Cycle. 2. K///I : Don't care 



• PAGE MODE READ CYCLE 

(TAB 




Note ) Y/A : Don't care 



HITACHI 

596 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 9 



HMS0464 Series 



PAGE MODE WRITE CYCLE 

RA5 



CAS 




NolelEZ): Don't ore 



• PAGE MODE READ MODIFY WRITE CYCLE 




T 



^wmmmM 



<* '///////////} , 




V777, 

Note) 7771 : l><m't rare 



HITACHI 

Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 5 97 



HMS02S6 Series 



262144-word x 1-bit Dynamic Random Access Memory 

■ FEATURES 

• Industry Standard 16-Pin DIP, 18-Pin PLCC, 16-Pin ZIP 

• Single 5V (±10%) 

• On chip substrate bias generator 

• Low Power: 350m W active, 20m W standby 

• Highspeed: Access Time 120ns/150ns/200ns(max.) 

• Common I/O capability using early write operation 

• Page mode capability 

• TTL compatible 

• 256 refresh cycles • • • (4ms) 

• 3 variations of refresh ■ ■ • RAS only refresh, CAS before RAS refresh, 

Hidden refresh 

■ ORDERING INFORMATION 



Type No. 


Access Time 


Package 


HM50256P-12 
HM50256P-15 
HM50256P-20 


120ns 
150ns 
200ns 


300 mil 16 pin Plastic 
DIP 


HM50256ZP-12 
HM50256ZP-15 
HM50256ZP-20 


120ns 
150ns 
200ns 


16 pin Plastic ZIP 


HM50256CP-12 
HM50256CP-15 
HM50256CP-20 


120ns 
150ns 
200ns 


18 pin PLCC 



■ PIN ARRANGEMENT 

• HM50256P Series 



• HM50256CP Series • HM50256ZP Series 




HM50256P Series 



(DP-16B) 



HM50256CP Series 



(CP-18) 



HM50256ZP Series 



(ZP-16) 



■ PIN DESCRIPTION 



(Top View) 



(Bottom View) 





Address Inputs 


CAS 


Column Address Strobe 


Din 


D>U In 


Dout 


Dsts Out 


RAS 


Row Address Strobe 


WE 


Reed/Write Input 


Vcc 


Power (+5V) 


v„ 


Ground 


A.-A, 


Refresh Address Inputs 



<§r HITACHI 

598 Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300 



HM 50256 Series 



■ BLOCK DIAGRAM 



Generator 



CAS 
Cluck 
Gencrttor 



H tS 
Generator 



U/r- 
IMfn 



Data-la 






IWh-l 





Main Amps 



Mvnv.rv 
\ r ray 



Arrav 



aril-ar™. acU ac~ 









DaiaOui 






Buffer 



[ami 



Memory 
Array 



Row 
Decker 



Memory 
Array 



■ ABSOLUTE MAXIMUM RATINGS 

Voltage on any pin relative to V^ -IV to +7V 

Operating temperature, Ta (Ambient) 0°C to +70°C 

Storage temperature -55° C to +125°C 

Short circuit output current 50mA 

Power dissipation 1W 

■ RECOMMENDED DC OPERATING CONDITIONS (Ta-0 to +70*C) 



Parameter 


Symbol 


min 


typ 


max 


Unit 


Note 


Supply Voltage 


Vcc 


4.5 


5.0 


5.5 


V 


1 


Input H